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Differential D2036

ARM: Add subtarget feature for CRC
ClosedPublic

Authored by bogden on Oct 28 2013, 6:19 AM.

Details

Reviewers
jmolloy
Commits
rL193599: ARM: Add subtarget feature for CRC
Summary

This patch adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend.

Diff Detail

Event Timeline

jmolloy accepted this revision.Oct 28 2013, 7:49 AM

Hi Bernie,

This change looks fairy obvious and looks good to me.

Cheers,

James

rengolin added a comment.Oct 28 2013, 9:29 AM

LGTM, too.

bogden closed this revision.Oct 29 2013, 2:51 AM

Closed by commit rL193599 (authored by @bogden).

Revision Contents

PathSize
lib/
Target/
ARM/
6 lines
4 lines
2 lines
4 lines
MCTargetDesc/
4 lines
test/
MC/
ARM/
19 lines
19 lines

Diff 5192

lib/Target/ARM/ARM.td

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Linesdef FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
"Floating point unit supports single precision only">; "Floating point unit supports single precision only">;
def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
"Enable support for Performance Monitor extensions">; "Enable support for Performance Monitor extensions">;
def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
"Enable support for TrustZone security extensions">; "Enable support for TrustZone security extensions">;
def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
"Enable support for Cryptography extensions", "Enable support for Cryptography extensions",
[FeatureNEON]>; [FeatureNEON]>;
def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
"Enable support for CRC instructions">;
// Some processors have FP multiply-accumulate instructions that don't // Some processors have FP multiply-accumulate instructions that don't
// play nicely with other VFP / NEON instructions, and it's generally better // play nicely with other VFP / NEON instructions, and it's generally better
// to just not use them. // to just not use them.
def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
"Disable VFP / NEON MAC instructions">; "Disable VFP / NEON MAC instructions">;
// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Linesdef ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureMP, FeatureHWDiv, FeatureHWDivARM,
FeatureAvoidPartialCPSR, FeatureAvoidPartialCPSR,
FeatureTrustZone]>; FeatureTrustZone]>;
def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
"Cortex-A53 ARM processors", "Cortex-A53 ARM processors",
[FeatureMP, FeatureHWDiv, FeatureHWDivARM, [FeatureMP, FeatureHWDiv, FeatureHWDivARM,
FeatureTrustZone, FeatureT2XtPk, FeatureTrustZone, FeatureT2XtPk,
FeatureCrypto]>; FeatureCrypto, FeatureCRC]>;
def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
"Cortex-A57 ARM processors", "Cortex-A57 ARM processors",
[FeatureMP, FeatureHWDiv, FeatureHWDivARM, [FeatureMP, FeatureHWDiv, FeatureHWDivARM,
FeatureTrustZone, FeatureT2XtPk, FeatureTrustZone, FeatureT2XtPk,
FeatureCrypto]>; FeatureCrypto, FeatureCRC]>;
def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
"Cortex-R5 ARM processors", "Cortex-R5 ARM processors",
[FeatureSlowFPBrcc, [FeatureSlowFPBrcc,
FeatureHWDiv, FeatureHWDivARM, FeatureHWDiv, FeatureHWDivARM,
FeatureHasSlowFPVMLx, FeatureHasSlowFPVMLx,
FeatureAvoidPartialCPSR, FeatureAvoidPartialCPSR,
FeatureT2XtPk]>; FeatureT2XtPk]>;
▲ Show 20 Lines • Show All 157 Lines • Show Last 20 Lines

lib/Target/ARM/ARMInstrInfo.td

Show First 20 Lines • Show All 215 Lines • ▼ Show 20 Linesdef HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
AssemblerPredicate<"!FeatureVFPOnlySP", AssemblerPredicate<"!FeatureVFPOnlySP",
"double precision VFP">; "double precision VFP">;
def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">; AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
def HasNEON : Predicate<"Subtarget->hasNEON()">, def HasNEON : Predicate<"Subtarget->hasNEON()">,
AssemblerPredicate<"FeatureNEON", "NEON">; AssemblerPredicate<"FeatureNEON", "NEON">;
def HasCrypto : Predicate<"Subtarget->hasCrypto()">, def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
AssemblerPredicate<"FeatureCrypto", "crypto">; AssemblerPredicate<"FeatureCrypto", "crypto">;
def HasCRC : Predicate<"Subtarget->hasCRC()">,
AssemblerPredicate<"FeatureCRC", "crc">;
def HasFP16 : Predicate<"Subtarget->hasFP16()">, def HasFP16 : Predicate<"Subtarget->hasFP16()">,
AssemblerPredicate<"FeatureFP16","half-float">; AssemblerPredicate<"FeatureFP16","half-float">;
def HasDivide : Predicate<"Subtarget->hasDivide()">, def HasDivide : Predicate<"Subtarget->hasDivide()">,
AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">; AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">, def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
AssemblerPredicate<"FeatureT2XtPk", AssemblerPredicate<"FeatureT2XtPk",
▲ Show 20 Lines • Show All 3,795 Lines • ▼ Show 20 Lines
// + CRC32{B,H,W} 0x04C11DB7 // + CRC32{B,H,W} 0x04C11DB7
// + CRC32C{B,H,W} 0x1EDC6F41 // + CRC32C{B,H,W} 0x1EDC6F41
// //
class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
: AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
!strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
[(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
Requires<[IsARM, HasV8]> { Requires<[IsARM, HasV8, HasCRC]> {
bits<4> Rd; bits<4> Rd;
bits<4> Rn; bits<4> Rn;
bits<4> Rm; bits<4> Rm;
let Inst{31-28} = 0b1110; let Inst{31-28} = 0b1110;
let Inst{27-23} = 0b00010; let Inst{27-23} = 0b00010;
let Inst{22-21} = sz; let Inst{22-21} = sz;
let Inst{20} = 0; let Inst{20} = 0;
▲ Show 20 Lines • Show All 1,509 Lines • Show Last 20 Lines

lib/Target/ARM/ARMInstrThumb2.td

Show First 20 Lines • Show All 3,021 Lines • ▼ Show 20 Lines
// + CRC32{B,H,W} 0x04C11DB7 // + CRC32{B,H,W} 0x04C11DB7
// + CRC32C{B,H,W} 0x1EDC6F41 // + CRC32C{B,H,W} 0x1EDC6F41
// //
class T2I_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> class T2I_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
: T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary, : T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary,
!strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"), !strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"),
[(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>, [(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>,
Requires<[IsThumb2, HasV8]> { Requires<[IsThumb2, HasV8, HasCRC]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-21} = 0b010110; let Inst{26-21} = 0b010110;
let Inst{20} = C; let Inst{20} = C;
let Inst{15-12} = 0b1111; let Inst{15-12} = 0b1111;
let Inst{7-6} = 0b10; let Inst{7-6} = 0b10;
let Inst{5-4} = sz; let Inst{5-4} = sz;
} }
▲ Show 20 Lines • Show All 1,565 Lines • Show Last 20 Lines

lib/Target/ARM/ARMSubtarget.h

Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Linesprotected:
bool HasPerfMon; bool HasPerfMon;
/// HasTrustZone - if true, processor supports TrustZone security extensions /// HasTrustZone - if true, processor supports TrustZone security extensions
bool HasTrustZone; bool HasTrustZone;
/// HasCrypto - if true, processor supports Cryptography extensions /// HasCrypto - if true, processor supports Cryptography extensions
bool HasCrypto; bool HasCrypto;
/// HasCRC - if true, processor supports CRC instructions
bool HasCRC;
/// AllowsUnalignedMem - If true, the subtarget allows unaligned memory /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
/// accesses for some types. For details, see /// accesses for some types. For details, see
/// ARMTargetLowering::allowsUnalignedMemoryAccesses(). /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
bool AllowsUnalignedMem; bool AllowsUnalignedMem;
/// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
/// and such) instructions in Thumb2 code. /// and such) instructions in Thumb2 code.
bool Thumb2DSP; bool Thumb2DSP;
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Linespublic:
bool hasARMOps() const { return !NoARM; } bool hasARMOps() const { return !NoARM; }
bool hasVFP2() const { return HasVFPv2; } bool hasVFP2() const { return HasVFPv2; }
bool hasVFP3() const { return HasVFPv3; } bool hasVFP3() const { return HasVFPv3; }
bool hasVFP4() const { return HasVFPv4; } bool hasVFP4() const { return HasVFPv4; }
bool hasFPARMv8() const { return HasFPARMv8; } bool hasFPARMv8() const { return HasFPARMv8; }
bool hasNEON() const { return HasNEON; } bool hasNEON() const { return HasNEON; }
bool hasCrypto() const { return HasCrypto; } bool hasCrypto() const { return HasCrypto; }
bool hasCRC() const { return HasCRC; }
bool useNEONForSinglePrecisionFP() const { bool useNEONForSinglePrecisionFP() const {
return hasNEON() && UseNEONForSinglePrecisionFP; } return hasNEON() && UseNEONForSinglePrecisionFP; }
bool hasDivide() const { return HasHardwareDivide; } bool hasDivide() const { return HasHardwareDivide; }
bool hasDivideInARMMode() const { return HasHardwareDivideInARM; } bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
bool hasT2ExtractPack() const { return HasT2ExtractPack; } bool hasT2ExtractPack() const { return HasT2ExtractPack; }
bool hasDataBarrier() const { return HasDataBarrier; } bool hasDataBarrier() const { return HasDataBarrier; }
bool hasAnyDataBarrier() const { bool hasAnyDataBarrier() const {
▲ Show 20 Lines • Show All 79 Lines • Show Last 20 Lines

lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

Show First 20 Lines • Show All 99 Lines • ▼ Show 20 Linesstd::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
bool NoCPU = CPU == "generic" || CPU.empty(); bool NoCPU = CPU == "generic" || CPU.empty();
std::string ARMArchFeature; std::string ARMArchFeature;
if (Idx) { if (Idx) {
unsigned SubVer = TT[Idx]; unsigned SubVer = TT[Idx];
if (SubVer == '8') { if (SubVer == '8') {
if (NoCPU) if (NoCPU)
// v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2, FeatureMP, // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2, FeatureMP,
// FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone, FeatureT2XtPk, FeatureCrypto // FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone, FeatureT2XtPk, FeatureCrypto, FeatureCRC
ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,+trustzone,+t2xtpk,+crypto"; ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,+trustzone,+t2xtpk,+crypto,+crc";
else else
// Use CPU to figure out the exact features // Use CPU to figure out the exact features
ARMArchFeature = "+v8"; ARMArchFeature = "+v8";
} else if (SubVer == '7') { } else if (SubVer == '7') {
if (Len >= Idx+2 && TT[Idx+1] == 'm') { if (Len >= Idx+2 && TT[Idx+1] == 'm') {
isThumb = true; isThumb = true;
if (NoCPU) if (NoCPU)
// v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
▲ Show 20 Lines • Show All 254 Lines • Show Last 20 Lines

test/MC/ARM/crc32-thumb.s

@ RUN: llvm-mc -triple=thumbv8 -show-encoding < %s | FileCheck %s @ RUN: llvm-mc -triple=thumbv8 -show-encoding < %s | FileCheck %s
@ RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7 @ RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
@ RUN: not llvm-mc -triple=thumbv8 -mattr=-crc -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOCRC
crc32b r0, r1, r2 crc32b r0, r1, r2
crc32h r0, r1, r2 crc32h r0, r1, r2
crc32w r0, r1, r2 crc32w r0, r1, r2
@ CHECK: crc32b r0, r1, r2 @ encoding: [0xc1,0xfa,0x82,0xf0] @ CHECK: crc32b r0, r1, r2 @ encoding: [0xc1,0xfa,0x82,0xf0]
@ CHECK: crc32h r0, r1, r2 @ encoding: [0xc1,0xfa,0x92,0xf0] @ CHECK: crc32h r0, r1, r2 @ encoding: [0xc1,0xfa,0x92,0xf0]
@ CHECK: crc32w r0, r1, r2 @ encoding: [0xc1,0xfa,0xa2,0xf0] @ CHECK: crc32w r0, r1, r2 @ encoding: [0xc1,0xfa,0xa2,0xf0]
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
crc32cb r0, r1, r2 crc32cb r0, r1, r2
crc32ch r0, r1, r2 crc32ch r0, r1, r2
crc32cw r0, r1, r2 crc32cw r0, r1, r2
@ CHECK: crc32cb r0, r1, r2 @ encoding: [0xd1,0xfa,0x82,0xf0] @ CHECK: crc32cb r0, r1, r2 @ encoding: [0xd1,0xfa,0x82,0xf0]
@ CHECK: crc32ch r0, r1, r2 @ encoding: [0xd1,0xfa,0x92,0xf0] @ CHECK: crc32ch r0, r1, r2 @ encoding: [0xd1,0xfa,0x92,0xf0]
@ CHECK: crc32cw r0, r1, r2 @ encoding: [0xd1,0xfa,0xa2,0xf0] @ CHECK: crc32cw r0, r1, r2 @ encoding: [0xd1,0xfa,0xa2,0xf0]
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc

test/MC/ARM/crc32.s

@ RUN: llvm-mc -triple=armv8 -show-encoding < %s | FileCheck %s @ RUN: llvm-mc -triple=armv8 -show-encoding < %s | FileCheck %s
@ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7 @ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
@ RUN: not llvm-mc -triple=thumbv8 -mattr=-crc -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOCRC
crc32b r0, r1, r2 crc32b r0, r1, r2
crc32h r0, r1, r2 crc32h r0, r1, r2
crc32w r0, r1, r2 crc32w r0, r1, r2
@ CHECK: crc32b r0, r1, r2 @ encoding: [0x42,0x00,0x01,0xe1] @ CHECK: crc32b r0, r1, r2 @ encoding: [0x42,0x00,0x01,0xe1]
@ CHECK: crc32h r0, r1, r2 @ encoding: [0x42,0x00,0x21,0xe1] @ CHECK: crc32h r0, r1, r2 @ encoding: [0x42,0x00,0x21,0xe1]
@ CHECK: crc32w r0, r1, r2 @ encoding: [0x42,0x00,0x41,0xe1] @ CHECK: crc32w r0, r1, r2 @ encoding: [0x42,0x00,0x41,0xe1]
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
crc32cb r0, r1, r2 crc32cb r0, r1, r2
crc32ch r0, r1, r2 crc32ch r0, r1, r2
crc32cw r0, r1, r2 crc32cw r0, r1, r2
@ CHECK: crc32cb r0, r1, r2 @ encoding: [0x42,0x02,0x01,0xe1] @ CHECK: crc32cb r0, r1, r2 @ encoding: [0x42,0x02,0x01,0xe1]
@ CHECK: crc32ch r0, r1, r2 @ encoding: [0x42,0x02,0x21,0xe1] @ CHECK: crc32ch r0, r1, r2 @ encoding: [0x42,0x02,0x21,0xe1]
@ CHECK: crc32cw r0, r1, r2 @ encoding: [0x42,0x02,0x41,0xe1] @ CHECK: crc32cw r0, r1, r2 @ encoding: [0x42,0x02,0x41,0xe1]
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc