AMDGPU: Simplify control flow / conditions

[rivanvx]

LGTM

[arsenm]

r268676

lib/Target/AMDGPU/SIISelLowering.cpp

if (CallConv == CallingConv::AMDGPU_PS && !Arg.Flags.isInReg() &&
 
       Info->markPSInputAllocated(PSInputNum);
       if (Arg.Used)
         Info->PSInputEna |= 1 << PSInputNum;
 
       ++PSInputNum;
     }
 
+    if (AMDGPU::isShader(CallConv)) {
       // Second split vertices into their elements
-    if (AMDGPU::isShader(CallConv) &&
-        Arg.VT.isVector()) {
+      if (Arg.VT.isVector()) {
         ISD::InputArg NewArg = Arg;
         NewArg.Flags.setSplit();
         NewArg.VT = Arg.VT.getVectorElementType();
 
         // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
         // three or five element vertex only needs three or five registers,
         // NOT four or eight.
         Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
         unsigned NumElements = ParamType->getVectorNumElements();
 
         for (unsigned j = 0; j != NumElements; ++j) {
           Splits.push_back(NewArg);
           NewArg.PartOffset += NewArg.VT.getStoreSize();
         }
-
-    } else if (AMDGPU::isShader(CallConv)) {
+      } else {
         Splits.push_back(Arg);
       }
     }
+  }
 
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
                  *DAG.getContext());
 
   // At least one interpolation mode must be enabled or else the GPU will hang.
   //
   // Check PSInputAddr instead of PSInputEna. The idea is that if the user set