[NVPTX] Fix sign/zero-extending ldg/ldu instruction selection

[jholewinski]

Summary

We don't have sign-/zero-extending ldg/ldu instructions defined,
so we need to emulate them with explicit CVTs. We were originally
handling the i8 case, but not any other cases.

Fixes PR26185

[jholewinski]

Just putting this up for Tobias to try... test case incoming.

[grosser]

Hi Justin,

thank you for this fix. This resolves the problem I have seen earlier.

[jingyue]

Awesome! Thanks Justin.

lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

2080

The giant if-switch below may be simplified by

DestType = OrigType.getSimpleVT().SimpleTy;
if (SizeOf(EltVT) < SizeOf(DestType)) {
  CvtOpc = GetConvertOpcode(EltVT, DestType);
  ...
}

[jholewinski]

lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

2080

You're suggesting pulling the logic out into a utility function? Or am I just missing your point?

[jingyue]

lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

2080

Yes, I am suggesting some refactoring.

[jholewinski]

Refactor opcode selection into utility function and add test case

[jingyue]

Looks great! Thanks.

lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

5292

You can directly return IsSigned ? ... : ... so you don't need break for each case.

lib/Target/NVPTX/NVPTXISelDAGToDAG.h

96 ↗

(On Diff #55470)

Is this method static?

[jholewinski]

Address review comments

lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(SDNode *N) {
   MemRefs0[0] = Mem->getMemOperand();
   cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
 
   // For automatic generation of LDG (through SelectLoad[Vector], not the
   // intrinsics), we may have an extending load like:
   //
   //   i32,ch = load<LD1[%data1(addrspace=1)], zext from i8> t0, t7, undef:i64
   //
-  // Since we load an i8 value, the matching logic above will have selected an
-  // LDG instruction that reads i8 and stores it in an i16 register (NVPTX does
-  // not expose 8-bit registers):
-  //
-  //   i16,ch = INT_PTX_LDG_GLOBAL_i8areg64 t7, t0
-  //
-  // To get the correct type in this case, truncate back to i8 and then extend
-  // to the original load type.
+  // In this case, the matching logic above will select a load for the original
+  // memory type (in this case, i8) and our types will not match (the node needs
+  // to return an i32 in this case). Our LDG/LDU nodes do not support the
+  // concept of sign-/zero-extension, so emulate it here by adding an explicit
+  // CVT instruction. Ptxas should clean up any redundancies here.
+
   EVT OrigType = N->getValueType(0);
-  LoadSDNode *LDSD = dyn_cast<LoadSDNode>(N);
-  if (LDSD && EltVT == MVT::i8 && OrigType.getScalarSizeInBits() >= 32) {
+  LoadSDNode *LdNode = dyn_cast<LoadSDNode>(N);
+
+  if (OrigType != EltVT && LdNode) {
+    // We have an extending-load. The instruction we selected operates on the
+    // smaller type, but the SDNode we are replacing has the larger type. We
+    // need to emit a CVT to make the types match.
     unsigned CvtOpc = 0;
 
-    switch (LDSD->getExtensionType()) {
+    if (EltVT == MVT::i8) {
+      switch (LdNode->getExtensionType()) {
       default:
-      llvm_unreachable("An extension is required for i8 loads");
+        llvm_unreachable("Unknown load extension");
         break;
       case ISD::SEXTLOAD:
         switch (OrigType.getSimpleVT().SimpleTy) {
         default:
           llvm_unreachable("Unhandled integer load type");
           break;
+        case MVT::i16:
+          CvtOpc = NVPTX::CVT_s16_s8;
+          break;
         case MVT::i32:
           CvtOpc = NVPTX::CVT_s32_s8;
           break;
         case MVT::i64:
           CvtOpc = NVPTX::CVT_s64_s8;
           break;
         }
         break;
       case ISD::EXTLOAD:
       case ISD::ZEXTLOAD:
         switch (OrigType.getSimpleVT().SimpleTy) {
         default:
           llvm_unreachable("Unhandled integer load type");
           break;
+        case MVT::i16:
+          CvtOpc = NVPTX::CVT_u16_u8;
+          break;
         case MVT::i32:
           CvtOpc = NVPTX::CVT_u32_u8;
           break;
         case MVT::i64:
           CvtOpc = NVPTX::CVT_u64_u8;
           break;
         }
         break;
       }
+    } else if (EltVT == MVT::i16) {
+      switch (LdNode->getExtensionType()) {
+      default:
+        llvm_unreachable("Unknown load extension");
+        break;
+      case ISD::SEXTLOAD:
+        switch (OrigType.getSimpleVT().SimpleTy) {
+        default:
+          llvm_unreachable("Unhandled integer load type");
+          break;
+        case MVT::i32:
+          CvtOpc = NVPTX::CVT_s32_s16;
+          break;
+        case MVT::i64:
+          CvtOpc = NVPTX::CVT_s64_s16;
+          break;
+        }
+        break;
+      case ISD::EXTLOAD:
+      case ISD::ZEXTLOAD:
+        switch (OrigType.getSimpleVT().SimpleTy) {
+        default:
+          llvm_unreachable("Unhandled integer load type");
+          break;
+        case MVT::i32:
+          CvtOpc = NVPTX::CVT_u32_u16;
+          break;
+        case MVT::i64:
+          CvtOpc = NVPTX::CVT_u64_u16;
+          break;
+        }
+        break;
+      }
+    } else if (EltVT == MVT::i32) {
+      switch (LdNode->getExtensionType()) {
+      default:
+        llvm_unreachable("Unknown load extension");
+        break;
+      case ISD::SEXTLOAD:
+        switch (OrigType.getSimpleVT().SimpleTy) {
+        default:
+          llvm_unreachable("Unhandled integer load type");
+          break;
+        case MVT::i64:
+          CvtOpc = NVPTX::CVT_s64_s32;
+          break;
+        }
+        break;
+      case ISD::EXTLOAD:
+      case ISD::ZEXTLOAD:
+        switch (OrigType.getSimpleVT().SimpleTy) {
+        default:
+          llvm_unreachable("Unhandled integer load type");
+          break;
+        case MVT::i64:
+          CvtOpc = NVPTX::CVT_u64_u32;
+          break;
+        }
+        break;
+      }
+    } else {
+      llvm_unreachable("Extending load of invalid base type");
+    }
 
-    // For each output value, truncate to i8 (since the upper 8 bits are
-    // undefined) and then extend to the desired type.
+    // For each output value, apply the manual sign/zero-extension and make sure
+    // all users of the load go through that CVT.
     for (unsigned i = 0; i != NumElts; ++i) {
       SDValue Res(LD, i);
       SDValue OrigVal(N, i);
 
       SDNode *CvtNode =
         CurDAG->getMachineNode(CvtOpc, DL, OrigType, Res,
-                               CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE, DL, MVT::i32));
+                               CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE,
+                                                         DL, MVT::i32));
       ReplaceUses(OrigVal, SDValue(CvtNode, 0));
     }
   }
 
   return LD;
 }
 
 SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) {
case InlineAsm::Constraint_m: // memory
     if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
       OutOps.push_back(Op0);
       OutOps.push_back(Op1);
       return false;
     }
     break;
   }
   return true;
 }