[SystemZ] Add SVC instruction.

[• koriakin]

Summary

This is going to be useful for inline assembly only.

[uweigand]

While this is not for CodeGen, I think for the benefit of analysis tools (e.g. LLDB) the pattern should still be marked with the appropriate flags, at least something like "isCall = 1, Defs = [CC]". Not sure if hasSideEffects is necessary, but it probably cannot hurt to add it as well.

Otherweise the patch looks good.

[• koriakin]

Added hasSideEffects = 1, Defs = [CC], isCall = 1.

[uweigand]

LGTM, I'll check it in.

lib/Target/SystemZ/SystemZInstrFormats.td

 //   bits<4> Mn   : mode value for operand n
 //
 // The operand numbers ("n" in the list above) follow the architecture manual.
 // Assembly operands sometimes have a different order; in particular, R3 often
 // is often written between operands 1 and 2.
 //
 //===----------------------------------------------------------------------===//
 
+class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSystemZ<2, outs, ins, asmstr, pattern> {
+  field bits<16> Inst;
+  field bits<16> SoftFail = 0;
+
+  bits<8> I1;
+
+  let Inst{15-8} = op;
+  let Inst{7-0}  = I1;
+}
+
 class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
   field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<16> I2;
 

lib/Target/SystemZ/SystemZInstrInfo.td

let usesCustomInserter = 1 in {
   def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
 }
 
 // Search a block of memory for a character.
 let mayLoad = 1, Defs = [CC] in
   defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
 
 // Other instructions for inline assembly
+def SVC : InstI<0x0A, (outs), (ins imm32zx8:$I1),
+                "svc\t$I1",
+                []>;
 let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
   def STCK : InstS<0xB205, (outs), (ins bdaddr12only:$BD2),
                        "stck\t$BD2",
                        []>;
 let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
   def STCKF : InstS<0xB27C, (outs), (ins bdaddr12only:$BD2),
                        "stckf\t$BD2",
                        []>;

test/MC/Disassembler/SystemZ/insns.txt

 0xe3 0x01 0xff 0xff 0x7f 0x50
 
 # CHECK: sty %r0, 524287(%r15,%r1)
 0xe3 0x0f 0x1f 0xff 0x7f 0x50
 
 # CHECK: sty %r15, 0
 0xe3 0xf0 0x00 0x00 0x00 0x50
 
+# CHECK: svc 0
+0x0a 0x00
+
+# CHECK: svc 3
+0x0a 0x03
+
+# CHECK: svc 128
+0x0a 0x80
+
+# CHECK: svc 255
+0x0a 0xff
+
 # CHECK: sxbr %f0, %f0
 0xb3 0x4b 0x00 0x00
 
 # CHECK: sxbr %f0, %f13
 0xb3 0x4b 0x00 0x0d
 
 # CHECK: sxbr %f8, %f8
 0xb3 0x4b 0x00 0x88

test/MC/SystemZ/insn-good.s

#CHECK: strvg %r15, 0                 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x2f]
   strvg %r0,1
   strvg %r0,524287
   strvg %r0,0(%r1)
   strvg %r0,0(%r15)
   strvg %r0,524287(%r1,%r15)
   strvg %r0,524287(%r15,%r1)
   strvg %r15,0
 
+#CHECK: svc 0     # encoding: [0x0a,0x00]
+#CHECK: svc 3     # encoding: [0x0a,0x03]
+#CHECK: svc 128     # encoding: [0x0a,0x80]
+#CHECK: svc 255     # encoding: [0x0a,0xff]
+
+  svc 0
+  svc 3
+  svc 128
+  svc 0xff
+
 #CHECK: sty %r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x50]
 #CHECK: sty %r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x50]
 #CHECK: sty %r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x50]
 #CHECK: sty %r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x50]
 #CHECK: sty %r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x50]
 #CHECK: sty %r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x50]
 #CHECK: sty %r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x50]
 #CHECK: sty %r0, 524287(%r1,%r15)   # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x50]