TableGen: Add hasNoSchedulingInfo flag to instructions

[MatzeB]

Summary

This introduces a new flag that indicates that a specific instruction will never be present when the MachineScheduler runs and therefore needs no scheduling information.

This is in preparation for an upcoming commit which checks completeness of a scheduling model when tablegen runs.

[atrick]

I had the same idea when adding the "Unsupported" flag to the ProcWriteResources template. It emits InvalidNumMicroOps, so you can use the API SchedModel.getSchedClassDesc(SchedClassIdx).isValid().

The idea was that some subtargets support only a subset of the ISA.

Do we really need to add a scheduling specific flag to tablegen Instruction class too?

[MatzeB]

In D17728#364714, @atrick wrote:

I had the same idea when adding the "Unsupported" flag to the ProcWriteResources template. It emits InvalidNumMicroOps, so you can use the API SchedModel.getSchedClassDesc(SchedClassIdx).isValid().

The idea was that some subtargets support only a subset of the ISA.

Do we really need to add a scheduling specific flag to tablegen Instruction class too?

The problem with Unsupproted is that it forces us to list the unsupported instructions in each scheduling model again. We've got a bunch of generic instructions which we will never even encounter when the scheduler is running (e.g. PHI, EXTRACT_SUBREG, INSERT_SUBREG, STACKMAP) or for which we deliberately do not want to create scheduling info because they will not result in machine instructions (DBG_VALUE, IMPLICIT_DEF, KILL, LIFETIME_START, LIFETIME_END).
None of the existing instruction flags appears to match exactly these cases, (the closes existing thing is isPseudo and isCodeGenOnly, but both have examples where we still want scheduling information; e.g. COPY has isPseudo and isCodeGenOnly set but we still want scheduling information for it.

After our discussion I thought about introducing a new flag for instructions that do not result in machine instructions after all, but this won't catch this case either, because for example EXTRACT_SUBREG, INSERT_SUBREG do actually result in machine instruction but we still don't want to ever include them into the scheduling model because they are lowered early enough.

So is it okay to add this flag is specifically about the instruction being included in the scheduling model?

[atrick]

Yes, that makes sense.

include/llvm/Target/Target.td

class Instruction {
   //   CodeEmitter unchanged, but duplicates a canonical instruction
   //   definition's encoding and should be ignored when constructing the
   //   assembler match tables.
   bit isCodeGenOnly = 0;
 
   // Is this instruction a pseudo instruction for use by the assembler parser.
   bit isAsmParserOnly = 0;
 
+  // This instruction is not expected to be queried for scheduling latencies
+  // and therefore needs no scheduling information even for a complete
+  // scheduling model.
+  bit hasNoSchedulingInfo = 0;
+
   InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
 
   // Scheduling information from TargetSchedule.td.
   list<SchedReadWrite> SchedRW;
 
   string Constraints = "";  // OperandConstraint, e.g. $src = $dst.
 
   /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
class InstrInfo {
   // generator has better support for complex operands and targets have
   // migrated away from using positionally encoded operands.
   bit noNamedPositionallyEncodedOperands = 0;
 }
 
 // Standard Pseudo Instructions.
 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
 // Only these instructions are allowed in the TargetOpcode namespace.
-let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
+let isCodeGenOnly = 1, isPseudo = 1, hasNoSchedulingInfo = 1,
+    Namespace = "TargetOpcode" in {
 def PHI : Instruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "PHINODE";
 }
 def INLINEASM : Instruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
def REG_SEQUENCE : Instruction {
   let isAsCheapAsAMove = 1;
 }
 def COPY : Instruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins unknown:$src);
   let AsmString = "";
   let hasSideEffects = 0;
   let isAsCheapAsAMove = 1;
+  let hasNoSchedulingInfo = 0;
 }
 def BUNDLE : Instruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "BUNDLE";
 }
 def LIFETIME_START : Instruction {
   let OutOperandList = (outs);

utils/TableGen/CodeGenInstruction.h

public:
     bool hasExtraSrcRegAllocReq : 1;
     bool hasExtraDefRegAllocReq : 1;
     bool isCodeGenOnly : 1;
     bool isPseudo : 1;
     bool isRegSequence : 1;
     bool isExtractSubreg : 1;
     bool isInsertSubreg : 1;
     bool isConvergent : 1;
+    bool hasNoSchedulingInfo : 1;
 
     std::string DeprecatedReason;
     bool HasComplexDeprecationPredicate;
 
     /// Are there any undefined flags?
     bool hasUndefFlags() const {
       return mayLoad_Unset || mayStore_Unset || hasSideEffects_Unset;
     }

utils/TableGen/CodeGenInstruction.cpp

CodeGenInstruction::CodeGenInstruction(Record *R)
   usesCustomInserter = R->getValueAsBit("usesCustomInserter");
   hasPostISelHook = R->getValueAsBit("hasPostISelHook");
   hasCtrlDep   = R->getValueAsBit("hasCtrlDep");
   isNotDuplicable = R->getValueAsBit("isNotDuplicable");
   isRegSequence = R->getValueAsBit("isRegSequence");
   isExtractSubreg = R->getValueAsBit("isExtractSubreg");
   isInsertSubreg = R->getValueAsBit("isInsertSubreg");
   isConvergent = R->getValueAsBit("isConvergent");
+  hasNoSchedulingInfo = R->getValueAsBit("hasNoSchedulingInfo");
 
   bool Unset;
   mayLoad      = R->getValueAsBitOrUnset("mayLoad", Unset);
   mayLoad_Unset = Unset;
   mayStore     = R->getValueAsBitOrUnset("mayStore", Unset);
   mayStore_Unset = Unset;
   hasSideEffects = R->getValueAsBitOrUnset("hasSideEffects", Unset);
   hasSideEffects_Unset = Unset;

utils/TableGen/CodeGenSchedule.cpp

void CodeGenSchedModels::collectSchedClasses() {
   DEBUG(EnableDump = true);
   if (!EnableDump)
     return;
 
   for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
     std::string InstName = Inst->TheDef->getName();
     unsigned SCIdx = InstrClassMap.lookup(Inst->TheDef);
     if (!SCIdx) {
+      if (!Inst->hasNoSchedulingInfo)
         dbgs() << "No machine model for " << Inst->TheDef->getName() << '\n';
       continue;
     }
     CodeGenSchedClass &SC = getSchedClass(SCIdx);
     if (SC.ProcIndices[0] != 0)
       PrintFatalError(Inst->TheDef->getLoc(), "Instruction's sched class "
                       "must not be subtarget specific.");
 
     IdxVec ProcIndices;