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Differential D16485

AMDGPU/SI: Stoney has only 16 LDS banks
ClosedPublic

Authored by mareko on Jan 22 2016, 1:15 PM.

Details

Reviewers
• tstellarAMD
Commits
rG92b4e31b11cc: Merging r258922:
rGe86f252209a3: AMDGPU/SI: Stoney has only 16 LDS banks
rL258922: AMDGPU/SI: Stoney has only 16 LDS banks
Summary

This is a candidate for stable, along with all patches that add the "stoney"
processor.

Diff Detail

Event Timeline

mareko updated this revision to Diff 45732.Jan 22 2016, 1:15 PM
mareko retitled this revision from to AMDGPU/SI: Stoney has only 16 LDS banks.
mareko updated this object.
mareko added a reviewer: • tstellarAMD.
Herald added a subscriber: arsenm. · View Herald TranscriptJan 22 2016, 1:15 PM
• tstellarAMD accepted this revision.Jan 25 2016, 8:57 AM
• tstellarAMD edited edge metadata.

LGTM

This revision is now accepted and ready to land.Jan 25 2016, 8:57 AM
Closed by commit rL258922: AMDGPU/SI: Stoney has only 16 LDS banks (authored by mareko). · Explain WhyJan 27 2016, 3:23 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
2 lines
12 lines
test/
CodeGen/
AMDGPU/
1 line

Diff 45732

lib/Target/AMDGPU/AMDGPU.td

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def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS", def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536, [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace, FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
FeatureGCN1Encoding, FeatureCIInsts]>; FeatureGCN1Encoding, FeatureCIInsts]>;
def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS", def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536, [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN, FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
FeatureGCN3Encoding, FeatureCIInsts, FeatureLDSBankCount32]>; FeatureGCN3Encoding, FeatureCIInsts]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def AMDGPUInstrInfo : InstrInfo { def AMDGPUInstrInfo : InstrInfo {
let guessInstructionProperties = 1; let guessInstructionProperties = 1;
let noNamedPositionallyEncodedOperands = 1; let noNamedPositionallyEncodedOperands = 1;
} }
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lib/Target/AMDGPU/Processors.td

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def : ProcessorModel<"mullins", SIQuarterSpeedModel, def : ProcessorModel<"mullins", SIQuarterSpeedModel,
[FeatureSeaIslands, FeatureLDSBankCount16]>; [FeatureSeaIslands, FeatureLDSBankCount16]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Volcanic Islands // Volcanic Islands
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : ProcessorModel<"tonga", SIQuarterSpeedModel, def : ProcessorModel<"tonga", SIQuarterSpeedModel,
[FeatureVolcanicIslands, FeatureSGPRInitBug, FeatureISAVersion8_0_0] [FeatureVolcanicIslands, FeatureSGPRInitBug, FeatureISAVersion8_0_0,
FeatureLDSBankCount32]
>; >;
def : ProcessorModel<"iceland", SIQuarterSpeedModel, def : ProcessorModel<"iceland", SIQuarterSpeedModel,
[FeatureVolcanicIslands, FeatureSGPRInitBug, FeatureISAVersion8_0_0] [FeatureVolcanicIslands, FeatureSGPRInitBug, FeatureISAVersion8_0_0,
FeatureLDSBankCount32]
>; >;
def : ProcessorModel<"carrizo", SIQuarterSpeedModel, def : ProcessorModel<"carrizo", SIQuarterSpeedModel,
[FeatureVolcanicIslands, FeatureISAVersion8_0_1] [FeatureVolcanicIslands, FeatureISAVersion8_0_1, FeatureLDSBankCount32]
>; >;
def : ProcessorModel<"fiji", SIQuarterSpeedModel, def : ProcessorModel<"fiji", SIQuarterSpeedModel,
[FeatureVolcanicIslands, FeatureISAVersion8_0_3] [FeatureVolcanicIslands, FeatureISAVersion8_0_3, FeatureLDSBankCount32]
>; >;
def : ProcessorModel<"stoney", SIQuarterSpeedModel, def : ProcessorModel<"stoney", SIQuarterSpeedModel,
[FeatureVolcanicIslands, FeatureISAVersion8_0_1] [FeatureVolcanicIslands, FeatureISAVersion8_0_1, FeatureLDSBankCount16]
>; >;

test/CodeGen/AMDGPU/llvm.SI.fs.interp.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
;RUN: llc < %s -march=amdgcn -mcpu=kabini -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s ;RUN: llc < %s -march=amdgcn -mcpu=kabini -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s
;RUN: llc < %s -march=amdgcn -mcpu=stoney -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
;GCN-LABEL: {{^}}main: ;GCN-LABEL: {{^}}main:
;GCN-NOT: s_wqm ;GCN-NOT: s_wqm
;GCN: s_mov_b32 ;GCN: s_mov_b32
;GCN-NEXT: v_interp_mov_f32 ;GCN-NEXT: v_interp_mov_f32
;GCN: v_interp_p1_f32 ;GCN: v_interp_p1_f32
;GCN: v_interp_p2_f32 ;GCN: v_interp_p2_f32
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