[ELF] Add AMDGPU support

[• tstellarAMD]

Summary

This will allow us to remove the AMDGPU support from old ELF.

[ruiu]

This patch itself seems simple, but I don't know the reason of each change. A description for each change would be greatly appreciated.

ELF/Driver.cpp

246

Why is AMDGPU special for this if?

ELF/OutputSections.cpp

789–790

Why is this needed?

1295

Ditto

ELF/Target.cpp

1272

{ } -> {}

(Please run clang-format for this patch.)

ELF/Writer.cpp

840

unsigned -> uint32_t.

This function needs a brief comment to describe why AMDGPU is special.

[• tstellarAMD]

Added comments explaining changes.

[ruiu]

ELF/Driver.cpp

248

Then the check should be added here, no?

ELF/OutputSections.cpp

789

It still looks odd since the value does not include section's address, but I guess there's a reason for that. Is there a spec or something for this? Please add a link if the document is available.

[• tstellarAMD]

Clarify a comment and move EM_AMDGPU check.

[• tstellarAMD]

ELF/OutputSections.cpp

789

I have clarified this comment in the latest revision, but offsets stored in a symbol's st_value field for AMDGPU need to be byte offsets from the start of the section. So the section address needs to be ignored when computing the offset.

There is a document specifying this object format. I have been working with people internally to get it released, I will add it to the documents once it is available.

[ruiu]

ELF/Driver.cpp

251

If -e doesn't make sense for AMDGPU, should we treat it an error if a user specifies -e for AMDGPU?

ELF/Writer.cpp

904–905

I think this is slightly better since readers don't have to read the subroutine unless they are interested in AMDGPU.

uint32_t PTType = (Config->Emachine != EM_AMDGPU) ? PT_LOAD : getAmdgpuPhdr();

[• tstellarAMD]

Prevent -e from being used with AMDGPU, simplify some other code.

[ruiu]

LGTM

ELF/Writer.cpp

843

Remove this empty line.

847

Ditto

850

Ditto

ELF/Driver.cpp

void LinkerDriver::createFiles(opt::InputArgList &Args) {
   if (Config->GnuHash && Config->EMachine == EM_MIPS)
     error("The .gnu.hash section is not compatible with the MIPS target.");
 }
 
 template <class ELFT> void LinkerDriver::link(opt::InputArgList &Args) {
   SymbolTable<ELFT> Symtab;
   Target.reset(createTarget());
 
-  if (!Config->Shared) {
+  if (!Config->Shared && Config->EMachine != EM_AMDGPU) {
     // Add entry symbol.
     if (Config->Entry.empty())
       Config->Entry = (Config->EMachine == EM_MIPS) ? "__start" : "_start";
 
     // In the assembly for 32 bit x86 the _GLOBAL_OFFSET_TABLE_ symbol
     // is magical and is used to produce a R_386_GOTPC relocation.
     // The R_386_GOTPC relocation value doesn't actually depend on the
     // symbol value, so it could use an index of STN_UNDEF which, according
     // to the spec, means the symbol value is 0.
     // Unfortunately both gas and MC keep the _GLOBAL_OFFSET_TABLE_ symbol in
     // the object file.
     // The situation is even stranger on x86_64 where the assembly doesn't
     // need the magical symbol, but gas still puts _GLOBAL_OFFSET_TABLE_ as

ELF/OutputSections.cpp

case SymbolBody::DefinedSyntheticKind: {
     auto &D = cast<DefinedSynthetic<ELFT>>(S);
     return D.Section.getVA() + D.Sym.st_value;
   }
   case SymbolBody::DefinedAbsoluteKind:
     return cast<DefinedAbsolute<ELFT>>(S).Sym.st_value;
   case SymbolBody::DefinedRegularKind: {
     const auto &DR = cast<DefinedRegular<ELFT>>(S);
     InputSectionBase<ELFT> &SC = DR.Section;
+    if (Config->EMachine == EM_AMDGPU)
+      return SC.getOffset(DR.Sym);
     if (DR.Sym.getType() == STT_TLS)
       return SC.OutSec->getVA() + SC.getOffset(DR.Sym) -
              Out<ELFT>::TlsPhdr->p_vaddr;
     return SC.OutSec->getVA() + SC.getOffset(DR.Sym);
   }
   case SymbolBody::DefinedCommonKind:
     return Out<ELFT>::Bss->getVA() + cast<DefinedCommon<ELFT>>(S).OffsetInBSS;
   case SymbolBody::SharedKind: {
for (const Elf_Sym &Sym : Syms) {
         ESym->st_shndx = SHN_ABS;
         VA = Sym.st_value;
       } else {
         InputSectionBase<ELFT> *Section = File->getSection(Sym);
         if (!Section->isLive())
           continue;
         const OutputSectionBase<ELFT> *OutSec = Section->OutSec;
         ESym->st_shndx = OutSec->SectionIndex;
-        VA += OutSec->getVA() + Section->getOffset(Sym);
+        VA = Section->getOffset(Sym);
+        if (Config->EMachine != EM_AMDGPU)
+          VA += OutSec->getVA();
       }
       ESym->st_name = StrTabSec.getOffset(SymName);
       ESym->st_size = Sym.st_size;
       ESym->setBindingAndType(Sym.getBinding(), Sym.getType());
       ESym->st_value = VA;
       Buf += sizeof(*ESym);
     }
   }

ELF/Target.cpp

public:
   bool relocNeedsCopy(uint32_t Type, const SymbolBody &S) const override;
   bool relocNeedsGot(uint32_t Type, const SymbolBody &S) const override;
   bool relocNeedsPlt(uint32_t Type, const SymbolBody &S) const override;
   void relocateOne(uint8_t *Loc, uint8_t *BufEnd, uint32_t Type, uint64_t P,
                    uint64_t SA, uint64_t ZA = 0,
                    uint8_t *PairedLoc = nullptr) const override;
 };
 
+class AMDGPUTargetInfo final : public TargetInfo {
+public:
+  AMDGPUTargetInfo();
+  void writeGotPltEntry(uint8_t *Buf, uint64_t Plt) const override;
+  void writePltZeroEntry(uint8_t *Buf, uint64_t GotEntryAddr,
+                         uint64_t PltEntryAddr) const override;
+  void writePltEntry(uint8_t *Buf, uint64_t GotAddr, uint64_t GotEntryAddr,
+                     uint64_t PltEntryAddr, int32_t Index,
+                     unsigned RelOff) const override;
+  bool relocNeedsGot(uint32_t Type, const SymbolBody &S) const override;
+  bool relocNeedsPlt(uint32_t Type, const SymbolBody &S) const override;
+  void relocateOne(uint8_t *Loc, uint8_t *BufEnd, uint32_t Type, uint64_t P,
+                   uint64_t SA, uint64_t ZA = 0,
+                   uint8_t *PairedLoc = nullptr) const override;
+};
+
 template <class ELFT> class MipsTargetInfo final : public TargetInfo {
 public:
   MipsTargetInfo();
   void writeGotHeaderEntries(uint8_t *Buf) const override;
   void writeGotPltEntry(uint8_t *Buf, uint64_t Plt) const override;
   void writePltZeroEntry(uint8_t *Buf, uint64_t GotEntryAddr,
                          uint64_t PltEntryAddr) const override;
   void writePltEntry(uint8_t *Buf, uint64_t GotAddr, uint64_t GotEntryAddr,
                      uint64_t PltEntryAddr, int32_t Index,
                      unsigned RelOff) const override;
   bool relocNeedsGot(uint32_t Type, const SymbolBody &S) const override;
   bool relocNeedsPlt(uint32_t Type, const SymbolBody &S) const override;
   void relocateOne(uint8_t *Loc, uint8_t *BufEnd, uint32_t Type, uint64_t P,
                    uint64_t SA, uint64_t ZA = 0,
                    uint8_t *PairedLoc = nullptr) const override;
 };
 } // anonymous namespace
 
 TargetInfo *createTarget() {
   switch (Config->EMachine) {
   case EM_386:
     return new X86TargetInfo();
   case EM_AARCH64:
     return new AArch64TargetInfo();
+  case EM_AMDGPU:
+    return new AMDGPUTargetInfo();
   case EM_MIPS:
     switch (Config->EKind) {
     case ELF32LEKind:
       return new MipsTargetInfo<ELF32LE>();
     case ELF32BEKind:
       return new MipsTargetInfo<ELF32BE>();
     default:
       error("Unsupported MIPS target");
void AArch64TargetInfo::relocateOne(uint8_t *Loc, uint8_t *BufEnd,
   case R_AARCH64_PREL64:
     write64le(Loc, SA - P);
     break;
   default:
     error("unrecognized reloc " + Twine(Type));
   }
 }
 
+AMDGPUTargetInfo::AMDGPUTargetInfo() { }
+
+void AMDGPUTargetInfo::writeGotPltEntry(uint8_t *Buf, uint64_t Plt) const {
+  llvm_unreachable("not implemented");
+}
+
+void AMDGPUTargetInfo::writePltZeroEntry(uint8_t *Buf, uint64_t GotEntryAddr,
+                                         uint64_t PltEntryAddr) const {
+  llvm_unreachable("not implemented");
+}
+
+void AMDGPUTargetInfo::writePltEntry(uint8_t *Buf, uint64_t GotAddr,
+                                     uint64_t GotEntryAddr,
+                                     uint64_t PltEntryAddr, int32_t Index,
+                                     unsigned RelOff) const {
+  llvm_unreachable("not implemented");
+}
+
+bool AMDGPUTargetInfo::relocNeedsGot(uint32_t Type, const SymbolBody &S) const {
+  return false;
+}
+
+bool AMDGPUTargetInfo::relocNeedsPlt(uint32_t Type, const SymbolBody &S) const {
+  return false;
+}
+
+void AMDGPUTargetInfo::relocateOne(uint8_t *Loc, uint8_t *BufEnd, uint32_t Type,
+                                   uint64_t P, uint64_t SA, uint64_t ZA,
+                                   uint8_t *PairedLoc) const {
+  llvm_unreachable("not implemented");
+}
+
 template <class ELFT> MipsTargetInfo<ELFT>::MipsTargetInfo() {
   PageSize = 65536;
   GotHeaderEntriesNum = 2;
 }
 
 template <class ELFT>
 void MipsTargetInfo<ELFT>::writeGotHeaderEntries(uint8_t *Buf) const {
   typedef typename ELFFile<ELFT>::Elf_Off Elf_Off;

ELF/Writer.cpp

static uint32_t toPhdrFlags(uint64_t Flags) {
   uint32_t Ret = PF_R;
   if (Flags & SHF_WRITE)
     Ret |= PF_W;
   if (Flags & SHF_EXECINSTR)
     Ret |= PF_X;
   return Ret;
 }
 
+template <class ELFT> static unsigned getPhdrTy(OutputSectionBase<ELFT> *Sec) {
+  if (Config->EMachine != EM_AMDGPU)
+    return PT_LOAD;
+
+  uint32_t Flags = Sec->getFlags();
+  if (Flags & SHF_AMDGPU_HSA_CODE)
+    return PT_AMDGPU_HSA_LOAD_CODE_AGENT;
+
+  if ((Flags & SHF_AMDGPU_HSA_GLOBAL) && !(Flags & SHF_AMDGPU_HSA_AGENT))
+    return PT_AMDGPU_HSA_LOAD_GLOBAL_PROGRAM;
+
+  return PT_LOAD;
+}
+
 template <class ELFT>
 void Writer<ELFT>::updateRelro(Elf_Phdr *Cur, Elf_Phdr *GnuRelroPhdr,
                                OutputSectionBase<ELFT> *Sec, uintX_t VA) {
   if (!Config->ZRelro || !(Cur->p_flags & PF_W) || !isRelroSection(Sec))
     return;
   if (!GnuRelroPhdr->p_type)
     setPhdr(GnuRelroPhdr, PT_GNU_RELRO, PF_R, Cur->p_offset, Cur->p_vaddr,
             VA - Cur->p_vaddr, 1 /*p_align*/);
template <class ELFT> void Writer<ELFT>::assignAddresses() {
   for (OutputSectionBase<ELFT> *Sec : OutputSections) {
     if (needsPhdr<ELFT>(Sec)) {
       uintX_t Flags = toPhdrFlags(Sec->getFlags());
       if (Phdrs[PhdrIdx].p_flags != Flags) {
         // Flags changed. Create a new PT_LOAD.
         VA = RoundUpToAlignment(VA, Target->getPageSize());
         FileOff = RoundUpToAlignment(FileOff, Target->getPageSize());
         Elf_Phdr *PH = &Phdrs[++PhdrIdx];
-        setPhdr(PH, PT_LOAD, Flags, FileOff, VA, 0, Target->getPageSize());
+        unsigned PTType = getPhdrTy(Sec);
+        setPhdr(PH, PTType, Flags, FileOff, VA, 0, Target->getPageSize());
       }
 
       if (Sec->getFlags() & SHF_TLS) {
         if (!TlsPhdr.p_vaddr)
           setPhdr(&TlsPhdr, PT_TLS, PF_R, FileOff, VA, 0, Sec->getAlign());
         if (Sec->getType() != SHT_NOBITS)
           VA = RoundUpToAlignment(VA, Sec->getAlign());
         uintX_t TVA = RoundUpToAlignment(VA + ThreadBSSOffset, Sec->getAlign());

test/ELF/amdgpu-globals.s

+# RUN: llvm-mc -filetype=obj -triple=amdgcpu--amdgcn -mcpu=kaveri %s -o %t.o
+# RUN: lld -flavor gnu %t.o -o %t
+# RUN: llvm-readobj -sections -symbols -program-headers %t | FileCheck %s
+
+# Requires: amdgpu
+
+  .amdgpu_hsa_module_global module_global_program
+  .size module_global_program, 4
+  .hsadata_global_program
+module_global_program:
+  .long 0                       ; 0x0
+
+  .amdgpu_hsa_program_global program_global_program
+  .size program_global_program, 4
+  .hsadata_global_program
+program_global_program:
+  .long 0                       ; 0x0
+
+  .amdgpu_hsa_module_global module_global_agent
+  .size module_global_agent, 4
+  .hsadata_global_agent
+module_global_agent:
+  .long 0                       ; 0x0
+
+  .amdgpu_hsa_program_global program_global_agent
+  .size program_global_agent, 4
+  .hsadata_global_agent
+program_global_agent:
+  .long 0                       ; 0x0
+
+  .amdgpu_hsa_module_global module_global_readonly
+  .size module_global_readonly, 4
+  .hsatext
+module_global_readonly:
+  .long 0                       ; 0x0
+
+  .amdgpu_hsa_program_global program_global_readonly
+  .size program_global_readonly, 4
+  .hsatext
+program_global_readonly:
+  .long 0                       ; 0x0
+
+# CHECK: Section {
+# CHECK: Name: .hsadata_global_program
+# CHECK: Type: SHT_PROGBITS (0x1)
+# CHECK: Flags [ (0x100003)
+# CHECK: SHF_ALLOC (0x2)
+# CHECK: SHF_AMDGPU_HSA_GLOBAL (0x100000)
+# CHECK: SHF_WRITE (0x1)
+# CHECK: ]
+# CHECK: Address: [[HSADATA_GLOBAL_PROGRAM_ADDR:[0-9xa-f]+]]
+# CHECK: }
+
+# CHECK: Section {
+# CHECK: Name: .hsadata_global_agent
+# CHECK: Type: SHT_PROGBITS (0x1)
+# CHECK: Flags [ (0x900003)
+# CHECK: SHF_ALLOC (0x2)
+# CHECK: SHF_AMDGPU_HSA_AGENT (0x800000)
+# CHECK: SHF_AMDGPU_HSA_GLOBAL (0x100000)
+# CHECK: SHF_WRITE (0x1)
+# CHECK: ]
+# CHECK: }
+
+# CHECK: Section {
+# CHECK: Name: .hsatext
+# CHECK: Type: SHT_PROGBITS
+# CHECK: Flags [ (0xC00007)
+# CHECK: SHF_ALLOC (0x2)
+# CHECK: SHF_AMDGPU_HSA_AGENT (0x800000)
+# CHECK: SHF_AMDGPU_HSA_CODE (0x400000)
+# CHECK: SHF_EXECINSTR (0x4)
+# CHECK: SHF_WRITE (0x1)
+# CHECK: ]
+# CHECK: Address: [[HSATEXT_ADDR:[0-9xa-f]+]]
+# CHECK: }
+
+# CHECK: Symbol {
+# CHECK: Name: module_global_agent
+# CHECK: Value: 0x0
+# CHECK: Size: 4
+# CHECK: Binding: Local
+# CHECK: Section: .hsadata_global_agent
+# CHECK: }
+
+# CHECK: Symbol {
+# CHECK: Name: module_global_program
+# CHECK: Value: 0x0
+# CHECK: Size: 4
+# CHECK: Binding: Local
+# CHECK: Section: .hsadata_global_program
+# CHECK: }
+
+# CHECK: Symbol {
+# CHECK: Name: module_global_readonly
+# CHECK: Value: 0x0
+# CHECK: Size: 4
+# CHECK: Binding: Local
+# CHECK: Type: Object
+# CHECK: Section: .hsatext
+# CHECK: }
+
+# CHECK: Symbol {
+# CHECK: Name: program_global_agent
+# CHECK: Value: 0x4
+# CHECK: Size: 4
+# CHECK: Binding: Global
+# CHECK: Type: Object
+# CHECK: Section: .hsadata_global_agent
+# CHECK: }
+
+# CHECK: Symbol {
+# CHECK: Name: program_global_program
+# CHECK: Value: 0x4
+# CHECK: Size: 4
+# CHECK: Binding: Global
+# CHECK: Type: Object
+# CHECK: Section: .hsadata_global_program
+# CHECK: }
+
+# CHECK: Symbol {
+# CHECK: Name: program_global_readonly
+# CHECK: Value: 0x4
+# CHECK: Size: 4
+# CHECK: Binding: Global
+# CHECK: Type: Object
+# CHECK: Section: .hsatext
+# CHECK: }
+
+# CHECK: ProgramHeader {
+# CHECK: Type: PT_AMDGPU_HSA_LOAD_GLOBAL_PROGRAM
+# CHECK: VirtualAddress: [[HSADATA_GLOBAL_PROGRAM_ADDR]]
+# CHECK: }
+
+# CHECK: ProgramHeader {
+# CHECK: Type: PT_AMDGPU_HSA_LOAD_CODE_AGENT
+# CHECK: VirtualAddress: [[HSATEXT_ADDR]]
+# CHECK: }

test/ELF/amdgpu-kernels.s

+# RUN: llvm-mc -filetype=obj -triple=amdgcpu--amdgcn -mcpu=kaveri %s -o %t.o
+# RUN: lld -flavor gnu %t.o -o %t
+# RUN: llvm-readobj -sections -symbols -program-headers %t | FileCheck %s
+
+.hsa_code_object_version 1,0
+.hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
+
+.hsatext
+.globl kernel0
+.align 256
+.amdgpu_hsa_kernel kernel0
+kernel0:
+  s_endpgm
+.Lfunc_end0:
+  .size kernel0, .Lfunc_end0-kernel0
+
+.globl kernel1
+.align 256
+.amdgpu_hsa_kernel kernel1
+kernel1:
+  s_endpgm
+  s_endpgm
+.Lfunc_end1:
+  .size kernel1, .Lfunc_end1-kernel1
+
+
+# CHECK: Section {
+# CHECK: Name: .hsatext
+# CHECK: Type: SHT_PROGBITS
+# CHECK: Flags [ (0xC00007)
+# CHECK: SHF_ALLOC (0x2)
+# CHECK: SHF_AMDGPU_HSA_AGENT (0x800000)
+# CHECK: SHF_AMDGPU_HSA_CODE (0x400000)
+# CHECK: SHF_EXECINSTR (0x4)
+# CHECK: SHF_WRITE (0x1)
+# CHECK: ]
+# CHECK: Address: [[HSATEXT_ADDR:[0-9xa-f]+]]
+# CHECK: }
+
+# CHECK: Symbol {
+# CHECK: Name: kernel0
+# CHECK: Value: 0x0
+# CHECK: Size: 4
+# CHECK: Binding: Global
+# CHECK: Type: AMDGPU_HSA_KERNEL
+# CHECK: Section: .hsatext
+# CHECK: }
+
+# CHECK: Symbol {
+# CHECK: Name: kernel1
+# CHECK: Value: 0x100
+# CHECK: Size: 8
+# CHECK: Binding: Global
+# CHECK: Type: AMDGPU_HSA_KERNEL
+# CHECK: Section: .hsatext
+# CHECK: }
+
+# CHECK: ProgramHeader {
+# CHECK: Type: PT_AMDGPU_HSA_LOAD_CODE_AGENT
+# CHECK: VirtualAddress: [[HSATEXT_ADDR]]
+# CHECK: }