WIP

clang/lib/CodeGen/Targets/ARM.cpp

if (getABIKind() == ARMABIKind::AAPCS ||
     // default otherwise.
     Align = getContext().getTypeUnadjustedAlignInChars(Ty).getQuantity();
     unsigned BaseAlign = getContext().getTypeAlignInChars(Base).getQuantity();
     Align = (Align > BaseAlign && Align >= 8) ? 8 : 0;
   }
   return ABIArgInfo::getDirect(nullptr, 0, nullptr, false, Align);
 }
 
+static bool isIntegerLikeType(QualType Ty, ASTContext &Context,
+                              llvm::LLVMContext &VMContext);
+
+// Returns true if `Ty` could be flattened into a valid ABIArgInfo `A`.
+static bool canFlatten(const RecordType *Ty, ASTContext &Ctx, llvm::LLVMContext &LLVMCtx, ABIArgInfo *A) {
+  // AAPCS32 6.5 Parameter Passing
+  // The base standard provides for passing arguments in core registers (r0-r3)
+  // and on the stack.
+  // ...
+  // When a Composite Type argument is assigned to core registers (either fully
+  // or partially), the behavior is as if the argument had been stored to memory
+  // at a word-aligned (4-byte) address and then loaded into consecutive
+  // registers using a suitable load-multiple instruction.
+
+  const RecordDecl *RD = Ty->getDecl();
+  const long NumFields = std::distance(RD->field_begin(), RD->field_end());
+  if (NumFields < 0 || NumFields > 4)
+    return false;
+
+  llvm::SmallVector<llvm::Type*, 4> ParamTypes;
+  uint64_t TotalSize = 0;
+  for (FieldDecl *FD : RD->fields()) {
+    QualType FieldType = FD->getType();
+    if (!FieldType->isIntegerType())
+      return false;
+
+    // Size in bits.
+    uint64_t TypeSize = Ctx.getTypeSize(FieldType);
+    if (TypeSize > 64)
+      return false;
+
+    TotalSize += TypeSize;
+    if (TotalSize > 16 * 8)
+      return false;
+
+    llvm::Type *T = llvm::Type::getIntNTy(LLVMCtx, TypeSize);
+    ParamTypes.push_back(T);
+  }
+
+  // llvm::dbgs() << llvm::StructType::get(LLVMCtx, ParamTypes) << "\n";
+  *A = ABIArgInfo::getDirect(llvm::StructType::get(LLVMCtx, ParamTypes));
+  return true;
+}
+
 ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty, bool isVariadic,
                                             unsigned functionCallConv) const {
   // 6.1.2.1 The following argument types are VFP CPRCs:
   //   A single-precision floating-point type (including promoted
   //   half-precision types); A double-precision floating-point type;
   //   A 64-bit or 128-bit containerized vector type; Homogeneous Aggregate
   //   with a Base Type of a single- or double-precision floating-point type,
   //   64-bit containerized vectors or 128-bit containerized vectors with one
ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty, bool isVariadic,
   }
 
   // On RenderScript, coerce Aggregates <= 64 bytes to an integer array of
   // same size and alignment.
   if (getTarget().isRenderScriptTarget()) {
     return coerceToIntArray(Ty, getContext(), getVMContext());
   }
 
+  // Try to flatten small structs.
+  if (getABIKind() == ARMABIKind::AAPCS && Ty->isStructureType()) {
+    ABIArgInfo A;
+    if (canFlatten(Ty->getAs<RecordType>(), getContext(), getVMContext(), &A))
+      return A;
+  }
+
   // Otherwise, pass by coercing to a structure of the appropriate size.
   llvm::Type* ElemTy;
   unsigned SizeRegs;
-  // FIXME: Try to match the types of the arguments more accurately where
-  // we can.
   if (TyAlign <= 4) {
     ElemTy = llvm::Type::getInt32Ty(getVMContext());
     SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32;
   } else {
     ElemTy = llvm::Type::getInt64Ty(getVMContext());
     SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64;
   }
 

clang/test/CodeGen/aapcs-align.cpp

 void f0(int, S);
 void f0m(int, int, int, int, int, S);
 void g0() {
   S s = {6, 7};
   f0(1, s);
   f0m(1, 2, 3, 4, 5, s);
 }
 // CHECK: define{{.*}} void @g0
-// CHECK: call void @f0(i32 noundef 1, [2 x i32] [i32 6, i32 7]
-// CHECK: call void @f0m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [2 x i32] [i32 6, i32 7]
-// CHECK: declare void @f0(i32 noundef, [2 x i32])
-// CHECK: declare void @f0m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [2 x i32])
+// CHECK: call void @f0(i32 noundef 1, i32 6, i32 7
+// CHECK: call void @f0m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 6, i32 7)
+// CHECK: declare void @f0(i32 noundef, i32, i32)
+// CHECK: declare void @f0m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32, i32)
 
 // Aligned struct, passed according to its natural alignment.
 struct __attribute__((aligned(8))) S8 {
   int x, y;
 } s8;
 
 void f1(int, S8);
 void f1m(int, int, int, int, int, S8);
 void g1() {
   S8 s = {6, 7};
   f1(1, s);
   f1m(1, 2, 3, 4, 5, s);
 }
 // CHECK: define{{.*}} void @g1
-// CHECK: call void @f1(i32 noundef 1, [2 x i32] [i32 6, i32 7]
-// CHECK: call void @f1m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [2 x i32] [i32 6, i32 7]
-// CHECK: declare void @f1(i32 noundef, [2 x i32])
-// CHECK: declare void @f1m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [2 x i32])
+// CHECK: call void @f1(i32 noundef 1, i32 6, i32 7)
+// CHECK: call void @f1m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 6, i32 7)
+// CHECK: declare void @f1(i32 noundef, i32, i32)
+// CHECK: declare void @f1m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32, i32)
 
 // Aligned struct, passed according to its natural alignment.
 struct alignas(16) S16 {
   int x, y;
 };
 
 extern "C" void f2(int, S16);
 extern "C" void f2m(int, int, int, int, int, S16);
 
 void g2() {
   S16 s = {6, 7};
   f2(1, s);
   f2m(1, 2, 3, 4, 5, s);
 }
 // CHECK: define{{.*}} void @g2
-// CHECK: call void @f2(i32 noundef 1, [4 x i32] [i32 6, i32 7
-// CHECK: call void @f2m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [4 x i32] [i32 6, i32 7
-// CHECK: declare void @f2(i32 noundef, [4 x i32])
-// CHECK: declare void @f2m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [4 x i32])
+// CHECK: call void @f2(i32 noundef 1, i32 6, i32 7)
+// CHECK: call void @f2m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 6, i32 7)
+// CHECK: declare void @f2(i32 noundef, i32, i32)
+// CHECK: declare void @f2m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32, i32)
 
 // Increased natural alignment.
 struct SF8 {
   int x __attribute__((aligned(8)));
   int y;
 };
 
 void f3(int, SF8);
 void f3m(int, int, int, int, int, SF8);
 void g3() {
   SF8 s = {6, 7};
   f3(1, s);
   f3m(1, 2, 3, 4, 5, s);
 }
 // CHECK: define{{.*}} void @g3
-// CHECK: call void @f3(i32 noundef 1, [1 x i64] [i64 30064771078]
-// CHECK: call void @f3m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [1 x i64] [i64 30064771078]
-// CHECK: declare void @f3(i32 noundef, [1 x i64])
-// CHECK: declare void @f3m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [1 x i64])
+// CHECK: call void @f3(i32 noundef 1, i32 6, i32 7)
+// CHECK: call void @f3m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 6, i32 7)
+// CHECK: declare void @f3(i32 noundef, i32, i32)
+// CHECK: declare void @f3m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32, i32)
 
 // Increased natural alignment, capped to 8 though.
 struct SF16 {
   int x;
   int y alignas(16);
   int z, a, b, c, d, e, f, g, h, i, j, k;
 };
 

 void f5(int, P);
 void f5m(int, int, int, int, int, P);
 void g5() {
   P s = {6, 7};
   f5(1, s);
   f5m(1, 2, 3, 4, 5, s);
 }
 // CHECK: define{{.*}} void @g5
-// CHECK: call void @f5(i32 noundef 1, [3 x i32] [i32 6, i32 7, i32 0])
-// CHECK: call void @f5m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [3 x i32] [i32 6, i32 7, i32 0])
-// CHECK: declare void @f5(i32 noundef, [3 x i32])
-// CHECK: declare void @f5m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [3 x i32])
+// CHECK: call void @f5(i32 noundef 1, i32 6, i64 0)
+// CHECK: call void @f5m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 6, i64 0)
+// CHECK: declare void @f5(i32 noundef, i32, i64)
+// CHECK: declare void @f5m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32, i64)
 
 
 // Packed and aligned, alignement causes padding at the end.
 struct  __attribute__((packed, aligned(8))) P8 {
   int x;
   long long u;
 };
 
 void f6(int, P8);
 void f6m(int, int, int, int, int, P8);
 void g6() {
   P8 s = {6, 7};
   f6(1, s);
   f6m(1, 2, 3, 4, 5, s);
 }
 // CHECK: define{{.*}} void @g6
-// CHECK: call void @f6(i32 noundef 1, [4 x i32] [i32 6, i32 7, i32 0, i32 undef])
-// CHECK: call void @f6m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [4 x i32] [i32 6, i32 7, i32 0, i32 undef])
-// CHECK: declare void @f6(i32 noundef, [4 x i32])
-// CHECK: declare void @f6m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [4 x i32])
+// CHECK: call void @f6(i32 noundef 1, i32 6, i64 0)
+// CHECK: call void @f6m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 6, i64 0)
+// CHECK: declare void @f6(i32 noundef, i32, i64)
+// CHECK: declare void @f6m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32, i64)
 }

clang/test/CodeGen/arm-arguments.c

 // APCS-GNU: define{{.*}} void @f30({{.*}} noalias sret
 // AAPCS: define{{.*}} arm_aapcscc void @f30({{.*}} noalias sret
 struct s30 { _Complex int f0; };
 struct s30 f30() {}
 
 // PR11905
 struct s31 { char x; };
 void f31(struct s31 s) { }
-// AAPCS: @f31([1 x i32] %s.coerce)
+// AAPCS: @f31(i8 %s.coerce)
 // AAPCS: %s = alloca %struct.s31, align 1
-// AAPCS: [[TEMP:%.*]] = alloca [1 x i32], align 4
-// AAPCS: store [1 x i32] %s.coerce, ptr [[TEMP]], align 4
+// AAPCS: [[TEMP:%.*]] = getelementptr inbounds %struct.s31, ptr %s, i32 0, i32 0
+// AAPCS: store i8 %s.coerce, ptr [[TEMP]], align 1
 // APCS-GNU: @f31([1 x i32] %s.coerce)
 // APCS-GNU: %s = alloca %struct.s31, align 1
 // APCS-GNU: [[TEMP:%.*]] = alloca [1 x i32], align 4
 // APCS-GNU: store [1 x i32] %s.coerce, ptr [[TEMP]], align 4
 
 // PR13562
 struct s32 { double x; };
 void f32(struct s32 s) { }
 // AAPCS: @f32([1 x i64] %s.coerce)
 // APCS-GNU: @f32([2 x i32] %s.coerce)
 
 // PR13350
 struct s33 { char buf[32*32]; };
 void f33(struct s33 s) { }
 // APCS-GNU-LABEL: define{{.*}} void @f33(ptr noundef byval(%struct.s33) align 4 %s)
 // AAPCS-LABEL: define{{.*}} arm_aapcscc void @f33(ptr noundef byval(%struct.s33) align 4 %s)
 
 // PR14048
 struct s34 { char c; };
 void f34(struct s34 s);
 void g34(struct s34 *s) { f34(*s); }
 // AAPCS: @g34(ptr noundef %s)
-// AAPCS: %[[a:.*]] = alloca [1 x i32]
-// AAPCS: load [1 x i32], ptr %[[a]]
+// AAPCS: %[[a:.*]] = alloca ptr, align 4
+// AAPCS: load ptr, ptr %[[a]]
 
 // rdar://12596507
 struct s35
 {
    float v[18]; //make sure byval is on.
 } __attribute__((aligned(16)));
 typedef struct s35 s35_with_align;