[GlobalIsel][X86] Add scalar support for G_FSHR and G_FSHL.

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

case TargetOpcode::G_XOR: {
     // AN = BinOp<Ty/N> BN, CN
     // A = G_MERGE_VALUES A1, ..., AN
     return narrowScalarBasic(MI, TypeIdx, NarrowTy);
   }
   case TargetOpcode::G_SHL:
   case TargetOpcode::G_LSHR:
   case TargetOpcode::G_ASHR:
     return narrowScalarShift(MI, TypeIdx, NarrowTy);
+  case TargetOpcode::G_FSHR:
+  case TargetOpcode::G_FSHL:
+    if (TypeIdx != 1)
+      return UnableToLegalize;
+    Observer.changingInstr(MI);
+    narrowScalarSrc(MI, NarrowTy, 3);
+    Observer.changedInstr(MI);
+    return Legalized;
   case TargetOpcode::G_CTLZ:
   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
   case TargetOpcode::G_CTTZ:
   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
   case TargetOpcode::G_CTPOP:
     if (TypeIdx == 1)
       switch (MI.getOpcode()) {
       case TargetOpcode::G_CTLZ:

llvm/lib/Target/X86/X86InstrGISel.td

+//=----- X86InstrGISel.td - X86 GISel target pseudos -*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// X86 GlobalISel target pseudo instruction definitions. This is kept
+// separately from the other tablegen files for organizational purposes, but
+// share the same infrastructure.
+//
+//===----------------------------------------------------------------------===//
+
+
+class X86GenericInstruction : GenericInstruction {
+  let Namespace = "X86";
+}
+
+// A pseudo to represent 16 bit funnel left shift modulo 32
+def G_FSHL16 : X86GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src1, type0:$src2, type1:$src3);
+  let hasSideEffects = false;
+}
+
+// A pseudo to represent 16 bit funnel right shift modulo 32
+def G_FSHR16 : X86GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src1, type0:$src2, type1:$src3);
+  let hasSideEffects = false;
+}
+
+def : GINodeEquiv<G_FSHL16, X86fshl>;
+def : GINodeEquiv<G_FSHR16, X86fshr>;

llvm/lib/Target/X86/X86InstrInfo.td

 
 // Compiler Pseudo Instructions and Pat Patterns
 include "X86InstrCompiler.td"
 include "X86InstrVecCompiler.td"
 
 // Assembler mnemonic/instruction aliases
 include "X86InstrAsmAlias.td"
 
+// GISel target pseudos
+include "X86InstrGISel.td"

llvm/lib/Target/X86/X86InstructionSelector.cpp

bool X86InstructionSelector::select(MachineInstr &I) {
   assert(I.getParent() && "Instruction should be in a basic block!");
   assert(I.getParent()->getParent() && "Instruction should be in a function!");
 
   MachineBasicBlock &MBB = *I.getParent();
   MachineFunction &MF = *MBB.getParent();
   MachineRegisterInfo &MRI = MF.getRegInfo();
 
   unsigned Opcode = I.getOpcode();
-  if (!isPreISelGenericOpcode(Opcode)) {
+  if (!isPreISelGenericOpcode(Opcode) && !I.isPreISelOpcode()) {
     // Certain non-generic instructions also need some special handling.
 
     if (Opcode == TargetOpcode::LOAD_STACK_GUARD)
       return false;
 
     if (I.isCopy())
       return selectCopy(I, MRI);
 

llvm/lib/Target/X86/X86LegalizerInfo.h

 //===- X86LegalizerInfo.h ------------------------------------------*- C++
 //-*-==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 /// \file
 /// This file declares the targeting of the Machinelegalizer class for X86.
 /// \todo This should be generated by TableGen.
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_X86_X86MACHINELEGALIZER_H
 #define LLVM_LIB_TARGET_X86_X86MACHINELEGALIZER_H
 
+#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
+#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 
 namespace llvm {
 
 class X86Subtarget;
 class X86TargetMachine;
 
 /// This class provides the information for the target register banks.
 class X86LegalizerInfo : public LegalizerInfo {
 private:
   /// Keep a reference to the X86Subtarget around so that we can
   /// make the right decision when generating code for different targets.
   const X86Subtarget &Subtarget;
 
 public:
   X86LegalizerInfo(const X86Subtarget &STI, const X86TargetMachine &TM);
 
+  bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
+
   bool legalizeIntrinsic(LegalizerHelper &Helper,
                          MachineInstr &MI) const override;
+
+private:
+  bool legalizeFunnelShift(MachineInstr &MI, MachineRegisterInfo &MRI,
+                           MachineIRBuilder &MIRBuilder,
+                           GISelChangeObserver &Observer) const;
 };
 } // namespace llvm
 #endif

llvm/lib/Target/X86/X86LegalizerInfo.cpp

 //===- X86LegalizerInfo.cpp --------------------------------------*- C++ -*-==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 /// \file
 /// This file implements the targeting of the Machinelegalizer class for X86.
 /// \todo This should be generated by TableGen.
 //===----------------------------------------------------------------------===//
 
 #include "X86LegalizerInfo.h"
 #include "X86Subtarget.h"
 #include "X86TargetMachine.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
+#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/TargetOpcodes.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/Type.h"
 
 using namespace llvm;
 using namespace TargetOpcode;
 using namespace LegalizeActions;
getActionDefinitionsBuilder({G_ADD, G_SUB})
       .clampMaxNumElements(0, s8, HasBWI ? 64 : (HasAVX2 ? 32 : 16))
       .clampMaxNumElements(0, s16, HasBWI ? 32 : (HasAVX2 ? 16 : 8))
       .clampMaxNumElements(0, s32, HasAVX512 ? 16 : (HasAVX2 ? 8 : 4))
       .clampMaxNumElements(0, s64, HasAVX512 ? 8 : (HasAVX2 ? 4 : 2))
       .widenScalarToNextPow2(0, /*Min=*/32)
       .clampScalar(0, s8, sMaxScalar)
       .scalarize(0);
 
+  getActionDefinitionsBuilder({G_FSHL, G_FSHR})
+    .legalIf([=](const LegalityQuery &Query) -> bool {
+      if (typeInSet(0, {s32})(Query) || (Is64Bit && typeInSet(0, {s64})(Query)))
+        return typeInSet(1, {s8})(Query);
+      return false;
+    })
+    .clampScalar(1, s8, s8)
+    .customFor({s16})
+    .lowerFor({s8});
+
   getActionDefinitionsBuilder({G_UADDE, G_UADDO, G_USUBE, G_USUBO})
       .legalIf([=](const LegalityQuery &Query) -> bool {
         return typePairInSet(0, 1, {{s8, s1}, {s16, s1}, {s32, s1}})(Query) ||
                (Is64Bit && typePairInSet(0, 1, {{s64, s1}})(Query));
       })
       .widenScalarToNextPow2(0, /*Min=*/32)
       .clampScalar(0, s8, sMaxScalar)
       .clampScalar(1, s1, s1)
getActionDefinitionsBuilder({G_FREEZE, G_CONSTANT_FOLD_BARRIER})
     .legalFor({s8, s16, s32, s64, p0})
     .widenScalarToNextPow2(0, /*Min=*/8)
     .clampScalar(0, s8, sMaxScalar);
 
   getLegacyLegalizerInfo().computeTables();
   verify(*STI.getInstrInfo());
 }
 
+bool X86LegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
+                                      MachineInstr &MI) const {
+  MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
+  MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
+  GISelChangeObserver &Observer = Helper.Observer;
+  switch (MI.getOpcode()) {
+    default:
+      return false;
+    case TargetOpcode::G_FSHL:
+    case TargetOpcode::G_FSHR:
+      return legalizeFunnelShift(MI, MRI, MIRBuilder, Observer);
+  }
+}
+
+bool X86LegalizerInfo::legalizeFunnelShift(MachineInstr &MI,
+                                           MachineRegisterInfo &MRI,
+                                           MachineIRBuilder &MIRBuilder,
+                                           GISelChangeObserver &Observer) const {
+  const TargetInstrInfo &TII = MIRBuilder.getTII();
+  auto Masked = MIRBuilder.buildAnd(LLT::scalar(8), MI.getOperand(3), MIRBuilder.buildConstant(LLT::scalar(8), 15));
+  unsigned Opc = 0;
+  if (MI.getOpcode() == TargetOpcode::G_FSHL)
+    Opc = X86::G_FSHL16;
+  else if (MI.getOpcode() == TargetOpcode::G_FSHR)
+    Opc = X86::G_FSHR16;
+  else
+    return false;
+
+  Observer.changingInstr(MI);
+  MI.setDesc(TII.get(Opc));
+  MI.getOperand(3).setReg(Masked.getReg(0));
+  Observer.changedInstr(MI);
+  return true;
+}
+
 bool X86LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
                                          MachineInstr &MI) const {
   return true;
 }