x86: add has lahf/sahf feature

[jfb]

Summary

Some CPUs don't support lahf/sahf.

[jfb]

Follow-up to: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20150810/293071.html

This patch isn't ready yet:

• It needs to be taught about which CPUs support LAHF/SAHF and which don't.
• Code generation also needs to change in X86TargetLowering::ConvertCmpIfNecessary.
• Some tests need to be added.

The following tests are currently failing, and may need to be updated:

LLVM :: CodeGen/X86/2004-02-22-Casts.ll
LLVM :: CodeGen/X86/2004-06-10-StackifierCrash.ll
LLVM :: CodeGen/X86/2006-05-22-FPSetEQ.ll
LLVM :: CodeGen/X86/2008-05-01-InvalidOrdCompare.ll
LLVM :: CodeGen/X86/2009-02-12-SpillerBug.ll
LLVM :: CodeGen/X86/2009-03-09-SpillerBug.ll
LLVM :: CodeGen/X86/2012-08-28-UnsafeMathCrash.ll
LLVM :: CodeGen/X86/2012-10-02-DAGCycle.ll
LLVM :: CodeGen/X86/bitcast-int-to-vector.ll
LLVM :: CodeGen/X86/block-placement.ll
LLVM :: CodeGen/X86/cmovcmov.ll
LLVM :: CodeGen/X86/cmpxchg-clobber-flags.ll
LLVM :: CodeGen/X86/constpool.ll
LLVM :: CodeGen/X86/crash.ll
LLVM :: CodeGen/X86/fabs.ll
LLVM :: CodeGen/X86/fp-stack-O0-crash.ll
LLVM :: CodeGen/X86/fp-stack-compare.ll
LLVM :: CodeGen/X86/fp-stack.ll
LLVM :: CodeGen/X86/isnan.ll
LLVM :: CodeGen/X86/peephole-na-phys-copy-folding.ll
LLVM :: CodeGen/X86/scalar-fp-to-i64.ll
LLVM :: CodeGen/X86/setuge.ll
LLVM :: CodeGen/X86/stack-protector.ll
LLVM :: CodeGen/X86/vec_fp_to_int.ll

[jfb]

Abandoning in favor of @hans' D15240.

lib/Target/X86/X86.td

def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
                                       "Support ADX instructions">;
 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
                                       "Enable SHA instructions",
                                       [FeatureSSE2]>;
 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
                                       "Support PRFCHW instructions">;
 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
                                       "Support RDSEED instruction">;
+def FeatureLAHFSAHF : SubtargetFeature<"lahfsahf", "HasLAHFSAHF", "true",
+                                       "Support LAHF and SAHF instructions">;
 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
                                       "Support MPX instructions">;
 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
                                      "Use LEA for adjusting the stack pointer">;
 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
                                      "HasSlowDivide32", "true",
                                      "Use 8-bit divide for positive values less than 256">;
 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",

lib/Target/X86/X86InstrInfo.cpp

if (Opc) {
     return;
   }
 
   bool FromEFLAGS = SrcReg == X86::EFLAGS;
   bool ToEFLAGS = DestReg == X86::EFLAGS;
   int Reg = FromEFLAGS ? DestReg : SrcReg;
   bool is32 = X86::GR32RegClass.contains(Reg);
   bool is64 = X86::GR64RegClass.contains(Reg);
+
   if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
+
+    int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
+    int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
+    int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
+    int Pop = is64 ? X86::POP64r : X86::POP32r;
+    int PopF = is64 ? X86::POPF64 : X86::POPF32;
+    int AX = is64 ? X86::RAX : X86::EAX;
+
+    if (!Subtarget.hasLAHFSAHF()) {
+      // Moving EFLAGS to / from another register requires a push and a pop.
+      // Notice that we have to adjust the stack if we don't want to clobber the
+      // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
+      if (FromEFLAGS) {
+        BuildMI(MBB, MI, DL, get(PushF));
+        BuildMI(MBB, MI, DL, get(Pop), DestReg);
+      }
+      if (ToEFLAGS) {
+        BuildMI(MBB, MI, DL, get(Push))
+            .addReg(SrcReg, getKillRegState(KillSrc));
+        BuildMI(MBB, MI, DL, get(PopF));
+      }
+      return;
+    }
+
     // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
     // inefficient. Instead:
     //   - Save the overflow flag OF into AL using SETO, and restore it using a
     //     signed 8-bit addition of AL and INT8_MAX.
     //   - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
     //     using LAHF/SAHF.
     //   - When RAX/EAX is live and isn't the destination register, make sure it
     //     isn't clobbered by PUSH/POP'ing it before and after saving/restoring
     //     the flags.
     // This approach is ~2.25x faster than using PUSHF/POPF.
     //
     // This is still somewhat inefficient because we don't know which flags are
     // actually live inside EFLAGS. Were we able to do a single SETcc instead of
     // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
     //
     // PUSHF/POPF is also potentially incorrect because it affects other flags
     // such as TF/IF/DF, which LLVM doesn't model.
     //
     // Notice that we have to adjust the stack if we don't want to clobber the
     // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
 
-    int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
-    int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
-    int Pop = is64 ? X86::POP64r : X86::POP32r;
-    int AX = is64 ? X86::RAX : X86::EAX;
-
     bool AXDead = (Reg == AX);
     // FIXME: The above could figure out that AX is dead in more cases with:
     //          || (MachineBasicBlock::LQR_Dead ==
     //            MBB.computeRegisterLiveness(&getRegisterInfo(), AX, MI));
     //
     //        Unfortunately this is slightly broken, see PR24535 and the likely
     //        related PR25033 PR24991 PR24992 PR25201. These issues seem to
     //        showcase sub-register / super-register confusion: a previous kill

lib/Target/X86/X86InstrInfo.td

 def HasBMI       : Predicate<"Subtarget->hasBMI()">;
 def HasBMI2      : Predicate<"Subtarget->hasBMI2()">;
 def HasRTM       : Predicate<"Subtarget->hasRTM()">;
 def HasHLE       : Predicate<"Subtarget->hasHLE()">;
 def HasTSX       : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
 def HasADX       : Predicate<"Subtarget->hasADX()">;
 def HasSHA       : Predicate<"Subtarget->hasSHA()">;
 def HasPRFCHW    : Predicate<"Subtarget->hasPRFCHW()">;
+def HasLAHFSAHF  : Predicate<"Subtarget->hasLAHFSAHF()">;
 def HasRDSEED    : Predicate<"Subtarget->hasRDSEED()">;
 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
 def FPStackf32   : Predicate<"!Subtarget->hasSSE1()">;
 def FPStackf64   : Predicate<"!Subtarget->hasSSE2()">;
 def HasMPX       : Predicate<"Subtarget->hasMPX()">;
 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
                              AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
                      IIC_MOV_MEM>, Sched<[WriteLoad]>;
 }
 
 
 // Condition code ops, incl. set if equal/not equal/...
 let SchedRW = [WriteALU] in {
 let Defs = [EFLAGS], Uses = [AH] in
 def SAHF     : I<0x9E, RawFrm, (outs),  (ins), "sahf",
-                 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
+                 [(set EFLAGS, (X86sahf AH))], IIC_AHF>,
+    Requires<[HasLAHFSAHF]>;
 let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in
 def LAHF     : I<0x9F, RawFrm, (outs),  (ins), "lahf", [],
-                IIC_AHF>;  // AH = flags
+                 IIC_AHF>, // AH = flags
+    Requires<[HasLAHFSAHF]>;
 } // SchedRW
 
 //===----------------------------------------------------------------------===//
 // Bit tests instructions: BT, BTS, BTR, BTC.
 
 let Defs = [EFLAGS] in {
 let SchedRW = [WriteALU] in {
 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),

lib/Target/X86/X86Subtarget.h

protected:
   bool HasSHA;
 
   /// Processor has PRFCHW instructions.
   bool HasPRFCHW;
 
   /// Processor has RDSEED instructions.
   bool HasRDSEED;
 
+  /// Processor has LAHF/SAHF instructions.
+  bool HasLAHFSAHF;
+
   /// True if BT (bit test) of memory instructions are slow.
   bool IsBTMemSlow;
 
   /// True if SHLD instructions are slow.
   bool IsSHLDSlow;
 
   /// True if unaligned memory accesses of 16-bytes are slow.
   bool IsUAMem16Slow;
public:
   bool hasBMI() const { return HasBMI; }
   bool hasBMI2() const { return HasBMI2; }
   bool hasRTM() const { return HasRTM; }
   bool hasHLE() const { return HasHLE; }
   bool hasADX() const { return HasADX; }
   bool hasSHA() const { return HasSHA; }
   bool hasPRFCHW() const { return HasPRFCHW; }
   bool hasRDSEED() const { return HasRDSEED; }
+  bool hasLAHFSAHF() const { return HasLAHFSAHF; }
   bool isBTMemSlow() const { return IsBTMemSlow; }
   bool isSHLDSlow() const { return IsSHLDSlow; }
   bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
   bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
   bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
   bool hasCmpxchg16b() const { return HasCmpxchg16b; }
   bool useLeaForSP() const { return UseLeaForSP; }
   bool hasSlowDivide32() const { return HasSlowDivide32; }

lib/Target/X86/X86Subtarget.cpp

void X86Subtarget::initializeEnvironment() {
   HasPFI = false;
   HasDQI = false;
   HasBWI = false;
   HasVLX = false;
   HasADX = false;
   HasSHA = false;
   HasPRFCHW = false;
   HasRDSEED = false;
+  HasLAHFSAHF = false;
   HasMPX = false;
   IsBTMemSlow = false;
   IsSHLDSlow = false;
   IsUAMem16Slow = false;
   IsUAMem32Slow = false;
   HasSSEUnalignedMem = false;
   HasCmpxchg16b = false;
   UseLeaForSP = false;
X86Subtarget::X86Subtarget(const Triple &TT, const std::string &CPU,
   } else if (isTargetELF()) {
     setPICStyle(PICStyles::GOT);
   }
 }
 
 bool X86Subtarget::enableEarlyIfConversion() const {
   return hasCMov() && X86EarlyIfConv;
 }
-