In TargetParser, disallow duplicate CPU names. (NFC)

[tyomitch]

Summary

Allowing the same CPU to be listed multiple times, possibly
with different architectures and features every time, and
making the table lookups depend on the order of the entries,
is a maintenance nightmare.

This patch also adds a compile-time check for duplicate or empty names.

[rengolin]

lib/Support/TargetParser.cpp

106

Removing the comment without addressing the problem is not a fix.

577

I'd rather move to table-gen, which can guarantee correctness in the table-gen back-end, than adding this code.

[tyomitch]

lib/Support/TargetParser.cpp

106

I don't see what you mean here: I'm removing the comment which becomes false with this patch; and I'm keeping the FiXME: which remains relevant.

577

I agree that this code is a stop-gap before a table-gen implementation arrives; but I believe it's better than no consistency checks at all.

[tyomitch]

Ping?

The two changes this patch depended on were both committed last week, so hopefully we can now proceed with this one, too.

[tyomitch]

Ping again

[tyomitch]

In D14759#296536, @tyomitch wrote:

Ping?

The two changes this patch depended on were both committed last week, so hopefully we can now proceed with this one, too.

That's from three weeks ago now...

[rengolin]

Now that both ARM and AArch64 target parsers are implemented, we can follow to a table-gen driven design.

If you still want to have that stop-gap code, move it to a unit test.

lib/Support/TargetParser.cpp

static const struct {
   unsigned ID;
 
   StringRef getName() const { return StringRef(NameCStr, NameLength); }
 } HWDivNames[] = {
 #define ARM_HW_DIV_NAME(NAME, ID) { NAME, sizeof(NAME) - 1, ID },
 #include "llvm/Support/ARMTargetParser.def"
 };
 
 // List of CPU names and their arches.
-// The same CPU can have multiple arches and can be default on multiple arches.
-// When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
-// When this becomes table-generated, we'd probably need two tables.
 // FIXME: TableGen this.
 static const struct {
   const char *NameCStr;
   size_t NameLength;
   ARM::ArchKind ArchID;
   bool Default; // is $Name the default CPU for $ArchID ?
   unsigned DefaultExtensions;
 
unsigned llvm::ARM::parseArchVersion(StringRef Arch) {
   case ARM::AK_ARMV7EM:
     return 7;
   case ARM::AK_ARMV8A:
   case ARM::AK_ARMV8_1A:
     return 8;
   }
   return 0;
 }
+
+// ======================================================= //
+// Make sure all names are unique and non-empty
+// ======================================================= //
+
+static constexpr bool is_in(const char* elt) {
+    return false;
+}
+template<class... Tail>
+static constexpr bool is_in(const char* elt,
+                            const char* head, Tail... tail) {
+    return (elt == head) || is_in(elt, tail...);
+}
+
+static constexpr bool distinct() { return true; }
+template<class... Tail>
+static constexpr bool distinct(const char* head, Tail... tail) {
+    return !is_in(head, tail...) && distinct(tail...);
+}
+
+static_assert(distinct(
+#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) NAME,
+#include "llvm/Support/ARMTargetParser.def"
+              ""), "Duplicate ARM_FPU names!");
+
+static_assert(distinct(
+#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, \
+                 ARCH_BASE_EXT) NAME,
+#include "llvm/Support/ARMTargetParser.def"
+              ""), "Duplicate ARM_ARCH names!");
+
+static_assert(distinct(
+#define ARM_ARCH_EXT_NAME(NAME, ID) NAME,
+#include "llvm/Support/ARMTargetParser.def"
+              ""), "Duplicate ARM_ARCH_EXT_NAME's!");
+
+static_assert(distinct(
+#define ARM_HW_DIV_NAME(NAME, ID) NAME,
+#include "llvm/Support/ARMTargetParser.def"
+              ""), "Duplicate ARM_HW_DIV_NAME's!");
+
+static_assert(distinct(
+#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) NAME,
+#include "llvm/Support/ARMTargetParser.def"
+              ""), "Duplicate ARM_CPU_NAME's!");
+