NFC refactorings in lib/Support/TargetParser.cpp

[tyomitch]

Summary

• declare FPUNames, ARCHNames, ARCHExtNames, HWDivNames, CPUNames as static const
• implement getDefaultExtensions with a StringSwitch, in the same way getDefaultFPU is implemented

[rengolin]

LGTM, thanks!

[tyomitch]

Rebased over r253198

lib/Support/TargetParser.cpp

 using namespace ARM;
 
 namespace {
 
 // List of canonical FPU names (use getFPUSynonym) and which architectural
 // features they correspond to (use getFPUFeatures).
 // FIXME: TableGen this.
 // The entries must appear in the order listed in ARM::FPUKind for correct indexing
-struct {
+static const struct {
   const char *NameCStr;
   size_t NameLength;
   ARM::FPUKind ID;
   ARM::FPUVersion FPUVersion;
   ARM::NeonSupportLevel NeonSupport;
   ARM::FPURestriction Restriction;
 
   StringRef getName() const { return StringRef(NameCStr, NameLength); }
 } FPUNames[] = {
 #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) \
   { NAME, sizeof(NAME) - 1, KIND, VERSION, NEON_SUPPORT, RESTRICTION },
 #include "llvm/Support/ARMTargetParser.def"
 };
 
 // List of canonical arch names (use getArchSynonym).
 // This table also provides the build attribute fields for CPU arch
 // and Arch ID, according to the Addenda to the ARM ABI, chapters
 // 2.4 and 2.3.5.2 respectively.
 // FIXME: SubArch values were simplified to fit into the expectations
 // of the triples and are not conforming with their official names.
 // Check to see if the expectation should be changed.
 // FIXME: TableGen this.
-struct {
+static const struct {
   const char *NameCStr;
   size_t NameLength;
   ARM::ArchKind ID;
   const char *CPUAttrCStr;
   size_t CPUAttrLength;
   const char *SubArchCStr;
   size_t SubArchLength;
   ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.

 #define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_BASE_EXT)       \
   {NAME, sizeof(NAME) - 1, ID, CPU_ATTR, sizeof(CPU_ATTR) - 1, SUB_ARCH,       \
    sizeof(SUB_ARCH) - 1, ARCH_ATTR, ARCH_BASE_EXT},
 #include "llvm/Support/ARMTargetParser.def"
 };
 
 // List of Arch Extension names.
 // FIXME: TableGen this.
-struct {
+static const struct {
   const char *NameCStr;
   size_t NameLength;
   unsigned ID;
 
   StringRef getName() const { return StringRef(NameCStr, NameLength); }
 } ARCHExtNames[] = {
 #define ARM_ARCH_EXT_NAME(NAME, ID) { NAME, sizeof(NAME) - 1, ID },
 #include "llvm/Support/ARMTargetParser.def"
 };
 
 // List of HWDiv names (use getHWDivSynonym) and which architectural
 // features they correspond to (use getHWDivFeatures).
 // FIXME: TableGen this.
-struct {
+static const struct {
   const char *NameCStr;
   size_t NameLength;
   unsigned ID;
 
   StringRef getName() const { return StringRef(NameCStr, NameLength); }
 } HWDivNames[] = {
 #define ARM_HW_DIV_NAME(NAME, ID) { NAME, sizeof(NAME) - 1, ID },
 #include "llvm/Support/ARMTargetParser.def"
 };
 
 // List of CPU names and their arches.
 // The same CPU can have multiple arches and can be default on multiple arches.
 // When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
 // When this becomes table-generated, we'd probably need two tables.
 // FIXME: TableGen this.
-struct {
+static const struct {
   const char *NameCStr;
   size_t NameLength;
   ARM::ArchKind ArchID;
   bool Default; // is $Name the default CPU for $ArchID ?
   unsigned DefaultExtensions;
 
   StringRef getName() const { return StringRef(NameCStr, NameLength); }
 } CPUNames[] = {

 unsigned llvm::ARM::getDefaultFPU(StringRef CPU) {
   return StringSwitch<unsigned>(CPU)
 #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
     .Case(NAME, DEFAULT_FPU)
 #include "llvm/Support/ARMTargetParser.def"
     .Default(ARM::FK_INVALID);
 }
 
+unsigned llvm::ARM::getDefaultExtensions(StringRef CPU) {
+  return StringSwitch<unsigned>(CPU)
+#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
+    .Case(NAME, ARCHNames[ID].ArchBaseExtensions | DEFAULT_EXT)
+#include "llvm/Support/ARMTargetParser.def"
+    .Default(ARM::AEK_INVALID);
+}
+
 bool llvm::ARM::getHWDivFeatures(unsigned HWDivKind,
                                  std::vector<const char *> &Features) {
 
   if (HWDivKind == ARM::AEK_INVALID)
     return false;
 
   if (HWDivKind & ARM::AEK_HWDIVARM)
     Features.push_back("+hwdiv-arm");

 StringRef llvm::ARM::getHWDivName(unsigned HWDivKind) {
   for (const auto D : HWDivNames) {
     if (HWDivKind == D.ID)
       return D.getName();
   }
   return StringRef();
 }
 
-unsigned llvm::ARM::getDefaultExtensions(StringRef CPU) {
-  for (const auto C : CPUNames) {
-    if (CPU == C.getName())
-      return (ARCHNames[C.ArchID].ArchBaseExtensions | C.DefaultExtensions);
-  }
-  return ARM::AEK_INVALID;
-}
-
 StringRef llvm::ARM::getDefaultCPU(StringRef Arch) {
   unsigned AK = parseArch(Arch);
   if (AK == ARM::AK_INVALID)
     return StringRef();
 
   // Look for multiple AKs to find the default for pair AK+Name.
   for (const auto CPU : CPUNames) {
     if (CPU.ArchID == AK && CPU.Default)