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Differential D143770

[test] Remove occurences of br undef in Transform/Util tests
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Authored by kritgpt on Feb 10 2023, 11:05 AM.

Details

Reviewers
nlopes
Commits
rGfebe740b2c8f: [test] Remove occurences of br undef in Transform/Util tests [NFC]
Summary

This patch removes br undef as suggested by https://discourse.llvm.org/t/please-dont-use-br-undef-in-tests-aka-please-avoid-test-cases-with-ub/63115

Diff Detail

Unit TestsFailed

TimeTest
60,060 msx64 debian > libFuzzer.libFuzzer::minimize_crash.test

Event Timeline

kritgpt created this revision.Feb 10 2023, 11:05 AM
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kritgpt requested review of this revision.Feb 10 2023, 11:05 AM
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Harbormaster completed remote builds in B213120: Diff 496559.Feb 10 2023, 12:54 PM
nlopes accepted this revision.Feb 10 2023, 1:27 PM
This revision is now accepted and ready to land.Feb 10 2023, 1:27 PM
This revision was landed with ongoing or failed builds.Feb 12 2023, 2:14 AM
Closed by commit rGfebe740b2c8f: [test] Remove occurences of br undef in Transform/Util tests [NFC] (authored by kritgpt, committed by nlopes). · Explain Why
This revision was automatically updated to reflect the committed changes.
nlopes added a commit: rGfebe740b2c8f: [test] Remove occurences of br undef in Transform/Util tests [NFC].

Revision Contents

PathSize
llvm/
test/
Transforms/
Util/
PredicateInfo/
4 lines
24 lines
4 lines

Diff 496559

llvm/test/Transforms/Util/PredicateInfo/ordering.ll

; REQUIRES: asserts ; REQUIRES: asserts
; RUN: opt -passes=print-predicateinfo -debug < %s 2>&1 | FileCheck %s ; RUN: opt -passes=print-predicateinfo -debug < %s 2>&1 | FileCheck %s
declare void @use(i32) declare void @use(i32)
declare void @use.i1(i1) declare void @use.i1(i1)
; Make sure we are visiting the values to build predicate infos for in a ; Make sure we are visiting the values to build predicate infos for in a
; deterministic order. ; deterministic order.
define i32 @test12(i32 %x, i32 %y) { define i32 @test12(i32 %x, i32 %y, i1 %c1) {
; CHECK: Visiting %lcmp = icmp eq i32 %x, 0 ; CHECK: Visiting %lcmp = icmp eq i32 %x, 0
; CHECK: Visiting i32 %x ; CHECK: Visiting i32 %x
; CHECK: Visiting %lcmp2 = icmp slt i32 %y, 1000 ; CHECK: Visiting %lcmp2 = icmp slt i32 %y, 1000
; CHECK: Visiting i32 %y ; CHECK: Visiting i32 %y
; CHECK: Visiting %lcmp3 = icmp slt i32 %y.0, 900 ; CHECK: Visiting %lcmp3 = icmp slt i32 %y.0, 900
; CHECK: Visiting %lcmp4 = icmp slt i32 %y.0.1, 700 ; CHECK: Visiting %lcmp4 = icmp slt i32 %y.0.1, 700
; CHECK: Visiting %lcmp5 = icmp slt i32 %y.0.1.2, 700 ; CHECK: Visiting %lcmp5 = icmp slt i32 %y.0.1.2, 700
; CHECK: Visiting %lcmp6 = icmp slt i32 %y.0.1.2.3, 700 ; CHECK: Visiting %lcmp6 = icmp slt i32 %y.0.1.2.3, 700
; CHECK: Visiting %lcmp7 = icmp slt i32 %y.0.1.2.3.4, 700 ; CHECK: Visiting %lcmp7 = icmp slt i32 %y.0.1.2.3.4, 700
; CHECK: Visiting %rcmp = icmp eq i32 %x, 0 ; CHECK: Visiting %rcmp = icmp eq i32 %x, 0
entry: entry:
br i1 undef, label %left, label %right br i1 %c1, label %left, label %right
left: left:
%lcmp = icmp eq i32 %x, 0 %lcmp = icmp eq i32 %x, 0
br i1 %lcmp, label %left_cond_true, label %left_cond_false br i1 %lcmp, label %left_cond_true, label %left_cond_false
left_cond_true: left_cond_true:
%lcmp2 = icmp slt i32 %y, 1000 %lcmp2 = icmp slt i32 %y, 1000
br i1 %lcmp2, label %left_cond_true2, label %left_ret br i1 %lcmp2, label %left_cond_true2, label %left_ret
▲ Show 20 Lines • Show All 59 Lines • Show Last 20 Lines

llvm/test/Transforms/Util/lowerswitch.ll

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines; CHECK-NEXT: %tmp2 = phi i32 [ 2, %NodeBlock ], [ 5, %bb2 ], [ 2, %LeafBlock3 ]
%tmp2 = phi i32 [ 2, %bb1 ], [ 2, %bb1 ], [ 5, %bb2 ], [ 2, %bb1 ] %tmp2 = phi i32 [ 2, %bb1 ], [ 2, %bb1 ], [ 5, %bb2 ], [ 2, %bb1 ]
br label %exit br label %exit
exit: exit:
ret void ret void
} }
; Test that we don't crash. ; Test that we don't crash.
define void @test2(i32 %mode) { define void @test2(i32 %mode, i1 %c1, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6) {
; CHECK-LABEL: @test2 ; CHECK-LABEL: @test2
br i1 undef, label %1, label %._crit_edge br i1 %c1, label %1, label %._crit_edge
; <label>:1 ; preds = %0 ; <label>:1 ; preds = %0
switch i32 %mode, label %33 [ switch i32 %mode, label %33 [
i32 2, label %2 i32 2, label %2
i32 3, label %3 i32 3, label %3
i32 4, label %4 i32 4, label %4
i32 5, label %5 i32 5, label %5
i32 6, label %6 i32 6, label %6
Show All 35 Lines
; <label>:8 ; preds = %1 ; <label>:8 ; preds = %1
br label %34 br label %34
; <label>:9 ; preds = %1 ; <label>:9 ; preds = %1
br label %34 br label %34
; <label>:10 ; preds = %1 ; <label>:10 ; preds = %1
br i1 undef, label %11, label %12 br i1 %c2, label %11, label %12
; <label>:11 ; preds = %10 ; <label>:11 ; preds = %10
br label %13 br label %13
; <label>:12 ; preds = %10 ; <label>:12 ; preds = %10
br label %13 br label %13
; <label>:13 ; preds = %12, %11 ; <label>:13 ; preds = %12, %11
br label %34 br label %34
; <label>:14 ; preds = %1 ; <label>:14 ; preds = %1
br i1 undef, label %15, label %16 br i1 %c3, label %15, label %16
; <label>:15 ; preds = %14 ; <label>:15 ; preds = %14
br label %17 br label %17
; <label>:16 ; preds = %14 ; <label>:16 ; preds = %14
br label %17 br label %17
; <label>:17 ; preds = %16, %15 ; <label>:17 ; preds = %16, %15
br label %34 br label %34
; <label>:18 ; preds = %1 ; <label>:18 ; preds = %1
br i1 undef, label %19, label %20 br i1 %c4, label %19, label %20
; <label>:19 ; preds = %18 ; <label>:19 ; preds = %18
br label %21 br label %21
; <label>:20 ; preds = %18 ; <label>:20 ; preds = %18
br label %21 br label %21
; <label>:21 ; preds = %20, %19 ; <label>:21 ; preds = %20, %19
br label %34 br label %34
; <label>:22 ; preds = %1 ; <label>:22 ; preds = %1
br i1 undef, label %23, label %24 br i1 %c5, label %23, label %24
; <label>:23 ; preds = %22 ; <label>:23 ; preds = %22
br label %25 br label %25
; <label>:24 ; preds = %22 ; <label>:24 ; preds = %22
br label %25 br label %25
; <label>:25 ; preds = %24, %23 ; <label>:25 ; preds = %24, %23
br label %34 br label %34
; <label>:26 ; preds = %1 ; <label>:26 ; preds = %1
br label %34 br label %34
; <label>:27 ; preds = %1 ; <label>:27 ; preds = %1
br i1 undef, label %28, label %29 br i1 %c6, label %28, label %29
; <label>:28 ; preds = %27 ; <label>:28 ; preds = %27
br label %30 br label %30
; <label>:29 ; preds = %27 ; <label>:29 ; preds = %27
br label %30 br label %30
; <label>:30 ; preds = %29, %28 ; <label>:30 ; preds = %29, %28
Show All 14 Lines
._crit_edge: ; preds = %34, %0 ._crit_edge: ; preds = %34, %0
ret void ret void
} }
; Test that the PHI node in for.cond should have one entry for each predecessor ; Test that the PHI node in for.cond should have one entry for each predecessor
; of its parent basic block after lowerswitch merged several cases into a new ; of its parent basic block after lowerswitch merged several cases into a new
; default block. ; default block.
define void @test3(i32 %mode) { define void @test3(i32 %mode, i1 %c1, i1 %c2) {
; CHECK-LABEL: @test3 ; CHECK-LABEL: @test3
entry: entry:
br label %lbl1 br label %lbl1
lbl1: ; preds = %cleanup, %entry lbl1: ; preds = %cleanup, %entry
br label %lbl2 br label %lbl2
lbl2: ; preds = %cleanup, %lbl1 lbl2: ; preds = %cleanup, %lbl1
br label %for.cond br label %for.cond
for.cond: ; preds = %cleanup, %cleanup, %lbl2 for.cond: ; preds = %cleanup, %cleanup, %lbl2
; CHECK: for.cond: ; CHECK: for.cond:
; CHECK: phi i16 [ undef, %lbl2 ], [ %b.3, %LeafBlock ], [ %b.3, %LeafBlock1 ]{{$}} ; CHECK: phi i16 [ undef, %lbl2 ], [ %b.3, %LeafBlock ], [ %b.3, %LeafBlock1 ]{{$}}
; CHECK: for.cond1: ; CHECK: for.cond1:
%b.2 = phi i16 [ undef, %lbl2 ], [ %b.3, %cleanup ], [ %b.3, %cleanup ] %b.2 = phi i16 [ undef, %lbl2 ], [ %b.3, %cleanup ], [ %b.3, %cleanup ]
br label %for.cond1 br label %for.cond1
for.cond1: ; preds = %for.inc, %for.cond for.cond1: ; preds = %for.inc, %for.cond
%b.3 = phi i16 [ %b.2, %for.cond ], [ undef, %for.inc ] %b.3 = phi i16 [ %b.2, %for.cond ], [ undef, %for.inc ]
%tobool = icmp ne i16 %b.3, 0 %tobool = icmp ne i16 %b.3, 0
br i1 %tobool, label %for.body, label %for.end br i1 %tobool, label %for.body, label %for.end
for.body: ; preds = %for.cond1 for.body: ; preds = %for.cond1
br i1 undef, label %if.then, label %for.inc br i1 %c1, label %if.then, label %for.inc
if.then: ; preds = %for.body if.then: ; preds = %for.body
br label %cleanup br label %cleanup
for.inc: ; preds = %for.body for.inc: ; preds = %for.body
br label %for.cond1 br label %for.cond1
for.end: ; preds = %for.cond1 for.end: ; preds = %for.cond1
br i1 undef, label %if.then4, label %for.body7 br i1 %c2, label %if.then4, label %for.body7
if.then4: ; preds = %for.end if.then4: ; preds = %for.end
br label %cleanup br label %cleanup
for.body7: ; preds = %for.end for.body7: ; preds = %for.end
br label %cleanup br label %cleanup
cleanup: ; preds = %for.body7, %if.then4, %if.then cleanup: ; preds = %for.body7, %if.then4, %if.then
Show All 27 Lines; CHECK: return:
unreachable unreachable
return: return:
ret void ret void
} }
; Test that the PHI node in for.inc is updated correctly as the switch is ; Test that the PHI node in for.inc is updated correctly as the switch is
; replaced with a single branch to for.inc ; replaced with a single branch to for.inc
define void @test5(i32 %mode) { define void @test5(i32 %mode, i1 %c1) {
; CHECK-LABEL: @test5 ; CHECK-LABEL: @test5
entry: entry:
br i1 undef, label %cleanup10, label %cleanup10.thread br i1 %c1, label %cleanup10, label %cleanup10.thread
cleanup10.thread: cleanup10.thread:
br label %for.inc br label %for.inc
cleanup10: cleanup10:
switch i32 %mode, label %unreachable [ switch i32 %mode, label %unreachable [
i32 0, label %for.inc i32 0, label %for.inc
i32 4, label %for.inc i32 4, label %for.inc
Show All 11 Lines

llvm/test/Transforms/Util/simplify-dbg-declare-load.ll

; RUN: opt -passes=instcombine -instcombine-lower-dbg-declare=1 -S < %s | FileCheck %s ; RUN: opt -passes=instcombine -instcombine-lower-dbg-declare=1 -S < %s | FileCheck %s
; RUN: opt -passes=instcombine -instcombine-lower-dbg-declare=0 -S < %s | FileCheck %s --check-prefix=DECLARE ; RUN: opt -passes=instcombine -instcombine-lower-dbg-declare=0 -S < %s | FileCheck %s --check-prefix=DECLARE
; XFAIL: * ; XFAIL: *
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-pc-linux-gnu" target triple = "x86_64-pc-linux-gnu"
%foo = type { i64, i32, i32 } %foo = type { i64, i32, i32 }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 declare void @llvm.dbg.declare(metadata, metadata, metadata) #0
declare void @llvm.dbg.value(metadata, metadata, metadata) #0 declare void @llvm.dbg.value(metadata, metadata, metadata) #0
; Function Attrs: sspreq ; Function Attrs: sspreq
define void @julia_fastshortest_6256() #1 { define void @julia_fastshortest_6256(i1 %c1) #1 {
top: top:
%cp = alloca %foo, align 8 %cp = alloca %foo, align 8
%sink = alloca %foo, align 8 %sink = alloca %foo, align 8
call void @llvm.dbg.declare(metadata ptr %cp, metadata !1, metadata !16), !dbg !17 call void @llvm.dbg.declare(metadata ptr %cp, metadata !1, metadata !16), !dbg !17
br i1 undef, label %idxend, label %fail br i1 %c1, label %idxend, label %fail
fail: ; preds = %top fail: ; preds = %top
unreachable unreachable
idxend: ; preds = %top idxend: ; preds = %top
; CHECK-NOT: call void @llvm.dbg.value(metadata ptr %cp, ; CHECK-NOT: call void @llvm.dbg.value(metadata ptr %cp,
%0 = load %foo, ptr %cp, align 8 %0 = load %foo, ptr %cp, align 8
store volatile %foo %0, ptr %sink, align 8 store volatile %foo %0, ptr %sink, align 8
Show All 35 Lines