ARM: use new modified-imm instructions for all MC-level purposes.

[t.p.northover]

Summary

Hi,

This patch builds on Mihai Popa's steps towards supporting the edge cases of ARM's "modified immediate" format instructions. That patch should probably be committed first.

The instructions he added were actually much closer to the ideal MC representation of what's going on than the existing set, but it was decided that removing the originals in one massive patch would be too invasive, so this is a step in that direction.

It converts the instructions he added into the canonical assembly representation for these operations (with some slightly annoying accommodations for TableGen). The next step will be converting CodeGen to use these versions and eventually removing the legacy representation entirely.

[t.p.northover]

Noticed a couple of tidy ups just after posting. Isn't it always the way?

+ use "ARMModifiedImm" instead of "ModifiedImm" in printing. There's a Thumb one too.
+ An 80-col thing, that I'd even annotated "FIXME".

[rengolin]

Hi Tim,

Overall, I like this change and I agree it's the way forward. I had some
nitpick comments in phabricator, but I'm happy with the patch as it is.
Feel free to ignore whatever doesn't make sense.

cheers,
--renato

lib/Target/ARM/ARMCodeEmitter.cpp

private:
     unsigned getARMBLTargetOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
     unsigned getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
     unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
     unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
+    unsigned getModifiedImmOpValue(const MachineInstr &MI, unsigned Op)
+      const { return 0; }
     unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
     unsigned getSORegRegOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
     unsigned getSORegImmOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
     unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }

lib/Target/ARM/ARMInstrInfo.td

 def so_imm : Operand<i32>, ImmLeaf<i32, [{
     return ARM_AM::getSOImmVal(Imm) != -1;
   }]> {
   let EncoderMethod = "getSOImmOpValue";
   let ParserMatchClass = SOImmAsmOperand;
   let DecoderMethod = "DecodeSOImmOperand";
 }
 
+// ARM modified immediate records an 8-bit immediate rotated by an even number
+// of bits. There are modified variants so that (for example) "(add $LHS, -4)"
+// can be spotted and converted into "(sub $LHS 4)".
+class ModifiedImmAsmOperand<string Modifier> : AsmOperandClass {
+  let Name = "ARMModifiedImm" # Modifier;
+  let RenderMethod = "addARMModifiedImm" # Modifier # "Operands";
+  let ParserMethod = "parseARMModifiedImm";
+}
+
+class ModifiedImm<AsmOperandClass AsmOp> : Operand<i32> {
+  let MIOperandInfo = (ops i32imm:$base, i32imm:$rot);
+  let EncoderMethod = "getModifiedImmOpValue";
+  let ParserMatchClass = AsmOp;
+  let DecoderMethod = "DecodeARMModifiedImmOperand";
+  let PrintMethod = "printModifiedImmOperand";
+}
+
+def mod_imm_asmoperand : ModifiedImmAsmOperand<"">;
+def mod_imm : ModifiedImm<mod_imm_asmoperand>,
+              ComplexPattern<i32, 2, "SelectModifiedImm">;
+
+// mod_imm_neg deals with add <-> sub conversions
+def mod_imm_neg_asmoperand : ModifiedImmAsmOperand<"Neg">;
+def mod_imm_neg : ModifiedImm<mod_imm_neg_asmoperand>,
+                  ComplexPattern<i32, 2, "SelectModifiedImmNeg">;
+
+// mod_imm_not deals with and <-> bic and mov <-> mvn conversions.
+def mod_imm_not_asmoperand : ModifiedImmAsmOperand<"Not">;
+def mod_imm_not : ModifiedImm<mod_imm_not_asmoperand>,
+                  ComplexPattern<i32, 2, "SelectModifiedImmNot">;
+
 // Break so_imm's up into two pieces.  This handles immediates with up to 16
 // bits set in them.  This uses so_imm2part to match and so_imm2part_[12] to
 // get the first/second pieces.
 def so_imm2part : PatLeaf<(imm), [{
       return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
 }]>;
 
 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.

 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
   return Imm >= 0 && Imm < 32;
 }]> {
   let ParserMatchClass = Imm0_31AsmOperand;
 }
 
-/// imm0_31even predicate - True if the 32-bit immediate is in the range [0,31]
-/// and is even
-def Imm0_31EvenAsmOperand : ImmAsmOperand { 
-  let Name = "Imm0_31Even"; 
-  let DiagnosticType = "ImmRange0_31Even";
-}
-def imm0_31even : Operand<i32>, ImmLeaf<i32, [{
-  return Imm >= 0 && Imm < 32 && ((Imm % 2) == 0);
-}]> {
-  let ParserMatchClass = Imm0_31EvenAsmOperand;
-}
-
 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
   return Imm >= 0 && Imm < 32;
 }]> {
   let ParserMatchClass = Imm0_32AsmOperand;
 }
 

 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
 /// binop that produces a value.
 let TwoOperandAliasConstraint = "$Rn = $Rd" in
 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
                      InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
                         PatFrag opnode, bit Commutable = 0> {
   // The register-immediate version is re-materializable. This is useful
   // in particular for taking the address of a local.
-  let isReMaterializable = 1 in {
+  let isReMaterializable = 1, isCodeGenOnly = 1 in {
   def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
                iii, opc, "\t$Rd, $Rn, $imm",
                [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
            Sched<[WriteALU, ReadALU]> {
     bits<4> Rd;
     bits<4> Rn;
     bits<12> imm;
     let Inst{25} = 1;
     let Inst{19-16} = Rn;
     let Inst{15-12} = Rd;
     let Inst{11-0} = imm;
   }
   }
-  let isAsmParserOnly = 1 in
-  def rii : AsI1<opcod, (outs GPR:$Rd), 
-                (ins GPR:$Rn, imm0_255:$imm1, imm0_31even:$imm2), DPFrm,
-                iii, opc, "\t$Rd, $Rn, $imm1, $imm2", [] > {
+  def rii : AsI1<opcod, (outs GPR:$Rd),
+                (ins GPR:$Rn, mod_imm:$imm), DPFrm,
+                iii, opc, "\t$Rd, $Rn, $imm", [] > {
     bits<4> Rd;
     bits<4> Rn;
-    bits<8> imm1;
-    bits<5> imm2;
+    bits<12> imm;
+
     let Inst{25} = 1;
     let Inst{19-16} = Rn;
     let Inst{15-12} = Rd;
-    let Inst{11-8} = imm2{4-1};
-    let Inst{7-0} = imm1;
+    let Inst{11-0} = imm;
   }
   def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
                iir, opc, "\t$Rd, $Rn, $Rm",
                [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
            Sched<[WriteALU, ReadALU, ReadALU]> {
     bits<4> Rd;
     bits<4> Rn;
     bits<4> Rm;

 /// reversed.  The 'rr' form is only defined for the disassembler; for codegen
 /// it is equivalent to the AsI1_bin_irs counterpart.
 let TwoOperandAliasConstraint = "$Rn = $Rd" in
 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
                      InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
                         PatFrag opnode, bit Commutable = 0> {
   // The register-immediate version is re-materializable. This is useful
   // in particular for taking the address of a local.
-  let isReMaterializable = 1 in {
+  let isReMaterializable = 1, isCodeGenOnly = 1 in {
   def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
                iii, opc, "\t$Rd, $Rn, $imm",
                [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
            Sched<[WriteALU, ReadALU]> {
     bits<4> Rd;
     bits<4> Rn;
     bits<12> imm;
     let Inst{25} = 1;
     let Inst{19-16} = Rn;
     let Inst{15-12} = Rd;
     let Inst{11-0} = imm;
   }
   }
-  let isAsmParserOnly = 1 in 
-  def rii : AsI1<opcod, (outs GPR:$Rd), 
-               (ins GPR:$Rn, imm0_255:$imm1, imm0_31even:$imm2), DPFrm,
-                iii, opc, "\t$Rd, $Rn, $imm1, $imm2", []> {
+  def rii : AsI1<opcod, (outs GPR:$Rd),
+               (ins GPR:$Rn, mod_imm:$imm), DPFrm,
+                iii, opc, "\t$Rd, $Rn, $imm", []> {
     bits<4> Rd;
     bits<4> Rn;
-    bits<8> imm1;
-    bits<5> imm2;
+    bits<12> imm;
     let Inst{25} = 1;
     let Inst{19-16} = Rn;
     let Inst{15-12} = Rd;
-    let Inst{11-8} = imm2{4-1};
-    let Inst{7-0} = imm1;
+    let Inst{11-0} = imm;
   }
   def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
                iir, opc, "\t$Rd, $Rn, $Rm",
                [/* pattern left blank */]>,
            Sched<[WriteALU, ReadALU, ReadALU]> {
     bits<4> Rd;
     bits<4> Rn;
     bits<4> Rm;

 
 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
 /// a explicit result, only implicitly set CPSR.
 let isCompare = 1, Defs = [CPSR] in {
 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
                      InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
                        PatFrag opnode, bit Commutable = 0> {
+  let isCodeGenOnly = 1 in
   def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
                opc, "\t$Rn, $imm",
                [(opnode GPR:$Rn, so_imm:$imm)]>,
            Sched<[WriteCMP, ReadALU]> {
     bits<4> Rn;
     bits<12> imm;
     let Inst{25} = 1;
     let Inst{20} = 1;
     let Inst{19-16} = Rn;
     let Inst{15-12} = 0b0000;
     let Inst{11-0} = imm;
 
     let Unpredictable{15-12} = 0b1111;
   }
-  let isAsmParserOnly = 1 in 
-  def rii : AI1<opcod, (outs), (ins GPR:$Rn, imm0_255:$imm1, imm0_31even:$imm2), 
-                DPFrm, iii, opc, "\t$Rn, $imm1, $imm2", []> { 
+  def rii : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm),
+                DPFrm, iii, opc, "\t$Rn, $imm", []> {
     bits<4> Rn;
-    bits<8> imm1;
-    bits<5> imm2;
+    bits<12> imm;
     let Inst{25} = 1;
     let Inst{20} = 1;
     let Inst{19-16} = Rn;
     let Inst{15-12} = 0b0000;
-    let Inst{11-8} = imm2{4-1};
-    let Inst{7-0} = imm1;
+    let Inst{11-0} = imm;
     let Unpredictable{15-12} = 0b1111;
   }
   def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
                opc, "\t$Rn, $Rm",
                [(opnode GPR:$Rn, GPR:$Rm)]>,
            Sched<[WriteCMP, ReadALU, ReadALU]> {
     bits<4> Rn;
     bits<4> Rm;
def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
            Sched<[WriteALU, ReadALU]> {
     bits<4> Rd;
     bits<4> Rn;
     bits<12> imm;
     let Inst{25} = 1;
     let Inst{15-12} = Rd;
     let Inst{19-16} = Rn;
     let Inst{11-0} = imm;
+
+    let isCodeGenOnly = 1;
   }
-  let isAsmParserOnly = 1 in
-  def rii : AsI1<opcod, (outs GPR:$Rd), 
-                (ins GPR:$Rn, imm0_255:$imm1, imm0_31even:$imm2),
-                DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm1, $imm2", [] >, 
+  def rii : AsI1<opcod, (outs GPR:$Rd),
+                (ins GPR:$Rn, mod_imm:$imm),
+                DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", [] >,
                 Requires<[IsARM]> {
     bits<4> Rd;
     bits<4> Rn;
-    bits<8> imm1;
-    bits<5> imm2;
+    bits<12> imm;
     let Inst{25} = 1;
     let Inst{15-12} = Rd;
     let Inst{19-16} = Rn;
-    let Inst{11-8} = imm2{4-1};
-    let Inst{7-0} = imm1;
+    let Inst{11-0} = imm;
   }
   def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
                 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
                [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
                Requires<[IsARM]>,
            Sched<[WriteALU, ReadALU, ReadALU]> {
     bits<4> Rd;
     bits<4> Rn;
def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
            Sched<[WriteALU, ReadALU]> {
     bits<4> Rd;
     bits<4> Rn;
     bits<12> imm;
     let Inst{25} = 1;
     let Inst{15-12} = Rd;
     let Inst{19-16} = Rn;
     let Inst{11-0} = imm;
+
+    let isCodeGenOnly = 1;
   }
-  let isAsmParserOnly = 1 in
-  def rii : AsI1<opcod, (outs GPR:$Rd), 
-                 (ins GPR:$Rn, imm0_255:$imm1, imm0_31even:$imm2),
-                 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm1, $imm2", []>,
+  def rii : AsI1<opcod, (outs GPR:$Rd),
+                 (ins GPR:$Rn, mod_imm:$imm),
+                 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", []>,
                  Requires<[IsARM]> {
     bits<4> Rd;
     bits<4> Rn;
-    bits<8> imm1;
-    bits<5> imm2;
+    bits<12> imm;
     let Inst{25} = 1;
     let Inst{15-12} = Rd;
     let Inst{19-16} = Rn;
-    let Inst{11-8} = imm2{4-1};
-    let Inst{7-0} = imm1;
+    let Inst{11-0} = imm;
   }
   def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
                 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
                [/* pattern left blank */]>,
            Sched<[WriteALU, ReadALU, ReadALU]> {
     bits<4> Rd;
     bits<4> Rn;
     bits<4> Rm;
def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
   let Inst{15-12} = Rd;
   let Inst{19-16} = 0b0000;
   let Inst{11-5} = src{11-5};
   let Inst{4} = 0;
   let Inst{3-0} = src{3-0};
   let Inst{25} = 0;
 }
 
-let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
+let isCodeGenOnly = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
+    isMoveImm = 1 in
 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
                 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
                 Sched<[WriteALU]> {
   bits<4> Rd;
   bits<12> imm;
   let Inst{25} = 1;
   let Inst{15-12} = Rd;
   let Inst{19-16} = 0b0000;
   let Inst{11-0} = imm;
 }
 
-let isAsmParserOnly = 1 in
-def MOVii : AsI1<0b1101, (outs GPR:$Rd), (ins imm0_255:$imm1, imm0_31even:$imm2), 
-                 DPFrm, IIC_iMOVi, "mov", "\t$Rd, $imm1, $imm2", []>, UnaryDP,
+def MOVii : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm),
+                 DPFrm, IIC_iMOVi, "mov", "\t$Rd, $imm", []>, UnaryDP,
                  Sched<[WriteALU]> {
   bits<4> Rd;
-  bits<8> imm1;
-  bits<5> imm2;
+  bits<12> imm;
   let Inst{25} = 1;
   let Inst{15-12} = Rd;
   let Inst{19-16} = 0b0000;
-  let Inst{11-8} = imm2{4-1};
-  let Inst{7-0} = imm1;
+  let Inst{11-0} = imm;
 }
 
 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
                  DPFrm, IIC_iMOVi,
                  "movw", "\t$Rd, $imm",
                  [(set GPR:$Rd, imm0_65535:$imm)]>,
                  Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
def  MVNsr  : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
   let Inst{19-16} = 0b0000;
   let Inst{15-12} = Rd;
   let Inst{11-8} = shift{11-8};
   let Inst{7} = 0;
   let Inst{6-5} = shift{6-5};
   let Inst{4} = 1;
   let Inst{3-0} = shift{3-0};
 }
-let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
+let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
+    isMoveImm = 1 in
 def  MVNi  : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
                   IIC_iMVNi, "mvn", "\t$Rd, $imm",
                   [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
   bits<4> Rd;
   bits<12> imm;
   let Inst{25} = 1;
   let Inst{19-16} = 0b0000;
   let Inst{15-12} = Rd;
   let Inst{11-0} = imm;
 }
 
-let isAsmParserOnly = 1 in
-def MVNii : AsI1<0b1111, (outs GPR:$Rd), (ins imm0_255:$imm1, imm0_31even:$imm2),
-                 DPFrm, IIC_iMVNi, "mvn", "\t$Rd, $imm1, $imm2", []> {
+def MVNii : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm),
+                 DPFrm, IIC_iMVNi, "mvn", "\t$Rd, $imm", []> {
   bits<4> Rd;
-  bits<8> imm1;
-  bits<5> imm2;
+  bits<12> imm;
   let Inst{25} = 1;
   let Inst{19-16} = 0b0000;
   let Inst{15-12} = Rd;
-  let Inst{11-8} = imm2{4-1};
-  let Inst{7-0} = imm1;
+  let Inst{11-0} = imm;
 }
 
 
 def : ARMPat<(and   GPR:$src, so_imm_not:$imm),
              (BICri GPR:$src, so_imm_not:$imm)>;
 
 //===----------------------------------------------------------------------===//
 //  Multiply Instructions.
def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
   bits<12> imm;
   let Inst{25} = 1;
   let Inst{20} = 1;
   let Inst{19-16} = Rn;
   let Inst{15-12} = 0b0000;
   let Inst{11-0} = imm;
 
   let Unpredictable{15-12} = 0b1111;
+
+  let isCodeGenOnly = 1;
 }
 
-let isAsmParserOnly = 1 in 
-def CMNrii : AI1<0b1011, (outs), (ins GPR:$Rn, imm0_255:$imm1, imm0_31even:$imm2), 
-                 DPFrm, IIC_iCMPi, "cmn", "\t$Rn, $imm1, $imm2", []> {
+def CMNrii : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm),
+                 DPFrm, IIC_iCMPi, "cmn", "\t$Rn, $imm", []> {
   bits<4> Rn;
-  bits<8> imm1;
-  bits<5> imm2;
+  bits<12> imm;
 
   let Inst{25} = 1;
   let Inst{20} = 1;
   let Inst{19-16} = Rn;
   let Inst{15-12} = 0b0000;
-  let Inst{11-8} = imm2{4-1};
-  let Inst{7-0} = imm1;
+  let Inst{11-0} = imm;
 
   let Unpredictable{15-12} = 0b1111;
 }
 
 
 // CMN register-register/shift
 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
                  "cmn", "\t$Rn, $Rm",
def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
   let Inst{22} = mask{4}; // R bit
   let Inst{21-20} = 0b10;
   let Inst{19-16} = mask{3-0};
   let Inst{15-12} = 0b1111;
   let Inst{11-4} = 0b00000000;
   let Inst{3-0} = Rn;
 }
 
+let isCodeGenOnly = 1 in
 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask,  so_imm:$a), NoItinerary,
                "msr", "\t$mask, $a", []> {
   bits<5> mask;
   bits<12> a;
   let Inst{23} = 0;
   let Inst{22} = mask{4}; // R bit
   let Inst{21-20} = 0b10;
   let Inst{19-16} = mask{3-0};
   let Inst{15-12} = 0b1111;
   let Inst{11-0} = a;
 }
 
-let isAsmParserOnly = 1 in
-def MSRii : ABI<0b0011, (outs), 
-               (ins msr_mask:$mask, imm0_255:$imm1, imm0_31even:$imm2), NoItinerary,
-               "msr", "\t$mask, $imm1, $imm2", []> {
+def MSRii : ABI<0b0011, (outs),
+               (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
+               "msr", "\t$mask, $imm", []> {
   bits<5> mask;
-  bits<8> imm1;
-  bits<5> imm2;
+  bits<12> imm;
 
   let Inst{23} = 0;
   let Inst{22} = mask{4}; // R bit
   let Inst{21-20} = 0b10;
   let Inst{19-16} = mask{3-0};
   let Inst{15-12} = 0b1111;
-  let Inst{11-8} = imm2{4-1};
-  let Inst{7-0} = imm1;
+  let Inst{11-0} = imm;
 }
 
 
 //===----------------------------------------------------------------------===//
 // TLS Instructions
 //
 
 // __aeabi_read_tp preserves the registers r1-r3.

 def : MnemonicAlias<"uhsubaddx", "uhsax">;
 // UQASX == UQADDSUBX
 def : MnemonicAlias<"uqaddsubx", "uqasx">;
 // UQSAX == UQSUBADDX
 def : MnemonicAlias<"uqsubaddx", "uqsax">;
 // USAX == USUBADDX
 def : MnemonicAlias<"usubaddx", "usax">;
 
-// "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
+// "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
 // for isel.
 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
-                   (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
+                   (MVNii rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
-                   (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
+                   (MOVii rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
 // Same for AND <--> BIC
 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
-                   (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
+                   (ANDrii rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
                            pred:$p, cc_out:$s)>;
 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
-                   (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
+                   (ANDrii rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
                            pred:$p, cc_out:$s)>;
 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
-                   (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
+                   (BICrii rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
                            pred:$p, cc_out:$s)>;
 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
-                   (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
+                   (BICrii rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
                            pred:$p, cc_out:$s)>;
 
-// Likewise, "add Rd, so_imm_neg" -> sub
+// Likewise, "add Rd, mod_imm_neg" -> sub
 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
-                 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
+                   (SUBrii GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm,
+                           pred:$p, cc_out:$s)>;
 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
-                 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
-// Same for CMP <--> CMN via so_imm_neg
+                   (SUBrii GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm,
+                           pred:$p, cc_out:$s)>;
+
+// Same for CMP <--> CMN via mod_imm_neg
 def : ARMInstAlias<"cmp${p} $Rd, $imm",
-                   (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
+                   (CMNrii rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
 def : ARMInstAlias<"cmn${p} $Rd, $imm",
-                   (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
+                   (CMPrii rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
 
 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
 // LSR, ROR, and RRX instructions.
 // FIXME: We need C++ parser hooks to map the alias to the MOV
 //        encoding. It seems we should be able to do that sort of thing
 //        in tblgen, but it could get ugly.
 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

bool Warning(SMLoc L, const Twine &Msg,
                ArrayRef<SMRange> Ranges = None) {
     return Parser.Warning(L, Msg, Ranges);
   }
   bool Error(SMLoc L, const Twine &Msg,
              ArrayRef<SMRange> Ranges = None) {
     return Parser.Error(L, Msg, Ranges);
   }
 
+  int identifyRegister(StringRef Text);
   int tryParseRegister();
   bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
   int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
   bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
   bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
   bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
   bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
   bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
                                    StringRef Op, int Low, int High);
   OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
     return parsePKHImm(O, "lsl", 0, 31);
   }
   OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
     return parsePKHImm(O, "asr", 1, 32);
   }
   OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
+  OperandMatchResultTy parseARMModifiedImm(
+                                         SmallVectorImpl<MCParsedAsmOperand*>&);
   OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
   OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
   OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
   OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
   OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
   OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
   OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
   OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
enum KindTy {
     k_Register,
     k_RegisterList,
     k_DPRRegisterList,
     k_SPRRegisterList,
     k_VectorList,
     k_VectorListAllLanes,
     k_VectorListIndexed,
     k_ShiftedRegister,
+    k_ARMModifiedImmediate,
     k_ShiftedImmediate,
     k_ShifterImmediate,
     k_RotateImmediate,
     k_BitfieldDescriptor,
     k_Token
   } Kind;
 
   SMLoc StartLoc, EndLoc;
class ARMOperand : public MCParsedAsmOperand {
   };
 
   struct RegShiftedImmOp {
     ARM_AM::ShiftOpc ShiftTy;
     unsigned SrcReg;
     unsigned ShiftImm;
   };
 
+  struct ARMModifiedImmediateOp {
+    unsigned BaseImm;
+    unsigned Rot;
+  };
+
   struct RotImmOp {
     unsigned Imm;
   };
 
   struct BitfieldOp {
     unsigned LSB;
     unsigned Width;
   };
union {
     struct RegOp Reg;
     struct VectorListOp VectorList;
     struct VectorIndexOp VectorIndex;
     struct ImmOp Imm;
     struct MemoryOp Memory;
     struct PostIdxRegOp PostIdxReg;
     struct ShifterImmOp ShifterImm;
     struct RegShiftedRegOp RegShiftedReg;
+    struct ARMModifiedImmediateOp ARMModifiedImmediateOp;
     struct RegShiftedImmOp RegShiftedImm;
     struct RotImmOp RotImm;
     struct BitfieldOp Bitfield;
   };
 
   ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
 public:
   ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
case k_ProcIFlags:
       IFlags = o.IFlags;
       break;
     case k_ShifterImmediate:
       ShifterImm = o.ShifterImm;
       break;
     case k_ShiftedRegister:
       RegShiftedReg = o.RegShiftedReg;
       break;
+    case k_ARMModifiedImmediate:
+      ARMModifiedImmediateOp = o.ARMModifiedImmediateOp;
+      break;
     case k_ShiftedImmediate:
       RegShiftedImm = o.RegShiftedImm;
       break;
     case k_RotateImmediate:
       RotImm = o.RotImm;
       break;
     case k_BitfieldDescriptor:
       Bitfield = o.Bitfield;
public:
   }
   bool isAdrLabel() const {
     // If we have an immediate that's not a constant, treat it as a label
     // reference needing a fixup. If it is a constant, but it can't fit 
     // into shift immediate encoding, we reject it.
     if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
     else return (isARMSOImm() || isARMSOImmNeg());
   }
+  bool isARMModifiedImm() const {
+    if (isARMModifiedImmediate()) return true;
+
+    // Otherwise it's a normal immediate that we have to range-check.
+    if (!isImm()) return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return ARM_AM::getSOImmVal(Value) != -1;
+  }
+  bool isARMModifiedImmNeg() const {
+    // This is for aliases converting between add/sub, don't allow an explicit
+    // "#imm1, #imm2".
+    if (!isImm()) return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return ARM_AM::getSOImmVal(Value) == -1 &&
+           ARM_AM::getSOImmVal(-Value) != -1;
+  }
+  bool isARMModifiedImmNot() const {
+    // This is for aliases converting between and/bic, don't allow an explicit
+    // "#imm1, #imm2".
+    if (!isImm()) return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return ARM_AM::getSOImmVal(Value) == -1 &&
+           ARM_AM::getSOImmVal(~Value) != -1;
+  }
   bool isARMSOImm() const {
     if (!isImm()) return false;
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     if (!CE) return false;
     int64_t Value = CE->getValue();
     return ARM_AM::getSOImmVal(Value) != -1;
   }
   bool isARMSOImmNot() const {
public:
   bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
   bool isMem() const { return Kind == k_Memory; }
   bool isShifterImm() const { return Kind == k_ShifterImmediate; }
   bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
   bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
   bool isRotImm() const { return Kind == k_RotateImmediate; }
   bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
   bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
+  bool isARMModifiedImmediate() const { return Kind == k_ARMModifiedImmediate; }
   bool isPostIdxReg() const {
     return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
   }
   bool isMemNoOffset(bool alignOK = false) const {
     if (!isMem())
       return false;
     // No offset of any kind.
     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
void addBitfieldOperands(MCInst &Inst, unsigned N) const {
     Inst.addOperand(MCOperand::CreateImm(Mask));
   }
 
   void addImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     addExpr(Inst, getImm());
   }
 
+  void addARMModifiedImmOperands(MCInst &Inst, int64_t (*Op)(int64_t)) const {
+    uint32_t BaseImm, Rot;
+    if (isImm()) {
+      const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
+      int Bits = ARM_AM::getSOImmVal(Op(CE->getValue()));
+      assert(Bits != -1 && "expected valid modified immediate");
+      BaseImm = Bits & 0xff;
+      Rot = Bits >> 8;
+    } else {
+      assert(isARMModifiedImmediate() && "expected two-operand modified imm");
+      BaseImm = ARMModifiedImmediateOp.BaseImm;
+      Rot = ARMModifiedImmediateOp.Rot;
+    }
+    Inst.addOperand(MCOperand::CreateImm(BaseImm));
+    Inst.addOperand(MCOperand::CreateImm(Rot));
+  }
+
+  static int64_t identityOp(int64_t in) { return in; }
+  void addARMModifiedImmOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    return addARMModifiedImmOperands(Inst, identityOp);
+  }
+
+  static int64_t negOp(int64_t in) { return -in; }
+  void addARMModifiedImmNegOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    return addARMModifiedImmOperands(Inst, negOp);
+  }
+
+  static int64_t notOp(int64_t in) { return ~in; }
+  void addARMModifiedImmNotOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    return addARMModifiedImmOperands(Inst, notOp);
+  }
+
   void addFBits16Operands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
   }
 
   void addFBits32Operands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
     Op->RegShiftedReg.SrcReg = SrcReg;
     Op->RegShiftedReg.ShiftReg = ShiftReg;
     Op->RegShiftedReg.ShiftImm = ShiftImm;
     Op->StartLoc = S;
     Op->EndLoc = E;
     return Op;
   }
 
+  static ARMOperand *CreateARMModifiedImmediate(unsigned BaseImm,
+                                                unsigned Rot,
+                                                SMLoc S, SMLoc E) {
+    ARMOperand *Op = new ARMOperand(k_ARMModifiedImmediate);
+    Op->ARMModifiedImmediateOp.BaseImm = BaseImm;
+    Op->ARMModifiedImmediateOp.Rot = Rot;
+    Op->StartLoc = S;
+    Op->EndLoc = E;
+    return Op;
+  }
+
   static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
                                             unsigned SrcReg,
                                             unsigned ShiftImm,
                                             SMLoc S, SMLoc E) {
     ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
     Op->RegShiftedImm.ShiftTy = ShTy;
     Op->RegShiftedImm.SrcReg = SrcReg;
     Op->RegShiftedImm.ShiftImm = ShiftImm;
OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
        << " #" << ShifterImm.Imm << ">";
     break;
   case k_ShiftedRegister:
     OS << "<so_reg_reg "
        << RegShiftedReg.SrcReg << " "
        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
        << " " << RegShiftedReg.ShiftReg << ">";
     break;
+  case k_ARMModifiedImmediate:
+    OS << "<arm_modified_imm " << ARMModifiedImmediateOp.BaseImm
+       << " " << ARMModifiedImmediateOp.Rot << '>';
+    break;
   case k_ShiftedImmediate:
     OS << "<so_reg_imm "
        << RegShiftedImm.SrcReg << " "
        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
        << " #" << RegShiftedImm.ShiftImm << ">";
     break;
   case k_RotateImmediate:
     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
bool ARMAsmParser::ParseRegister(unsigned &RegNo,
                                  SMLoc &StartLoc, SMLoc &EndLoc) {
   StartLoc = Parser.getTok().getLoc();
   EndLoc = Parser.getTok().getEndLoc();
   RegNo = tryParseRegister();
 
   return (RegNo == (unsigned)-1);
 }
 
-/// Try to parse a register name.  The token must be an Identifier when called,
-/// and if it is a register name the token is eaten and the register number is
-/// returned.  Otherwise return -1.
-///
-int ARMAsmParser::tryParseRegister() {
-  const AsmToken &Tok = Parser.getTok();
-  if (Tok.isNot(AsmToken::Identifier)) return -1;
-
-  std::string lowerCase = Tok.getString().lower();
+int ARMAsmParser::identifyRegister(StringRef Text) {
+  std::string lowerCase = Text.lower();
   unsigned RegNum = MatchRegisterName(lowerCase);
+
   if (!RegNum) {
     RegNum = StringSwitch<unsigned>(lowerCase)
       .Case("r13", ARM::SP)
       .Case("r14", ARM::LR)
       .Case("r15", ARM::PC)
       .Case("ip", ARM::R12)
       // Additional register name aliases for 'gas' compatibility.
       .Case("a1", ARM::R0)
int ARMAsmParser::identifyRegister(StringRef Text) {
   if (!RegNum) {
     // Check for aliases registered via .req. Canonicalize to lower case.
     // That's more consistent since register names are case insensitive, and
     // it's how the original entry was passed in from MC/MCParser/AsmParser.
     StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
     // If no match, return failure.
     if (Entry == RegisterReqs.end())
       return -1;
-    Parser.Lex(); // Eat identifier token.
     return Entry->getValue();
   }
 
+  return RegNum;
+}
+
+/// Try to parse a register name.  The token must be an Identifier when called,
+/// and if it is a register name the token is eaten and the register number is
+/// returned.  Otherwise return -1.
+///
+int ARMAsmParser::tryParseRegister() {
+  const AsmToken &Tok = Parser.getTok();
+  if (Tok.isNot(AsmToken::Identifier)) return -1;
+
+  int RegNum = identifyRegister(Tok.getString());
+
+  if (RegNum != -1)
     Parser.Lex(); // Eat identifier token.
 
   return RegNum;
 }
 
 // Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
 // If a recoverable error occurs, return 1. If an irrecoverable error
 // occurs, return -1. An irrecoverable error is one where tokens have been
 // consumed in the process of trying to parse the shifter (i.e., when it is
if (Val == -1) {
     return MatchOperand_ParseFail;
   }
   Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
                                                                   getContext()),
                                            S, Tok.getEndLoc()));
   return MatchOperand_Success;
 }
 
+ARMAsmParser::OperandMatchResultTy ARMAsmParser::
+parseARMModifiedImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+  const AsmToken &Tok = Parser.getTok();
+  SMLoc S = Parser.getTok().getLoc(), E;
+
+  // An ARM modified immediate can't possibly match in thumb mode.
+  if (isThumb() || Tok.is(AsmToken::Colon))
+    return MatchOperand_NoMatch;
+
+  // We don't want to treat registers as normal expressions. For example we get
+  // called to deal with the second operand in "add r0, r0, #45" because "add
+  // r0, #45" is also valid syntax.
+  if (Tok.is(AsmToken::Identifier) && identifyRegister(Tok.getString()))
+    return MatchOperand_NoMatch;
+
+  if (Tok.is(AsmToken::Hash))
+    Parser.Lex();
+
+  const MCExpr *BaseImmExpr = 0;
+  if (getParser().parseExpression(BaseImmExpr, E)) {
+    // Error already emitted during parse.
+    return MatchOperand_ParseFail;
+  }
+
+  const MCConstantExpr *BaseImmCE = dyn_cast<MCConstantExpr>(BaseImmExpr);
+  if (!BaseImmCE) {
+    Error(S, "value must be compile-time constant");
+    return MatchOperand_ParseFail;
+  }
+  int64_t BaseImm = BaseImmCE->getValue();
+
+  if(Parser.getTok().isNot(AsmToken::Comma)) {
+    // Push the entire immediate as an operand, the range will be checked
+    // individually later.
+    Operands.push_back(ARMOperand::CreateImm(BaseImmCE, S, E));
+    return MatchOperand_Success;
+  }
+
+  Parser.Lex();
+
+  SMLoc SecondImmLoc = Parser.getTok().getLoc();
+  if (Parser.getTok().is(AsmToken::Hash))
+    Parser.Lex();
+
+  const MCExpr *RotExpr = 0;
+  if (getParser().parseExpression(RotExpr, E)) {
+    // Error already emitted during parse
+    return MatchOperand_ParseFail;
+  }
+
+  const MCConstantExpr *RotCE = dyn_cast<MCConstantExpr>(RotExpr);
+  if (!RotCE) {
+    Error(SecondImmLoc, "value must be compile-time constant");
+    return MatchOperand_ParseFail;
+  }
+  int64_t Rot = RotCE->getValue();
+
+  if (BaseImm < 0 || BaseImm > 255) {
+    Error(S, "modified-immediate base value must be integer in range [0,255]");
+    return MatchOperand_ParseFail;
+  } else if (Rot % 2 != 0 || Rot < 0 || Rot > 30) {
+    Error(SecondImmLoc, "modified-immediate rotate operand must be "
+                        "an even number in the range [0,30]");
+    return MatchOperand_ParseFail;
+  }
+
+  Operands.push_back(ARMOperand::CreateARMModifiedImmediate(BaseImm, Rot / 2,
+                                                            S, E));
+  return MatchOperand_Success;
+}
+
 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
 /// instructions. Legal values are:
 ///     lsl #n  'n' in [0,31]
 ///     asr #n  'n' in [1,32]
 ///             n == 32 encoded as n == 0.
 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
   const AsmToken &Tok = Parser.getTok();
static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
   }
 }
 
 bool ARMAsmParser::
 processInstruction(MCInst &Inst,
                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
   switch (Inst.getOpcode()) {
   // Alias for alternate form of 'ADR Rd, #imm' instruction.
-  case ARM::ADDri: {
+  case ARM::ADDrii: {
     if (Inst.getOperand(1).getReg() != ARM::PC ||
-        Inst.getOperand(5).getReg() != 0)
+        Inst.getOperand(6).getReg() != 0)
       return false;
     MCInst TmpInst;
     TmpInst.setOpcode(ARM::ADR);
     TmpInst.addOperand(Inst.getOperand(0));
-    TmpInst.addOperand(Inst.getOperand(2));
-    TmpInst.addOperand(Inst.getOperand(3));
+    uint32_t Imm = Inst.getOperand(2).getImm();
+    uint32_t Rot = Inst.getOperand(3).getImm() * 2;
+    uint32_t Amt = (Imm >> Rot) | (Imm << ((32 - Rot) & 0x1f));
+    TmpInst.addOperand(MCOperand::CreateImm(Amt));
     TmpInst.addOperand(Inst.getOperand(4));
+    TmpInst.addOperand(Inst.getOperand(5));
+    TmpInst.addOperand(Inst.getOperand(6));
     Inst = TmpInst;
     return true;
   }
   // Aliases for alternate PC+imm syntax of LDR instructions.
   case ARM::t2LDRpcrel:
     // Select the narrow version if the immediate will fit.
     if (Inst.getOperand(1).getImm() > 0 &&
         Inst.getOperand(1).getImm() <= 0xff &&
case Match_RequiresV6:
     return Error(IDLoc, "instruction variant requires ARMv6 or later");
   case Match_RequiresThumb2:
     return Error(IDLoc, "instruction variant requires Thumb2");
   case Match_ImmRange0_4: {
     SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
     return Error(ErrorLoc, "immediate operand must be in the range [0,4]");
   }
-  case Match_ImmRange0_31Even: {
-    SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
-    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
-    return Error(ErrorLoc, "immediate operand must an even number in the range [0,30]");
-  }
   case Match_ImmRange0_15: {
     SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
     return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
   }
   }
 
   llvm_unreachable("Implement any new match types added!");

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
                                unsigned RegNo, uint64_t Address,
                                const void *Decoder);
 
 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeARMModifiedImmOperand(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 
static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder) {
   if (Val)
     Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
   else
     Inst.addOperand(MCOperand::CreateReg(0));
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
+static DecodeStatus DecodeARMModifiedImmOperand(MCInst &Inst, unsigned Val,
                                         uint64_t Address, const void *Decoder) {
-  uint32_t imm = Val & 0xFF;
-  uint32_t rot = (Val & 0xF00) >> 7;
-  uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
-  Inst.addOperand(MCOperand::CreateImm(rot_imm));
+  Inst.addOperand(MCOperand::CreateImm(Val & 0xff));
+  Inst.addOperand(MCOperand::CreateImm(Val >> 8));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rm = fieldFromInstruction(Val, 0, 4);

lib/Target/ARM/InstPrinter/ARMInstPrinter.h

public:
   void printInstruction(const MCInst *MI, raw_ostream &O);
   static const char *getRegisterName(unsigned RegNo);
 
 
   void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
 
   void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printSORegImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
+  void printModifiedImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); // FIXME: 80 col
 
   void printAddrModeTBB(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printAddrModeTBH(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
                                   raw_ostream &O);
   void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum,

lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp

void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
 
   printRegName(O, MO1.getReg());
 
   // Print the shift opc.
   printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
                    ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
 }
 
+void ARMInstPrinter::printModifiedImmOperand(const MCInst *MI, unsigned OpNum,
+                                             raw_ostream &O) {
+  uint32_t Imm = MI->getOperand(OpNum).getImm();
+  uint32_t Rot = MI->getOperand(OpNum + 1).getImm() * 2;
 
+  uint32_t RotImm = (Imm >> Rot) | (Imm << ((32-Rot) & 0x1F));
+  if ((uint32_t)ARM_AM::getSOImmVal(RotImm) == (Imm | (Rot << 7)))
+    O << '#' << RotImm;
+  else
+    O << '#' << Imm << ", #" << Rot;
+}
 //===--------------------------------------------------------------------===//
 // Addressing Mode #2
 //===--------------------------------------------------------------------===//
 
 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
                                                 raw_ostream &O) {
   const MCOperand &MO1 = MI->getOperand(Op);
   const MCOperand &MO2 = MI->getOperand(Op+1);

lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
     unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
       << ARMII::SoRotImmShift;
 
     // Encode immed_8.
     Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
     return Binary;
   }
 
+  /// Return an encoded 12-bit shifted-immediate value.
+  unsigned getModifiedImmOpValue(const MCInst &MI, unsigned Op,
+                           SmallVectorImpl<MCFixup> &Fixups) const {
+    unsigned BaseImm = MI.getOperand(Op).getImm();
+    unsigned RotateAmt = MI.getOperand(Op + 1).getImm();
+
+    return BaseImm | (RotateAmt << 8);
+  }
+
   /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
   unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
                            SmallVectorImpl<MCFixup> &Fixups) const {
     unsigned SoImm = MI.getOperand(Op).getImm();
     unsigned Encoded =  ARM_AM::getT2SOImmVal(SoImm);
     assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
     return Encoded;
   }

test/MC/ARM/basic-arm-instructions.s

@ CHECK: add  r3, r1, r2, asr #32     @ encoding: [0x42,0x30,0x81,0xe0]
     add r0, r12, #40, #10
 @ CHECK: add  r0, r12, #40, #10       @ encoding: [0x28,0x05,0x8c,0xe2]
 
 @------------------------------------------------------------------------------
 @ ADDS
 @------------------------------------------------------------------------------
 
     adds r9, r8, #33, #20
-@ CHECK: adds  r9, r8, #33, #20        @ encoding: [0x21,0x9a,0x98,0xe2]
+@ CHECK: adds r9, r8, #135168           @ encoding: [0x21,0x9a,0x98,0xe2]
 
 @------------------------------------------------------------------------------
 @ AND
 @------------------------------------------------------------------------------
     and r10, r1, #0xf
     and r10, r1, r6
     and r10, r1, r6, lsl #10
     and r10, r1, r6, lsr #10

 @ CHECK: and  r10, r1, r6, lsr #10    @ encoding: [0x26,0xa5,0x01,0xe0]
 @ CHECK: and  r10, r1, r6, asr #10    @ encoding: [0x46,0xa5,0x01,0xe0]
 @ CHECK: and  r10, r1, r6, ror #10    @ encoding: [0x66,0xa5,0x01,0xe0]
 @ CHECK: and  r6, r7, r8, lsl r2      @ encoding: [0x18,0x62,0x07,0xe0]
 @ CHECK: and  r6, r7, r8, lsr r2      @ encoding: [0x38,0x62,0x07,0xe0]
 @ CHECK: and  r6, r7, r8, asr r2      @ encoding: [0x58,0x62,0x07,0xe0]
 @ CHECK: and  r6, r7, r8, ror r2      @ encoding: [0x78,0x62,0x07,0xe0]
 @ CHECK: and  r10, r1, r6, rrx        @ encoding: [0x66,0xa0,0x01,0xe0]
-@ CHECK: bic  r2, r3, #-2147483648    @ encoding: [0x02,0x21,0xc3,0xe3]
+@ CHECK: bic  r2, r3, #2147483648    @ encoding: [0x02,0x21,0xc3,0xe3]
 
 @ CHECK: and  r1, r1, #15             @ encoding: [0x0f,0x10,0x01,0xe2]
 @ CHECK: and  r10, r10, r1            @ encoding: [0x01,0xa0,0x0a,0xe0]
 @ CHECK: and  r10, r10, r1, lsl #10   @ encoding: [0x01,0xa5,0x0a,0xe0]
 @ CHECK: and  r10, r10, r1, lsr #10   @ encoding: [0x21,0xa5,0x0a,0xe0]
 @ CHECK: and  r10, r10, r1, lsr #10   @ encoding: [0x21,0xa5,0x0a,0xe0]
 @ CHECK: and  r10, r10, r1, asr #10   @ encoding: [0x41,0xa5,0x0a,0xe0]
 @ CHECK: and  r10, r10, r1, ror #10   @ encoding: [0x61,0xa5,0x0a,0xe0]
 @ CHECK: and  r6, r6, r7, lsl r2      @ encoding: [0x17,0x62,0x06,0xe0]
 @ CHECK: and  r6, r6, r7, lsr r2      @ encoding: [0x37,0x62,0x06,0xe0]
 @ CHECK: and  r6, r6, r7, asr r2      @ encoding: [0x57,0x62,0x06,0xe0]
 @ CHECK: and  r6, r6, r7, ror r2      @ encoding: [0x77,0x62,0x06,0xe0]
 @ CHECK: and  r10, r10, r1, rrx       @ encoding: [0x61,0xa0,0x0a,0xe0]
 
     @ Test right shift by 32, which is encoded as 0
     and r3, r1, r2, lsr #32
     and r3, r1, r2, asr #32
 @ CHECK: and  r3, r1, r2, lsr #32     @ encoding: [0x22,0x30,0x01,0xe0]
 @ CHECK: and  r3, r1, r2, asr #32     @ encoding: [0x42,0x30,0x01,0xe0]
 
     and r1, r9, #15, #14
-@ CHECK: and  r1, r9, #15, #14        @ encoding: [0x0f,0x17,0x09,0xe2]
+    and r1, r9, #60, #16
+@ CHECK: and  r1, r9, #3932160        @ encoding: [0x0f,0x17,0x09,0xe2]
+@ CHECK: and  r1, r9, #60, #16        @ encoding: [0x3c,0x18,0x09,0xe2]
 
 @------------------------------------------------------------------------------
 @ ANDS
 @------------------------------------------------------------------------------
 
     ands r6, r3, #127, #4
-@ CHECK: ands  r6, r3, #127, #4        @ encoding: [0x7f,0x62,0x13,0xe2]
+@ CHECK: ands r6, r3, #4026531847       @ encoding: [0x7f,0x62,0x13,0xe2]
 
 @------------------------------------------------------------------------------
 @ ASR
 @------------------------------------------------------------------------------
   asr r2, r4, #32
   asr r2, r4, #2
   asr r2, r4, #0
   asr r4, #2

 @ CHECK: bic  r10, r10, r1, rrx       @ encoding: [0x61,0xa0,0xca,0xe1]
 
     @ Test right shift by 32, which is encoded as 0
     bic r3, r1, r2, lsr #32
     bic r3, r1, r2, asr #32
 @ CHECK: bic  r3, r1, r2, lsr #32     @ encoding: [0x22,0x30,0xc1,0xe1]
 @ CHECK: bic  r3, r1, r2, asr #32     @ encoding: [0x42,0x30,0xc1,0xe1]
 
-        bic r0, r1, #90, #16
-@ CHECK: bic  r0, r1, #90, #16        @ encoding: [0x5a,0x08,0xc1,0xe3]
+        bic r0, r1, #180, #16
+@ CHECK: bic  r0, r1, #180, #16        @ encoding: [0xb4,0x08,0xc1,0xe3]
 
 @------------------------------------------------------------------------------
 @ BICS
 @------------------------------------------------------------------------------
 
         bics r5, r6, #240, #12
 @ CHECK: bics  r5, r6, #240, #12       @ encoding: [0xf0,0x56,0xd6,0xe3]
 

 @ CHECK: cmn  r1, r6, ror #10         @ encoding: [0x66,0x05,0x71,0xe1]
 @ CHECK: cmn  r7, r8, lsl r2          @ encoding: [0x18,0x02,0x77,0xe1]
 @ CHECK: cmn  sp, r8, lsr r2          @ encoding: [0x38,0x02,0x7d,0xe1]
 @ CHECK: cmn  r7, r8, asr r2          @ encoding: [0x58,0x02,0x77,0xe1]
 @ CHECK: cmn  r7, r8, ror r2          @ encoding: [0x78,0x02,0x77,0xe1]
 @ CHECK: cmn  r1, r6, rrx             @ encoding: [0x66,0x00,0x71,0xe1]
 
         cmn lr, #175, #28
-@ CHECK: cmn  lr, #175, #28           @ encoding: [0xaf,0x0e,0x7e,0xe3]
+@ CHECK: cmn lr, #2800                  @ encoding: [0xaf,0x0e,0x7e,0xe3]
 
 @------------------------------------------------------------------------------
 @ CMP
 @------------------------------------------------------------------------------
         cmp r1, #0xf
         cmp r1, r6
         cmp r1, r6, lsl #10
         cmp r1, r6, lsr #10

 @ CHECK: cmp  sp, r8, lsr r2          @ encoding: [0x38,0x02,0x5d,0xe1]
 @ CHECK: cmp  r7, r8, asr r2          @ encoding: [0x58,0x02,0x57,0xe1]
 @ CHECK: cmp  r7, r8, ror r2          @ encoding: [0x78,0x02,0x57,0xe1]
 @ CHECK: cmp  r1, r6, rrx             @ encoding: [0x66,0x00,0x51,0xe1]
 @ CHECK: cmn  r0, #2                  @ encoding: [0x02,0x00,0x70,0xe3]
 @ CHECK: cmp  lr, #0                    @ encoding: [0x00,0x00,0x5e,0xe3]
 
         cmp sp, #133, #18
-@ CHECK: cmp  sp, #133, #18           @ encoding: [0x85,0x09,0x5d,0xe3]
+@ CHECK: cmp sp, #2179072               @ encoding: [0x85,0x09,0x5d,0xe3]
 
 @------------------------------------------------------------------------------
 @ CPS
 @------------------------------------------------------------------------------
         cpsie  aif
         cps  #15
         cpsid  if, #10
 
@ CHECK: eor  r3, r1, r2, asr #32     @ encoding: [0x42,0x30,0x21,0xe0]
     eor r10, r7, #240, #20
 @ CHECK: eor  r10, r7, #240, #20      @ encoding: [0xf0,0xaa,0x27,0xe2]
 
 @------------------------------------------------------------------------------
 @ EORS
 @------------------------------------------------------------------------------
 
     eors r5, r5, #99, #30
-@ CHECK: eors  r5, r5, #99, #30        @ encoding: [0x63,0x5f,0x35,0xe2]
+@ CHECK: eors r5, r5, #396              @ encoding: [0x63,0x5f,0x35,0xe2]
 
 @------------------------------------------------------------------------------
 @ ISB
 @------------------------------------------------------------------------------
         isb sy
         isb
         isb #15
         isb #1

 @ CHECK: mov  r12, r8                 @ encoding: [0x08,0xc0,0xa0,0xe1]
 @ CHECK: mov  r2, r3                  @ encoding: [0x03,0x20,0xa0,0xe1]
 
 @------------------------------------------------------------------------------
 @ MOVS (immediate)
 @------------------------------------------------------------------------------
  
         movs r11, #99, #0
-@ CHECK: movs  r11, #99, #0            @ encoding: [0x63,0xb0,0xb0,0xe3]
+@ CHECK: movs  r11, #99                @ encoding: [0x63,0xb0,0xb0,0xe3]
 
 @------------------------------------------------------------------------------
 @ MOVT
 @------------------------------------------------------------------------------
         movt r3, #7
         movt r6, #0xffff
         movteq r4, #0xff0
 

 @ CHECK: msr  CPSR_fc, r0               @ encoding: [0x00,0xf0,0x29,0xe1]
 @ CHECK: msr  CPSR_fc, r0               @ encoding: [0x00,0xf0,0x29,0xe1]
 @ CHECK: msr  CPSR_fsx, r0              @ encoding: [0x00,0xf0,0x2e,0xe1]
 @ CHECK: msr  SPSR_fc, r0               @ encoding: [0x00,0xf0,0x69,0xe1]
 @ CHECK: msr  SPSR_fsxc, r0             @ encoding: [0x00,0xf0,0x6f,0xe1]
 @ CHECK: msr  CPSR_fsxc, r0             @ encoding: [0x00,0xf0,0x2f,0xe1]
 
         msr spsr_fc, #15, #16
-@ CHECK: msr  SPSR_fc, #15, #16       @ encoding: [0x0f,0xf8,0x69,0xe3]
+@ CHECK: msr SPSR_fc, #983040           @ encoding: [0x0f,0xf8,0x69,0xe3]
 
 @------------------------------------------------------------------------------
 @ MUL
 @------------------------------------------------------------------------------
         mul r5, r6, r7
         muls r5, r6, r7
         mulgt r5, r6, r7
         mulsle r5, r6, r7
@ CHECK: orrsgt  r4, r4, r5, rrx         @ encoding: [0x65,0x40,0x94,0xc1]
 
     @ Test right shift by 32, which is encoded as 0
     orr r3, r1, r2, lsr #32
     orr r3, r1, r2, asr #32
 @ CHECK: orr  r3, r1, r2, lsr #32     @ encoding: [0x22,0x30,0x81,0xe1]
 @ CHECK: orr  r3, r1, r2, asr #32     @ encoding: [0x42,0x30,0x81,0xe1]
 
     orr r9, pc, #233, #14
-@ CHECK: orr  r9, pc, #233, #14       @ encoding: [0xe9,0x97,0x8f,0xe3]
+@ CHECK: orr r9, pc, #61079552          @ encoding: [0xe9,0x97,0x8f,0xe3]
 
 @------------------------------------------------------------------------------
 @ ORRS
 @------------------------------------------------------------------------------
 
     orrs r5, sp, #144, #30
 @ CHECK: orrs  r5, sp, #144, #30       @ encoding: [0x90,0x5f,0x9d,0xe3] 
 

 @ CHECK: rsb  r4, r4, r5, ror #5      @ encoding: [0xe5,0x42,0x64,0xe0]
 @ CHECK: rsbgt  r6, r6, r7, lsl r9      @ encoding: [0x17,0x69,0x66,0xc0]
 @ CHECK: rsb  r6, r6, r7, lsr r9      @ encoding: [0x37,0x69,0x66,0xe0]
 @ CHECK: rsb  r6, r6, r7, asr r9      @ encoding: [0x57,0x69,0x66,0xe0]
 @ CHECK: rsb  r6, r6, r7, ror r9      @ encoding: [0x77,0x69,0x66,0xe0]
 @ CHECK: rsb  r4, r4, r5, rrx         @ encoding: [0x65,0x40,0x64,0xe0]
 
         rsb r9, r3, #255, #2
-@ CHECK: rsb  r9, r3, #255, #2        @ encoding: [0xff,0x91,0x63,0xe2]
+@ CHECK: rsb r9, r3, #3221225535        @ encoding: [0xff,0x91,0x63,0xe2]
 
 @------------------------------------------------------------------------------
 @ RSBS
 @------------------------------------------------------------------------------
 
         rsbs r10, r11, #99, #28
-@ CHECK: rsbs  r10, r11, #99, #28      @ encoding: [0x63,0xae,0x7b,0xe2]
+@ CHECK: rsbs r10, r11, #1584           @ encoding: [0x63,0xae,0x7b,0xe2]
 
 @------------------------------------------------------------------------------
 @ RSC
 @------------------------------------------------------------------------------
         rsc r4, r5, #0xf000
         rsc r4, r5, r6
         rsc r4, r5, r6, lsl #5
         rsclo r4, r5, r6, lsr #5

 @ CHECK: rsc  r4, r4, r5, asr #5      @ encoding: [0xc5,0x42,0xe4,0xe0]
 @ CHECK: rsc  r4, r4, r5, ror #5      @ encoding: [0xe5,0x42,0xe4,0xe0]
 @ CHECK: rscgt  r6, r6, r7, lsl r9      @ encoding: [0x17,0x69,0xe6,0xc0]
 @ CHECK: rsc  r6, r6, r7, lsr r9      @ encoding: [0x37,0x69,0xe6,0xe0]
 @ CHECK: rsc  r6, r6, r7, asr r9      @ encoding: [0x57,0x69,0xe6,0xe0]
 @ CHECK: rsc  r6, r6, r7, ror r9      @ encoding: [0x77,0x69,0xe6,0xe0]
 
          rsc    r11, r4, #91, #24
-@ CHECK: rsc  r11, r4, #91, #24       @ encoding: [0x5b,0xbc,0xe4,0xe2]
+@ CHECK: rsc  r11, r4, #23296         @ encoding: [0x5b,0xbc,0xe4,0xe2]
 
 @------------------------------------------------------------------------------
 @ RSCS
 @------------------------------------------------------------------------------
 
          rscs   r5, r12, #172, #16
 @ CHECK: rscs  r5, r12, #172, #16      @ encoding: [0xac,0x58,0xfc,0xe2]
 

 @ CHECK: sbc  r4, r4, r5, asr #5      @ encoding: [0xc5,0x42,0xc4,0xe0]
 @ CHECK: sbc  r4, r4, r5, ror #5      @ encoding: [0xe5,0x42,0xc4,0xe0]
 @ CHECK: sbc  r6, r6, r7, lsl r9      @ encoding: [0x17,0x69,0xc6,0xe0]
 @ CHECK: sbc  r6, r6, r7, lsr r9      @ encoding: [0x37,0x69,0xc6,0xe0]
 @ CHECK: sbc  r6, r6, r7, asr r9      @ encoding: [0x57,0x69,0xc6,0xe0]
 @ CHECK: sbc  r6, r6, r7, ror r9      @ encoding: [0x77,0x69,0xc6,0xe0]
 
          sbc    r0, r0, #33, #8
-@ CHECK: sbc  r0, r0, #33, #8         @ encoding: [0x21,0x04,0xc0,0xe2]
+@ CHECK: sbc r0, r0, #553648128         @ encoding: [0x21,0x04,0xc0,0xe2]
 
 @------------------------------------------------------------------------------
 @ SBCS
 @------------------------------------------------------------------------------
 
          sbcs   r9, r2, #30, #30
 @ CHECK: sbcs  r9, r2, #30, #30        @ encoding: [0x1e,0x9f,0xd2,0xe2]
  
@ CHECK: sub  r6, r6, r7, ror r9      @ encoding: [0x77,0x69,0x46,0xe0]
 
     @ Test right shift by 32, which is encoded as 0
     sub r3, r1, r2, lsr #32
     sub r3, r1, r2, asr #32
 @ CHECK: sub  r3, r1, r2, lsr #32     @ encoding: [0x22,0x30,0x41,0xe0]
 @ CHECK: sub  r3, r1, r2, asr #32     @ encoding: [0x42,0x30,0x41,0xe0]
 
     sub r4, r11, #255, #0
-@ CHECK: sub  r4, r11, #255, #0       @ encoding: [0xff,0x40,0x4b,0xe2]
+@ CHECK: sub r4, r11, #255              @ encoding: [0xff,0x40,0x4b,0xe2]
 
 @------------------------------------------------------------------------------
 @ SUBS
 @------------------------------------------------------------------------------
 
     subs r0, r3, #63, #2
-@ CHECK: subs  r0, r3, #63, #2         @ encoding: [0x3f,0x01,0x53,0xe2]
+@ CHECK: subs r0, r3, #3221225487       @ encoding: [0x3f,0x01,0x53,0xe2]
 
 @------------------------------------------------------------------------------
 @ SVC
 @------------------------------------------------------------------------------
         svc #16
         svc #0
         svc #0xffffff
 

 @ CHECK: teq  r4, r5, asr #5          @ encoding: [0xc5,0x02,0x34,0xe1]
 @ CHECK: teq  r4, r5, ror #5          @ encoding: [0xe5,0x02,0x34,0xe1]
 @ CHECK: teq  r6, r7, lsl r9          @ encoding: [0x17,0x09,0x36,0xe1]
 @ CHECK: teq  r6, r7, lsr r9          @ encoding: [0x37,0x09,0x36,0xe1]
 @ CHECK: teq  r6, r7, asr r9          @ encoding: [0x57,0x09,0x36,0xe1]
 @ CHECK: teq  r6, r7, ror r9          @ encoding: [0x77,0x09,0x36,0xe1]
 
         teq r11, #99, #30
-@ CHECK: teq  r11, #99, #30           @ encoding: [0x63,0x0f,0x3b,0xe3]
+@ CHECK: teq r11, #396                  @ encoding: [0x63,0x0f,0x3b,0xe3]
 
 @------------------------------------------------------------------------------
 @ TST
 @------------------------------------------------------------------------------
         tst r5, #0xf000
         tst r4, r5
         tst r4, r5, lsl #5
         tst r4, r5, lsr #5

 @ CHECK: tst  r4, r5, asr #5          @ encoding: [0xc5,0x02,0x14,0xe1]
 @ CHECK: tst  r4, r5, ror #5          @ encoding: [0xe5,0x02,0x14,0xe1]
 @ CHECK: tst  r6, r7, lsl r9          @ encoding: [0x17,0x09,0x16,0xe1]
 @ CHECK: tst  r6, r7, lsr r9          @ encoding: [0x37,0x09,0x16,0xe1]
 @ CHECK: tst  r6, r7, asr r9          @ encoding: [0x57,0x09,0x16,0xe1]
 @ CHECK: tst  r6, r7, ror r9          @ encoding: [0x77,0x09,0x16,0xe1]
 
         tst r5, #113, #10
-@ CHECK: tst  r5, #113, #10           @ encoding: [0x71,0x05,0x15,0xe3] 
+@ CHECK: tst r5, #473956352             @ encoding: [0x71,0x05,0x15,0xe3]
 
 @------------------------------------------------------------------------------
 @ UADD16/UADD8
 @------------------------------------------------------------------------------
         uadd16 r1, r2, r3
         uadd16gt r1, r2, r3
         uadd8 r1, r2, r3
         uadd8le r1, r2, r3

test/MC/ARM/diagnostics.s

@ Out of range immediate modifier values
         rscs   r5, r12, #172, #116
         sbc    r0, r0, #33, #81
         sbcs   r9, r2, #30, #29
         sub    r4, r11, #255, #1
         subs   r0, r3, #63, #3
         teq    r11, #99, #31
         tst    r5, #113, #11
 
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: adc    r10, r0, #220, #23
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: adcs   r5, r11, #88, #44
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: add    r0, r12, #40, #-10
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: adds   r9, r8, #33, #21
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: and    r1, r9, #15, #15
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: ands   r6, r3, #127, #40
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: bic    r0, r1, #90, #126
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: bics   r5, r6, #240, #13
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: cmn    lr, #175, #29
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: cmp    sp, #133, #19
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: eor    r10, r7, #240, #32
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: eors   r5, r5, #99, #31
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: mov    r9, #240, #-30
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: movs   r11, #99, #1
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: msr    spsr_fc, #15, #17
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: mvn    r8, #120, #5
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: mvns   r2, #55, #32
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: orr    r9, pc, #233, #-1
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: orrs   r5, sp, #144, #33
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: rsb    r9, r3, #255, #3
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: rsbs   r10, r11, #99, #128
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: rsc    r11, r4, #91, #25
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: rscs   r5, r12, #172, #116
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: sbc    r0, r0, #33, #81
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: sbcs   r9, r2, #30, #29
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: sub    r4, r11, #255, #1
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: subs   r0, r3, #63, #3
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: teq    r11, #99, #31
-@CHECK-ERRORS: error: immediate operand must an even number in the range [0,30]
+@CHECK-ERRORS: error: modified-immediate rotate operand must be an even number in the range [0,30]
 @CHECK-ERRORS: tst    r5, #113, #11
 
         @ Out of range 4 and 3 bit immediates on CDP[2]
 
         @ Out of range immediates for CDP/CDP2
         cdp  p7, #2, c1, c1, c1, #8
         cdp  p7, #1, c1, c1, c1, #8
         cdp2  p7, #2, c1, c1, c1, #8

test/MC/ARM/thumb-diagnostics.s

 @ CHECK-ERRORS:         add sp, #-1
 @ CHECK-ERRORS:                 ^
 @ CHECK-ERRORS: error: instruction requires: thumb2
 @ CHECK-ERRORS:         add sp, #3
 @ CHECK-ERRORS:                 ^
 @ CHECK-ERRORS: error: instruction requires: thumb2
 @ CHECK-ERRORS:         add sp, sp, #512
 @ CHECK-ERRORS:                     ^
-@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: instruction requires: arm
 @ CHECK-ERRORS:         add r2, sp, #1024
 @ CHECK-ERRORS:         ^
 
         add r2, sp, ip
 @ CHECK-ERRORS: error: source register must be the same as destination
 @ CHECK-ERRORS:         add r2, sp, ip
 @ CHECK-ERRORS:                     ^
 

test/MC/Disassembler/ARM/arm-tests.txt

 # RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mcpu=cortex-a9-mp | FileCheck %s
 
-# CHECK:  addpl r4, pc, #318767104
+# CHECK:  addpl r4, pc, #76, #10
 0x4c 0x45 0x8f 0x52
 
 # CHECK:  b #0
 0x00 0x00 0x00 0xea
 
 # CHECK:  bl  #7732
 0x8d 0x07 0x00 0xeb
 

 # CHECK: rfedb  #4!
 0x14 0x0 0x32 0xf9
 
 # CHECK: stc2l  p0, c0, [r2], #-96
 0x18 0x0 0x62 0xfc
 
 # CHECK: ldmgt  sp!, {r9}
 0x00 0x02 0xbd 0xc8
+
+
+#######################################################################
+# ARM modified immediate tests
+#######################################################################
+
+[0x37,0x2f,0xf0,0xe3]
+# CHECK: mvns r2, #55, #30
+
+[0x00 0x90,0x98,0xe2]
+# CHECK: adds r9, r8, #0{{$}}
+
+[0x08,0x21,0xc3,0xe3]
+# CHECK: bic   r2, r3, #8, #2
+
+[0x00,0x17,0x09,0xe2]
+# CHECK: and   r1, r9, #0, #14
+
+[0x3c,0x18,0x09,0xe2]
+# CHECK: and   r1, r9, #60, #16
+
+[0x74,0x62,0x13,0xe2]
+# CHECK: ands r6, r3, #116, #4
+
+[0xb4,0x08,0xc1,0xe3]
+# CHECK: bic   r0, r1, #180, #16
+
+[0xa0,0x0e,0x7e,0xe3]
+# CHECK: cmn lr, #160, #28
+
+[0x88,0x09,0x5d,0xe3]
+# CHECK: cmp sp, #136, #18
+
+[0x64,0x5f,0x35,0xe2]
+# CHECK: eors r5, r5, #100, #30
+
+[0x60,0xb0,0xb0,0xe3]
+# CHECK: movs  r11, #96{{$}}
+
+[0xf0,0xf8,0x69,0xe3]
+# CHECK: msr SPSR_fc, #240, #16
+
+[0xec,0x97,0x8f,0xe3]
+# CHECK: orr r9, pc, #236, #14
+
+[0xfc,0x91,0x63,0xe2]
+# CHECK: rsb r9, r3, #252, #2
+
+[0x64,0xae,0x7b,0xe2]
+# CHECK: rsbs r10, r11, #100, #28
+
+[0x5c,0xbc,0xe4,0xe2]
+# CHECK: rsc   r11, r4, #92, #24
+
+[0x84,0x04,0xc0,0xe2]
+# CHECK: sbc r0, r0, #132, #8
+
+[0xf0,0x40,0x4b,0xe2]
+# CHECK: sub r4, r11, #240{{$}}
+
+[0x3c,0x01,0x53,0xe2]
+# CHECK: subs r0, r3, #60, #2
+
+[0x64,0x0f,0x3b,0xe3]
+# CHECK: teq r11, #100, #30
+
+[0x78,0x05,0x15,0xe3]
+# CHECK: tst r5, #120, #10