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Differential D137333

[AggressiveInstCombine] Avoid load merge/widen if stores are present b/w loads
ClosedPublic

Authored by bipmis on Nov 3 2022, 5:47 AM.

Details

Reviewers
dmgreen
spatel
asmok-g
eaeltsin
joanahalili
Commits
rG150fc73ddab6: [AggressiveInstCombine] Avoid load merge/widen if stores are present b/w loads
Summary

This patch is to address the test cases in which the load has to be inserted at a right point. This happens when there is a store b/w the loads.

This patch reverts the loads merge in all cases when stores are present b/w loads and will eventually be replaced with proper fix and test cases in https://reviews.llvm.org/D137201

Diff Detail

Event Timeline

bipmis requested review of this revision.Nov 3 2022, 5:47 AM
bipmis created this revision.
bipmis edited the summary of this revision. (Show Details)
dmgreen accepted this revision.Nov 3 2022, 5:54 AM

Sounds sensible to me in the short term. LGTM.

You could add a TODO comment about working on reenabling it with AA once we've worked through all the edgecases.

llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
732–733

Perhaps add a TODO or reword this comment.

This revision is now accepted and ready to land.Nov 3 2022, 5:54 AM
Harbormaster completed remote builds in B195912: Diff 472910.Nov 3 2022, 7:00 AM
Closed by commit rG150fc73ddab6: [AggressiveInstCombine] Avoid load merge/widen if stores are present b/w loads (authored by bipmis). · Explain WhyNov 3 2022, 7:32 AM
This revision was automatically updated to reflect the committed changes.
bipmis added a commit: rG150fc73ddab6: [AggressiveInstCombine] Avoid load merge/widen if stores are present b/w loads.
dmgreen mentioned this in D135137: [AggressiveInstCombine] Load merge the reverse load pattern of consecutive loads..Nov 3 2022, 12:15 PM

Revision Contents

PathSize
llvm/
lib/
Transforms/
AggressiveInstCombine/
6 lines
test/
Transforms/
AggressiveInstCombine/
AArch64/
182 lines
X86/
208 lines

Diff 472932

llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp

Show First 20 Lines • Show All 723 Lines • ▼ Show 20 Linesstatic bool foldLoadsRecursive(Value *V, LoadOps &LOps, const DataLayout &DL,
uint64_t LoadSize2 = LI2->getType()->getPrimitiveSizeInBits(); uint64_t LoadSize2 = LI2->getType()->getPrimitiveSizeInBits();
if (Load1Ptr != Load2Ptr || LoadSize1 != LoadSize2) if (Load1Ptr != Load2Ptr || LoadSize1 != LoadSize2)
return false; return false;
// Support Loadsizes greater or equal to 8bits and only power of 2. // Support Loadsizes greater or equal to 8bits and only power of 2.
if (LoadSize1 < 8 || !isPowerOf2_64(LoadSize1)) if (LoadSize1 < 8 || !isPowerOf2_64(LoadSize1))
return false; return false;
// Alias Analysis to check for store b/w the loads. // TODO: Alias Analysis to check for stores b/w the loads.
// Currently bail out if there are stores b/w the loads.
dmgreenUnsubmitted
Not Done
ReplyInline Actions

Perhaps add a TODO or reword this comment.

dmgreen: Perhaps add a TODO or reword this comment.
LoadInst *Start = LI1, *End = LI2; LoadInst *Start = LI1, *End = LI2;
if (!LI1->comesBefore(LI2)) if (!LI1->comesBefore(LI2))
std::swap(Start, End); std::swap(Start, End);
MemoryLocation Loc = MemoryLocation::get(End);
unsigned NumScanned = 0; unsigned NumScanned = 0;
for (Instruction &Inst : for (Instruction &Inst :
make_range(Start->getIterator(), End->getIterator())) { make_range(Start->getIterator(), End->getIterator())) {
if (Inst.mayWriteToMemory() && isModSet(AA.getModRefInfo(&Inst, Loc))) if (Inst.mayWriteToMemory())
return false; return false;
if (++NumScanned > MaxInstrsToScan) if (++NumScanned > MaxInstrsToScan)
return false; return false;
} }
// Big endian swap the shifts // Big endian swap the shifts
if (IsBigEndian) if (IsBigEndian)
std::swap(ShAmt1, ShAmt2); std::swap(ShAmt1, ShAmt2);
▲ Show 20 Lines • Show All 215 Lines • Show Last 20 Lines

llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll

Show First 20 Lines • Show All 136 Lines • ▼ Show 20 Lines;
%o1 = or i32 %s1, %s2 %o1 = or i32 %s1, %s2
%o2 = or i32 %o1, %s3 %o2 = or i32 %o1, %s3
%o3 = or i32 %o2, %e4 %o3 = or i32 %o2, %e4
ret i32 %o3 ret i32 %o3
} }
define i32 @loadCombine_4consecutive_alias(ptr %p) { define i32 @loadCombine_4consecutive_alias(ptr %p) {
; LE-LABEL: @loadCombine_4consecutive_alias( ; ALL-LABEL: @loadCombine_4consecutive_alias(
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1 ; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
; LE-NEXT: store i8 10, ptr [[P]], align 1 ; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
; LE-NEXT: ret i32 [[L1]] ; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
; ; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
; BE-LABEL: @loadCombine_4consecutive_alias( ; ALL-NEXT: store i8 10, ptr [[P]], align 1
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1 ; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2 ; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
; BE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3 ; ALL-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 ; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
; BE-NEXT: store i8 10, ptr [[P]], align 1 ; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 ; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 ; ALL-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
; BE-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 ; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 ; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 ; ALL-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 ; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
; BE-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 ; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8 ; ALL-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16 ; ALL-NEXT: ret i32 [[O3]]
; BE-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; BE-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
; BE-NEXT: ret i32 [[O3]]
; ;
%p1 = getelementptr i8, ptr %p, i32 1 %p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 2 %p2 = getelementptr i8, ptr %p, i32 2
%p3 = getelementptr i8, ptr %p, i32 3 %p3 = getelementptr i8, ptr %p, i32 3
%l1 = load i8, ptr %p %l1 = load i8, ptr %p
store i8 10, i8* %p store i8 10, i8* %p
%l2 = load i8, ptr %p1 %l2 = load i8, ptr %p1
%l3 = load i8, ptr %p2 %l3 = load i8, ptr %p2
Show All 10 Lines;
%o1 = or i32 %e1, %s2 %o1 = or i32 %e1, %s2
%o2 = or i32 %o1, %s3 %o2 = or i32 %o1, %s3
%o3 = or i32 %o2, %s4 %o3 = or i32 %o2, %s4
ret i32 %o3 ret i32 %o3
} }
define i32 @loadCombine_4consecutive_alias_BE(ptr %p) { define i32 @loadCombine_4consecutive_alias_BE(ptr %p) {
; LE-LABEL: @loadCombine_4consecutive_alias_BE( ; ALL-LABEL: @loadCombine_4consecutive_alias_BE(
; LE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1 ; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
; LE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2 ; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
; LE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3 ; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
; LE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 ; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
; LE-NEXT: store i8 10, ptr [[P]], align 1 ; ALL-NEXT: store i8 10, ptr [[P]], align 1
; LE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 ; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
; LE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 ; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
; LE-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 ; ALL-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
; LE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 ; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
; LE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 ; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; LE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 ; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
; LE-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 ; ALL-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
; LE-NEXT: [[S1:%.*]] = shl i32 [[E1]], 24 ; ALL-NEXT: [[S1:%.*]] = shl i32 [[E1]], 24
; LE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16 ; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
; LE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 8 ; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 8
; LE-NEXT: [[O1:%.*]] = or i32 [[S1]], [[S2]] ; ALL-NEXT: [[O1:%.*]] = or i32 [[S1]], [[S2]]
; LE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]] ; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; LE-NEXT: [[O3:%.*]] = or i32 [[O2]], [[E4]] ; ALL-NEXT: [[O3:%.*]] = or i32 [[O2]], [[E4]]
; LE-NEXT: ret i32 [[O3]] ; ALL-NEXT: ret i32 [[O3]]
;
; BE-LABEL: @loadCombine_4consecutive_alias_BE(
; BE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
; BE-NEXT: store i8 10, ptr [[P]], align 1
; BE-NEXT: ret i32 [[L1]]
; ;
%p1 = getelementptr i8, ptr %p, i32 1 %p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 2 %p2 = getelementptr i8, ptr %p, i32 2
%p3 = getelementptr i8, ptr %p, i32 3 %p3 = getelementptr i8, ptr %p, i32 3
%l1 = load i8, ptr %p %l1 = load i8, ptr %p
store i8 10, i8* %p store i8 10, i8* %p
%l2 = load i8, ptr %p1 %l2 = load i8, ptr %p1
%l3 = load i8, ptr %p2 %l3 = load i8, ptr %p2
▲ Show 20 Lines • Show All 1,536 Lines • ▼ Show 20 Lines;
%e1 = zext i8 %l1 to i16 %e1 = zext i8 %l1 to i16
%e2 = zext i8 %l2 to i16 %e2 = zext i8 %l2 to i16
%s2 = shl i16 %e2, 8 %s2 = shl i16 %e2, 8
%o1 = or i16 %e1, %s2 %o1 = or i16 %e1, %s2
ret i16 %o1 ret i16 %o1
} }
define i32 @loadCombine_4consecutive_badinsert(ptr %p) { define i32 @loadCombine_4consecutive_badinsert(ptr %p) {
; LE-LABEL: @loadCombine_4consecutive_badinsert( ; ALL-LABEL: @loadCombine_4consecutive_badinsert(
; LE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1 ; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
; LE-NEXT: store i8 0, ptr [[P1]], align 1 ; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P]], align 1 ; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
; LE-NEXT: ret i32 [[L1]] ; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
; ; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
; BE-LABEL: @loadCombine_4consecutive_badinsert( ; ALL-NEXT: store i8 0, ptr [[P1]], align 1
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1 ; ALL-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2 ; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
; BE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3 ; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 ; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 ; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
; BE-NEXT: store i8 0, ptr [[P1]], align 1 ; ALL-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
; BE-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 ; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 ; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 ; ALL-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 ; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 ; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; BE-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 ; ALL-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8 ; ALL-NEXT: ret i32 [[O3]]
; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
; BE-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; BE-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
; BE-NEXT: ret i32 [[O3]]
; ;
%p1 = getelementptr i8, ptr %p, i32 1 %p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 2 %p2 = getelementptr i8, ptr %p, i32 2
%p3 = getelementptr i8, ptr %p, i32 3 %p3 = getelementptr i8, ptr %p, i32 3
%l2 = load i8, ptr %p1 %l2 = load i8, ptr %p1
%l3 = load i8, ptr %p2 %l3 = load i8, ptr %p2
store i8 0, ptr %p1, align 1 store i8 0, ptr %p1, align 1
%l4 = load i8, ptr %p3 %l4 = load i8, ptr %p3
Show All 10 Lines;
%o1 = or i32 %e1, %s2 %o1 = or i32 %e1, %s2
%o2 = or i32 %o1, %s3 %o2 = or i32 %o1, %s3
%o3 = or i32 %o2, %s4 %o3 = or i32 %o2, %s4
ret i32 %o3 ret i32 %o3
} }
define i32 @loadCombine_4consecutive_badinsert2(ptr %p) { define i32 @loadCombine_4consecutive_badinsert2(ptr %p) {
; LE-LABEL: @loadCombine_4consecutive_badinsert2( ; ALL-LABEL: @loadCombine_4consecutive_badinsert2(
; LE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 3 ; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
; LE-NEXT: store i8 0, ptr [[P3]], align 1 ; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P]], align 1 ; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
; LE-NEXT: ret i32 [[L1]] ; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
; ; ALL-NEXT: store i8 0, ptr [[P3]], align 1
; BE-LABEL: @loadCombine_4consecutive_badinsert2( ; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1 ; ALL-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2 ; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
; BE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3 ; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 ; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; BE-NEXT: store i8 0, ptr [[P3]], align 1 ; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 ; ALL-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
; BE-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 ; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 ; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 ; ALL-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 ; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 ; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; BE-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 ; ALL-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8 ; ALL-NEXT: ret i32 [[O3]]
; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
; BE-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; BE-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
; BE-NEXT: ret i32 [[O3]]
; ;
%p1 = getelementptr i8, ptr %p, i32 1 %p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 2 %p2 = getelementptr i8, ptr %p, i32 2
%p3 = getelementptr i8, ptr %p, i32 3 %p3 = getelementptr i8, ptr %p, i32 3
%l2 = load i8, ptr %p1 %l2 = load i8, ptr %p1
store i8 0, ptr %p3, align 1 store i8 0, ptr %p3, align 1
%l3 = load i8, ptr %p2 %l3 = load i8, ptr %p2
%l4 = load i8, ptr %p3 %l4 = load i8, ptr %p3
Show All 16 Lines

llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll

Show First 20 Lines • Show All 144 Lines • ▼ Show 20 Lines;
%o1 = or i32 %s1, %s2 %o1 = or i32 %s1, %s2
%o2 = or i32 %o1, %s3 %o2 = or i32 %o1, %s3
%o3 = or i32 %o2, %e4 %o3 = or i32 %o2, %e4
ret i32 %o3 ret i32 %o3
} }
define i32 @loadCombine_4consecutive_alias(ptr %p) { define i32 @loadCombine_4consecutive_alias(ptr %p) {
; LE-LABEL: @loadCombine_4consecutive_alias( ; ALL-LABEL: @loadCombine_4consecutive_alias(
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1 ; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
; LE-NEXT: store i8 10, ptr [[P]], align 1 ; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
; LE-NEXT: ret i32 [[L1]] ; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
; ; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
; BE-LABEL: @loadCombine_4consecutive_alias( ; ALL-NEXT: store i8 10, ptr [[P]], align 1
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1 ; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2 ; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
; BE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3 ; ALL-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 ; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
; BE-NEXT: store i8 10, ptr [[P]], align 1 ; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 ; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 ; ALL-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
; BE-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 ; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 ; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 ; ALL-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 ; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
; BE-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 ; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8 ; ALL-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16 ; ALL-NEXT: ret i32 [[O3]]
; BE-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; BE-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
; BE-NEXT: ret i32 [[O3]]
; ;
%p1 = getelementptr i8, ptr %p, i32 1 %p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 2 %p2 = getelementptr i8, ptr %p, i32 2
%p3 = getelementptr i8, ptr %p, i32 3 %p3 = getelementptr i8, ptr %p, i32 3
%l1 = load i8, ptr %p %l1 = load i8, ptr %p
store i8 10, i8* %p store i8 10, i8* %p
%l2 = load i8, ptr %p1 %l2 = load i8, ptr %p1
%l3 = load i8, ptr %p2 %l3 = load i8, ptr %p2
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%o1 = or i32 %e1, %s2 %o1 = or i32 %e1, %s2
%o2 = or i32 %o1, %s3 %o2 = or i32 %o1, %s3
%o3 = or i32 %o2, %s4 %o3 = or i32 %o2, %s4
ret i32 %o3 ret i32 %o3
} }
define i32 @loadCombine_4consecutive_alias_BE(ptr %p) { define i32 @loadCombine_4consecutive_alias_BE(ptr %p) {
; LE-LABEL: @loadCombine_4consecutive_alias_BE( ; ALL-LABEL: @loadCombine_4consecutive_alias_BE(
; LE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1 ; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
; LE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2 ; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
; LE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3 ; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
; LE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 ; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
; LE-NEXT: store i8 10, ptr [[P]], align 1 ; ALL-NEXT: store i8 10, ptr [[P]], align 1
; LE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 ; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
; LE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 ; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
; LE-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 ; ALL-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
; LE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 ; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
; LE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 ; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; LE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 ; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
; LE-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 ; ALL-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
; LE-NEXT: [[S1:%.*]] = shl i32 [[E1]], 24 ; ALL-NEXT: [[S1:%.*]] = shl i32 [[E1]], 24
; LE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16 ; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
; LE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 8 ; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 8
; LE-NEXT: [[O1:%.*]] = or i32 [[S1]], [[S2]] ; ALL-NEXT: [[O1:%.*]] = or i32 [[S1]], [[S2]]
; LE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]] ; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; LE-NEXT: [[O3:%.*]] = or i32 [[O2]], [[E4]] ; ALL-NEXT: [[O3:%.*]] = or i32 [[O2]], [[E4]]
; LE-NEXT: ret i32 [[O3]] ; ALL-NEXT: ret i32 [[O3]]
;
; BE-LABEL: @loadCombine_4consecutive_alias_BE(
; BE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
; BE-NEXT: store i8 10, ptr [[P]], align 1
; BE-NEXT: ret i32 [[L1]]
; ;
%p1 = getelementptr i8, ptr %p, i32 1 %p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 2 %p2 = getelementptr i8, ptr %p, i32 2
%p3 = getelementptr i8, ptr %p, i32 3 %p3 = getelementptr i8, ptr %p, i32 3
%l1 = load i8, ptr %p %l1 = load i8, ptr %p
store i8 10, i8* %p store i8 10, i8* %p
%l2 = load i8, ptr %p1 %l2 = load i8, ptr %p1
%l3 = load i8, ptr %p2 %l3 = load i8, ptr %p2
▲ Show 20 Lines • Show All 1,619 Lines • ▼ Show 20 Lines;
%o1 = or i32 %e1, %s2 %o1 = or i32 %e1, %s2
%o2 = or i32 %o1, %s3 %o2 = or i32 %o1, %s3
%o3 = or i32 %o2, %s4 %o3 = or i32 %o2, %s4
ret i32 %o3 ret i32 %o3
} }
define i16 @loadCombine_2consecutive_badinsert(ptr %p) { define i16 @loadCombine_2consecutive_badinsert(ptr %p) {
; LE-LABEL: @loadCombine_2consecutive_badinsert( ; ALL-LABEL: @loadCombine_2consecutive_badinsert(
; LE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1 ; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
; LE-NEXT: store i8 0, ptr [[P1]], align 1 ; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
; LE-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 1 ; ALL-NEXT: store i8 0, ptr [[P1]], align 1
; LE-NEXT: ret i16 [[L1]] ; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
; ; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i16
; BE-LABEL: @loadCombine_2consecutive_badinsert( ; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i16
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1 ; ALL-NEXT: [[S2:%.*]] = shl i16 [[E2]], 8
; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 ; ALL-NEXT: [[O1:%.*]] = or i16 [[E1]], [[S2]]
; BE-NEXT: store i8 0, ptr [[P1]], align 1 ; ALL-NEXT: ret i16 [[O1]]
; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i16
; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i16
; BE-NEXT: [[S2:%.*]] = shl i16 [[E2]], 8
; BE-NEXT: [[O1:%.*]] = or i16 [[E1]], [[S2]]
; BE-NEXT: ret i16 [[O1]]
; ;
%p1 = getelementptr i8, ptr %p, i32 1 %p1 = getelementptr i8, ptr %p, i32 1
%l2 = load i8, ptr %p1 %l2 = load i8, ptr %p1
store i8 0, ptr %p1, align 1 store i8 0, ptr %p1, align 1
%l1 = load i8, ptr %p %l1 = load i8, ptr %p
%e1 = zext i8 %l1 to i16 %e1 = zext i8 %l1 to i16
%e2 = zext i8 %l2 to i16 %e2 = zext i8 %l2 to i16
%s2 = shl i16 %e2, 8 %s2 = shl i16 %e2, 8
%o1 = or i16 %e1, %s2 %o1 = or i16 %e1, %s2
ret i16 %o1 ret i16 %o1
} }
define i32 @loadCombine_4consecutive_badinsert(ptr %p) { define i32 @loadCombine_4consecutive_badinsert(ptr %p) {
; LE-LABEL: @loadCombine_4consecutive_badinsert( ; ALL-LABEL: @loadCombine_4consecutive_badinsert(
; LE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1 ; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
; LE-NEXT: store i8 0, ptr [[P1]], align 1 ; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P]], align 1 ; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
; LE-NEXT: ret i32 [[L1]] ; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
; ; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
; BE-LABEL: @loadCombine_4consecutive_badinsert( ; ALL-NEXT: store i8 0, ptr [[P1]], align 1
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1 ; ALL-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2 ; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
; BE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3 ; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 ; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 ; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
; BE-NEXT: store i8 0, ptr [[P1]], align 1 ; ALL-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
; BE-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 ; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 ; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 ; ALL-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 ; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 ; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; BE-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 ; ALL-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8 ; ALL-NEXT: ret i32 [[O3]]
; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
; BE-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; BE-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
; BE-NEXT: ret i32 [[O3]]
; ;
%p1 = getelementptr i8, ptr %p, i32 1 %p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 2 %p2 = getelementptr i8, ptr %p, i32 2
%p3 = getelementptr i8, ptr %p, i32 3 %p3 = getelementptr i8, ptr %p, i32 3
%l2 = load i8, ptr %p1 %l2 = load i8, ptr %p1
%l3 = load i8, ptr %p2 %l3 = load i8, ptr %p2
store i8 0, ptr %p1, align 1 store i8 0, ptr %p1, align 1
%l4 = load i8, ptr %p3 %l4 = load i8, ptr %p3
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%o1 = or i32 %e1, %s2 %o1 = or i32 %e1, %s2
%o2 = or i32 %o1, %s3 %o2 = or i32 %o1, %s3
%o3 = or i32 %o2, %s4 %o3 = or i32 %o2, %s4
ret i32 %o3 ret i32 %o3
} }
define i32 @loadCombine_4consecutive_badinsert2(ptr %p) { define i32 @loadCombine_4consecutive_badinsert2(ptr %p) {
; LE-LABEL: @loadCombine_4consecutive_badinsert2( ; ALL-LABEL: @loadCombine_4consecutive_badinsert2(
; LE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 3 ; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
; LE-NEXT: store i8 0, ptr [[P3]], align 1 ; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P]], align 1 ; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
; LE-NEXT: ret i32 [[L1]] ; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
; ; ALL-NEXT: store i8 0, ptr [[P3]], align 1
; BE-LABEL: @loadCombine_4consecutive_badinsert2( ; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1 ; ALL-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2 ; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
; BE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3 ; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 ; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
; BE-NEXT: store i8 0, ptr [[P3]], align 1 ; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 ; ALL-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
; BE-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 ; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 ; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 ; ALL-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 ; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 ; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; BE-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 ; ALL-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8 ; ALL-NEXT: ret i32 [[O3]]
; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
; BE-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
; BE-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
; BE-NEXT: ret i32 [[O3]]
; ;
%p1 = getelementptr i8, ptr %p, i32 1 %p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 2 %p2 = getelementptr i8, ptr %p, i32 2
%p3 = getelementptr i8, ptr %p, i32 3 %p3 = getelementptr i8, ptr %p, i32 3
%l2 = load i8, ptr %p1 %l2 = load i8, ptr %p1
store i8 0, ptr %p3, align 1 store i8 0, ptr %p3, align 1
%l3 = load i8, ptr %p2 %l3 = load i8, ptr %p2
%l4 = load i8, ptr %p3 %l4 = load i8, ptr %p3
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