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Differential D13299

[SystemZ] Add assembly instructions for obtaining clock values as well as CPU features
ClosedPublic

Authored by joncmu on Sep 30 2015, 10:29 AM.

Details

Reviewers
uweigand
Commits
rGcf1670a095dd: [SystemZ] Add assembly instructions for obtaining clock values as well as CPU…
rL249015: [SystemZ] Add assembly instructions for obtaining clock values as well as CPU…
Summary

Provide assembler support for STCK, STCKF, STCKE, and STFLE

Diff Detail

Repository
rL LLVM

Event Timeline

joncmu updated this revision to Diff 36127.Sep 30 2015, 10:29 AM
joncmu retitled this revision from to [SystemZ] Add assembly instructions for obtaining clock values as well as CPU features.
joncmu updated this object.
joncmu added a reviewer: uweigand.
joncmu set the repository for this revision to rL LLVM.
uweigand accepted this revision.Oct 1 2015, 7:29 AM
uweigand edited edge metadata.

LGTM, thanks!

This revision is now accepted and ready to land.Oct 1 2015, 7:29 AM
Closed by commit rL249015: [SystemZ] Add assembly instructions for obtaining clock values as well as CPU… (authored by uweigand). · Explain WhyOct 1 2015, 7:45 AM
This revision was automatically updated to reflect the committed changes.
smd mentioned this in D131343: [RISC-V][HWASAN] Add support for lowering HWASAN intrinsic for RISC-V.Aug 30 2022, 11:34 PM

Revision Contents

PathSize
lib/
Target/
SystemZ/
20 lines
test/
MC/
Disassembler/
SystemZ/
74 lines
SystemZ/
56 lines

Diff 36127

lib/Target/SystemZ/SystemZInstrInfo.td

Show First 20 Lines • Show All 1,456 Lines • ▼ Show 20 Lineslet usesCustomInserter = 1 in {
def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>; def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
} }
// Search a block of memory for a character. // Search a block of memory for a character.
let mayLoad = 1, Defs = [CC], Uses = [R0L] in let mayLoad = 1, Defs = [CC], Uses = [R0L] in
defm SRST : StringRRE<"srst", 0xb25e, z_search_string>; defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
// Other instructions for inline assembly
let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
def STCK : InstS<0xB205, (outs), (ins bdaddr12only:$BD2),
"stck\t$BD2",
[]>;
let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
def STCKF : InstS<0xB27C, (outs), (ins bdaddr12only:$BD2),
"stckf\t$BD2",
[]>;
let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
def STCKE : InstS<0xB278, (outs), (ins bdaddr12only:$BD2),
"stcke\t$BD2",
[]>;
let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
def STFLE : InstS<0xB2B0, (outs), (ins bdaddr12only:$BD2),
"stfle\t$BD2",
[]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Peepholes. // Peepholes.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Use AL* for GR64 additions of unsigned 32-bit values. // Use AL* for GR64 additions of unsigned 32-bit values.
defm : ZXB<add, GR64, ALGFR>; defm : ZXB<add, GR64, ALGFR>;
def : Pat<(add GR64:$src1, imm64zx32:$src2), def : Pat<(add GR64:$src1, imm64zx32:$src2),
(ALGFI GR64:$src1, imm64zx32:$src2)>; (ALGFI GR64:$src1, imm64zx32:$src2)>;
Show All 37 Lines

test/MC/Disassembler/SystemZ/insns.txt

Show First 20 Lines • Show All 7,531 Lines • ▼ Show 20 Lines
0xe3 0x0f 0x1f 0xff 0x7f 0xc3 0xe3 0x0f 0x1f 0xff 0x7f 0xc3
# CHECK: stch %r15, 0 # CHECK: stch %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0xc3 0xe3 0xf0 0x00 0x00 0x00 0xc3
# CHECK: stcy %r0, -524288 # CHECK: stcy %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0x72 0xe3 0x00 0x00 0x00 0x80 0x72
# CHECK: stck 0
0xb2 0x05 0x00 0x00
# CHECK: stck 0(%r1)
0xb2 0x05 0x10 0x00
#CHECK: stck 0(%r15)
0xb2 0x05 0xf0 0x00
#CHECK: stck 4095
0xb2 0x05 0x0f 0xff
#CHECK: stck 4095(%r1)
0xb2 0x05 0x1f 0xff
#CHECK: stck 4095(%r15)
0xb2 0x05 0xff 0xff
# CHECK: stckf 0
0xb2 0x7c 0x00 0x00
# CHECK: stckf 0(%r1)
0xb2 0x7c 0x10 0x00
#CHECK: stckf 0(%r15)
0xb2 0x7c 0xf0 0x00
#CHECK: stckf 4095
0xb2 0x7c 0x0f 0xff
#CHECK: stckf 4095(%r1)
0xb2 0x7c 0x1f 0xff
#CHECK: stckf 4095(%r15)
0xb2 0x7c 0xff 0xff
# CHECK: stcke 0
0xb2 0x78 0x00 0x00
# CHECK: stcke 0(%r1)
0xb2 0x78 0x10 0x00
#CHECK: stcke 0(%r15)
0xb2 0x78 0xf0 0x00
#CHECK: stcke 4095
0xb2 0x78 0x0f 0xff
#CHECK: stcke 4095(%r1)
0xb2 0x78 0x1f 0xff
#CHECK: stcke 4095(%r15)
0xb2 0x78 0xff 0xff
# CHECK: stfle 0
0xb2 0xb0 0x00 0x00
# CHECK: stfle 0(%r1)
0xb2 0xb0 0x10 0x00
#CHECK: stfle 0(%r15)
0xb2 0xb0 0xf0 0x00
#CHECK: stfle 4095
0xb2 0xb0 0x0f 0xff
#CHECK: stfle 4095(%r1)
0xb2 0xb0 0x1f 0xff
#CHECK: stfle 4095(%r15)
0xb2 0xb0 0xff 0xff
# CHECK: stcy %r0, -1 # CHECK: stcy %r0, -1
0xe3 0x00 0x0f 0xff 0xff 0x72 0xe3 0x00 0x0f 0xff 0xff 0x72
# CHECK: stcy %r0, 0 # CHECK: stcy %r0, 0
0xe3 0x00 0x00 0x00 0x00 0x72 0xe3 0x00 0x00 0x00 0x00 0x72
# CHECK: stcy %r0, 1 # CHECK: stcy %r0, 1
0xe3 0x00 0x00 0x01 0x00 0x72 0xe3 0x00 0x00 0x01 0x00 0x72
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test/MC/SystemZ/insn-good.s

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,940 Lines • ▼ Show 20 Lines#CHECK: stc %r15, 0 # encoding: [0x42,0xf0,0x00,0x00]
stc %r0, 0 stc %r0, 0
stc %r0, 4095 stc %r0, 4095
stc %r0, 0(%r1) stc %r0, 0(%r1)
stc %r0, 0(%r15) stc %r0, 0(%r15)
stc %r0, 4095(%r1,%r15) stc %r0, 4095(%r1,%r15)
stc %r0, 4095(%r15,%r1) stc %r0, 4095(%r15,%r1)
stc %r15, 0 stc %r15, 0
#CHECK: stck 0 # encoding: [0xb2,0x05,0x00,0x00]
#CHECK: stck 0(%r1) # encoding: [0xb2,0x05,0x10,0x00]
#CHECK: stck 0(%r15) # encoding: [0xb2,0x05,0xf0,0x00]
#CHECK: stck 4095 # encoding: [0xb2,0x05,0x0f,0xff]
#CHECK: stck 4095(%r1) # encoding: [0xb2,0x05,0x1f,0xff]
#CHECK: stck 4095(%r15) # encoding: [0xb2,0x05,0xff,0xff]
stck 0
stck 0(%r1)
stck 0(%r15)
stck 4095
stck 4095(%r1)
stck 4095(%r15)
#CHECK: stckf 0 # encoding: [0xb2,0x7c,0x00,0x00]
#CHECK: stckf 0(%r1) # encoding: [0xb2,0x7c,0x10,0x00]
#CHECK: stckf 0(%r15) # encoding: [0xb2,0x7c,0xf0,0x00]
#CHECK: stckf 4095 # encoding: [0xb2,0x7c,0x0f,0xff]
#CHECK: stckf 4095(%r1) # encoding: [0xb2,0x7c,0x1f,0xff]
#CHECK: stckf 4095(%r15) # encoding: [0xb2,0x7c,0xff,0xff]
stckf 0
stckf 0(%r1)
stckf 0(%r15)
stckf 4095
stckf 4095(%r1)
stckf 4095(%r15)
#CHECK: stcke 0 # encoding: [0xb2,0x78,0x00,0x00]
#CHECK: stcke 0(%r1) # encoding: [0xb2,0x78,0x10,0x00]
#CHECK: stcke 0(%r15) # encoding: [0xb2,0x78,0xf0,0x00]
#CHECK: stcke 4095 # encoding: [0xb2,0x78,0x0f,0xff]
#CHECK: stcke 4095(%r1) # encoding: [0xb2,0x78,0x1f,0xff]
#CHECK: stcke 4095(%r15) # encoding: [0xb2,0x78,0xff,0xff]
stcke 0
stcke 0(%r1)
stcke 0(%r15)
stcke 4095
stcke 4095(%r1)
stcke 4095(%r15)
#CHECK: stfle 0 # encoding: [0xb2,0xb0,0x00,0x00]
#CHECK: stfle 0(%r1) # encoding: [0xb2,0xb0,0x10,0x00]
#CHECK: stfle 0(%r15) # encoding: [0xb2,0xb0,0xf0,0x00]
#CHECK: stfle 4095 # encoding: [0xb2,0xb0,0x0f,0xff]
#CHECK: stfle 4095(%r1) # encoding: [0xb2,0xb0,0x1f,0xff]
#CHECK: stfle 4095(%r15) # encoding: [0xb2,0xb0,0xff,0xff]
stfle 0
stfle 0(%r1)
stfle 0(%r15)
stfle 4095
stfle 4095(%r1)
stfle 4095(%r15)
#CHECK: stcy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x72] #CHECK: stcy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x72]
#CHECK: stcy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x72] #CHECK: stcy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x72]
#CHECK: stcy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x72] #CHECK: stcy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x72]
#CHECK: stcy %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x72] #CHECK: stcy %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x72]
#CHECK: stcy %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x72] #CHECK: stcy %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x72]
#CHECK: stcy %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x72] #CHECK: stcy %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x72]
#CHECK: stcy %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x72] #CHECK: stcy %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x72]
#CHECK: stcy %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x72] #CHECK: stcy %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x72]
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