[X86] Add intrinsic support for clac, stac, lgdt and sgdt

[mkuper]

Summary

These intrinsics are not documented by Intel, but are required for MS compatibility (MSVC does document them).
(LLVM part, Clang part posted separately)

[rnk]

lib/Target/X86/X86InstrSystem.td

394

Why should these change to ins? lgdt goes from memory into the chip and sgdt goes from the chip out to memory, right?

[majnemer]

Are these intrinsics supposed to be compiler barriers? Seems like bad stuff could happen if we speculated or sunk around them.

[rnk]

In D12277#231179, @majnemer wrote:

Are these intrinsics supposed to be compiler barriers? Seems like bad stuff could happen if we speculated or sunk around them.

They have no constraints, which means they are equivalent to a normal external function call. Isn't that enough of a barrier? I think most users (kernels, hypervisors) are fine with LLVM reordering identified object memory accesses across such a barrier.

[mkuper]

I don't think we can do better than a readwrite function call, really.

A readwrite function call ought to be a barrier to just about anything that reorders memory accesses, and if it's not enough - I don't think we have a stronger one available in the IR.
A volatile asm block should probably be equivalent, right?

lib/Target/X86/X86InstrSystem.td

394

I may be deeply confused, but I've always been under the impression memory operands should always go into the "ins" - regardless of whether the instruction is storing or loading through the pointer. The pointer itself is always an input to the instruction, never an output of it.

In practice, having it in as an "out" breaks pattern-matching since tablegen expects the input pattern to refer to instruction inputs, not outputs.

include/llvm/IR/IntrinsicsX86.td

def int_x86_fxrstor64 : GCCBuiltin<"__builtin_ia32_fxrstor64">,
               Intrinsic<[], [llvm_ptr_ty], []>;
   def int_x86_fxsave : GCCBuiltin<"__builtin_ia32_fxsave">,
               Intrinsic<[], [llvm_ptr_ty], []>;
   def int_x86_fxsave64 : GCCBuiltin<"__builtin_ia32_fxsave64">,
               Intrinsic<[], [llvm_ptr_ty], []>;
 }
 
 //===----------------------------------------------------------------------===//
+// SMAP
+let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
+  def int_x86_clac : GCCBuiltin<"__builtin_ia32_clac">,
+              Intrinsic<[], [], []>;
+  def int_x86_stac : GCCBuiltin<"__builtin_ia32_stac">,
+              Intrinsic<[], [], []>;
+}
+
+//===----------------------------------------------------------------------===//
+// LGDT, SGDT
+let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
+  def int_x86_lgdt : GCCBuiltin<"__builtin_ia32_lgdt">,
+              Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_x86_sgdt : GCCBuiltin<"__builtin_ia32_sgdt">,
+              Intrinsic<[], [llvm_ptr_ty], []>;
+}
+
+//===----------------------------------------------------------------------===//
 // Half float conversion
 
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_vcvtph2ps_128 : GCCBuiltin<"__builtin_ia32_vcvtph2ps">,
               Intrinsic<[llvm_v4f32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
   def int_x86_vcvtph2ps_256 : GCCBuiltin<"__builtin_ia32_vcvtph2ps256">,
               Intrinsic<[llvm_v8f32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
   def int_x86_vcvtps2ph_128 : GCCBuiltin<"__builtin_ia32_vcvtps2ph">,

lib/Target/X86/X86InstrSystem.td

 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
               "verw\t$seg", [], IIC_VERW_REG>, TB;
 } // SchedRW
 
 //===----------------------------------------------------------------------===//
 // Descriptor-table support instructions
 
 let SchedRW = [WriteSystem] in {
-def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
+def SGDT16m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
               "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
-def SGDT32m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
-              "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>;
-def SGDT64m : I<0x01, MRM0m, (outs opaque80mem:$dst), (ins),
-              "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
-def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
+def SGDT32m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
+              "sgdt{l}\t$dst", [(int_x86_sgdt addr:$dst)], IIC_SGDT>, OpSize32, TB,
+              Requires <[Not64BitMode]>;
+def SGDT64m : I<0x01, MRM0m, (outs), (ins opaque80mem:$dst),
+              "sgdt{q}\t$dst", [(int_x86_sgdt addr:$dst)], IIC_SGDT>, TB,
+              Requires <[In64BitMode]>;
+def SIDT16m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
               "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
-def SIDT32m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
-              "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
-def SIDT64m : I<0x01, MRM1m, (outs opaque80mem:$dst), (ins),
-              "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
+def SIDT32m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
+              "sidt{l}\t$dst", [], IIC_SIDT>, OpSize32, TB, Requires <[Not64BitMode]>;
+def SIDT64m : I<0x01, MRM1m, (outs), (ins opaque80mem:$dst),
+              "sidt{q}\t$dst", [], IIC_SIDT>, TB, Requires <[In64BitMode]>;
 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
                 "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16;
 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
                 "sldt{w}\t$dst", [], IIC_SLDT>, TB;
 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
                 "sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB;
 
 // LLDT is not interpreted specially in 64-bit mode because there is no sign
 //   extension.
 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
                  "sldt{q}\t$dst", [], IIC_SLDT>, TB;
 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
                  "sldt{q}\t$dst", [], IIC_SLDT>, TB;
 
 def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
               "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
 def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
-              "lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>;
+              "lgdt{l}\t$src", [(int_x86_lgdt addr:$src)], IIC_LGDT>, OpSize32, TB,
+              Requires<[Not64BitMode]>;
 def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
-              "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
+              "lgdt{q}\t$src", [(int_x86_lgdt addr:$src)], IIC_LGDT>, TB,
+              Requires<[In64BitMode]>;
 def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
               "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
 def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
               "lidt{l}\t$src", [], IIC_LIDT>, OpSize32, TB, Requires<[Not64BitMode]>;
 def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
               "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
                 "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
                 Requires<[Not64BitMode]>;
 def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
                 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
                 Requires<[In64BitMode]>;
 
 //===----------------------------------------------------------------------===//
 // SMAP Instruction
 let Defs = [EFLAGS] in {
-  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
-  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
+  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", [(int_x86_clac)]>, TB;
+  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", [(int_x86_stac)]>, TB;
 }
 
 //===----------------------------------------------------------------------===//
 // SMX Instruction
 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
   def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, TB;
 }

test/CodeGen/X86/system-intrinsics.ll

 
 define void @test_fxrstor(i8* %ptr) {
 ; CHECK-LABEL: test_fxrstor
 ; CHECK: fxrstor
   call void @llvm.x86.fxrstor(i8* %ptr)
   ret void;
 }
 declare void @llvm.x86.fxrstor(i8*)
+
+define void @test_clac() {
+; CHECK-LABEL: test_clac
+; CHECK: clac
+  call void @llvm.x86.clac()
+  ret void;
+}
+declare void @llvm.x86.clac()
+
+define void @test_stac() {
+; CHECK-LABEL: test_stac
+; CHECK: stac
+  call void @llvm.x86.stac()
+  ret void;
+}
+declare void @llvm.x86.stac()
+
+define void @test_lgdt(i8* %ptr) {
+; CHECK-LABEL: test_lgdt
+; CHECK: lgdtl
+  call void @llvm.x86.lgdt(i8* %ptr)
+  ret void;
+}
+declare void @llvm.x86.lgdt(i8*)
+
+define void @test_sgdt(i8* %ptr) {
+; CHECK-LABEL: test_sgdt
+; CHECK: sgdtl
+  call void @llvm.x86.sgdt(i8* %ptr)
+  ret void;
+}
+declare void @llvm.x86.sgdt(i8*)