[mips][FastISel] Fix code generation for logical-ops by zero-extending constant operands.

[vkalintiris]

Summary

For logical operations we should materialize the zero-extension of its
constant operand. Previously, we would sign-extend the operand and
materialize that into a register.

The new constants in logopm.ll match the constants that are generated without
FastISel.

[dsanders]

Could you show me the test case that required this change? The test cases in the patch aren't affected by whether the constant is sign or zero extended.

I suspect that (like an earlier bug in our fast isel involving shifts IIRC) the bug may be that an IR instruction that consumes the result of these bitwise operations is failing to emit a necessary zero extend prior to using it. For example, a comparison might not be zero extending to GPR-width before using it in setlt or similar.

[vkalintiris]

Abandon this review request in favour of D11592. As I explain in the new revision, this patch would simply hide the real cause of the bug.

lib/Target/Mips/MipsFastISel.cpp

unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
   if (!ResultReg)
     return 0;
 
   unsigned RHSReg;
   if (!LHSReg)
     return 0;
 
   if (const auto *C = dyn_cast<ConstantInt>(RHS))
-    RHSReg = materializeInt(C, MVT::i32);
+    RHSReg = materialize32BitInt(C->getZExtValue(), &Mips::GPR32RegClass);
   else
     RHSReg = getRegForValue(RHS);
 
   if (!RHSReg)
     return 0;
 
   emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
   return ResultReg;

test/CodeGen/Mips/Fast-ISel/logopm.ll

entry:
   store i8 %and, i8* @uc, align 1, !tbaa !2
 ; CHECK-LABEL:  .ent    andUc1
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
 ; CHECK-DAG:    lw      $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
 ; CHECK-DAG:    lbu     $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
-; CHECK-DAG:    addiu   $[[CONST_Neg89:[0-9]+]], $zero, -89
-; CHECK-DAG:    and     $[[RES:[0-9]+]], $[[UC1]], $[[CONST_Neg89]]
+; CHECK-DAG:    addiu   $[[CONST_167:[0-9]+]], $zero, 167
+; CHECK-DAG:    and     $[[RES:[0-9]+]], $[[UC1]], $[[CONST_167]]
 ; CHECK:        sb      $[[RES]], 0($[[UC_ADDR]])
 ; CHECK:        .end    andUc1
   ret void
 }
 
 ; Function Attrs: noinline nounwind
 define void @orUc() #0 {
 entry:
entry:
   store i8 %or, i8* @uc, align 1, !tbaa !2
 ; CHECK-LABEL:  .ent    orUc1
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
 ; CHECK-DAG:    lw      $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
 ; CHECK-DAG:    lbu     $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
-; CHECK-DAG:    addiu   $[[CONST_neg18:[0-9]+]], $zero, -18
-; CHECK-DAG:    or      $[[RES:[0-9]+]], $[[UC1]], $[[CONST_neg18]]
+; CHECK-DAG:    addiu   $[[CONST_238:[0-9]+]], $zero, 238
+; CHECK-DAG:    or      $[[RES:[0-9]+]], $[[UC1]], $[[CONST_238]]
 ; CHECK:        sb      $[[RES]], 0($[[UC_ADDR]])
 ; CHECK:        .end    orUc1
   ret void
 }
 
 ; Function Attrs: noinline nounwind
 define void @xorUc() #0 {
 entry:
entry:
   store i16 %and, i16* @us, align 2, !tbaa !5
 ; CHECK-LABEL:  .ent    andUs1
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
 ; CHECK-DAG:    lw      $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
 ; CHECK-DAG:    lhu     $[[US1:[0-9]+]], 0($[[US1_ADDR]])
-; CHECK-DAG:    addiu   $[[CONST_Neg4185:[0-9]+]], $zero, -4185
-; CHECK-DAG:    and     $[[RES:[0-9]+]], $[[US1]], $[[CONST_Neg4185]]
+; CHECK-DAG:    ori     $[[CONST_61351:[0-9]+]], $zero, 61351
+; CHECK-DAG:    and     $[[RES:[0-9]+]], $[[US1]], $[[CONST_61351]]
 ; CHECK:        sh      $[[RES]], 0($[[US_ADDR]])
 ; CHECK:        .end    andUs1
   ret void
 }
 
 ; Function Attrs: noinline nounwind
 define void @orUs() #0 {
 entry:
entry:
   store i16 %or, i16* @us, align 2, !tbaa !5
 ; CHECK-LABEL:  .ent    orUs1
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
 ; CHECK-DAG:    lw      $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
 ; CHECK-DAG:    lhu     $[[US1:[0-9]+]], 0($[[US1_ADDR]])
-; CHECK-DAG:    addiu   $[[CONST_neg4591:[0-9]+]], $zero, -4591
-; CHECK-DAG:    or      $[[RES:[0-9]+]], $[[US1]], $[[CONST_neg4591]]
+; CHECK-DAG:    ori     $[[CONST_60945:[0-9]+]], $zero, 60945
+; CHECK-DAG:    or      $[[RES:[0-9]+]], $[[US1]], $[[CONST_60945]]
 ; CHECK:        sh      $[[RES]], 0($[[US_ADDR]])
 ; CHECK:        .end    orUs1
   ret void
 }
 
 ; Function Attrs: noinline nounwind
 define void @xorUs() #0 {
 entry:
entry:
   store i16 %xor, i16* @us, align 2, !tbaa !5
 ; CHECK-LABEL:  .ent    xorUs1
 ; CHECK:        lui     $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
 ; CHECK:        addiu   $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
 ; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
 ; CHECK-DAG:    lw      $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
 ; CHECK-DAG:    lw      $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
 ; CHECK-DAG:    lhu     $[[US1:[0-9]+]], 0($[[US1_ADDR]])
-; CHECK-DAG:    addiu   $[[CONST_Neg5512:[0-9]+]], $zero, -5512
-; CHECK-DAG:    xor     $[[RES:[0-9]+]], $[[US1]], $[[CONST_Neg5512]]
+; CHECK-DAG:    ori     $[[CONST_60024:[0-9]+]], $zero, 60024
+; CHECK-DAG:    xor     $[[RES:[0-9]+]], $[[US1]], $[[CONST_60024]]
 ; CHECK:        sh      $[[RES]], 0($[[US_ADDR]])
 ; CHECK:        .end    xorUs1
   ret void
 }
 
 attributes #0 = { noinline nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #2 = { nounwind }