[ARM][test] Add new tests for (mul (add r, c0), c1)

llvm/test/CodeGen/ARM/addimm-mulimm.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv6-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,CHECKV6
+; RUN: llc -mtriple=armv7a-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,CHECKV7
+
+define i32 @fold_addimm_mulimm_a(i32 %a) {
+; CHECK-LABEL: fold_addimm_mulimm_a:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    mov r1, #11
+; CHECK-NEXT:    mul r0, r0, r1
+; CHECK-NEXT:    add r0, r0, #209
+; CHECK-NEXT:    bx lr
+  %b = add i32 %a, 19
+  %c = mul i32 %b, 11
+  ret i32 %c
+}
+
+define i32 @fold_addimm_mulimm_b(i32 %a) {
+; CHECK-LABEL: fold_addimm_mulimm_b:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    mov r1, #11
+; CHECK-NEXT:    mul r0, r0, r1
+; CHECK-NEXT:    sub r0, r0, #209
+; CHECK-NEXT:    bx lr
+  %b = add i32 %a, -19
+  %c = mul i32 %b, 11
+  ret i32 %c
+}
+
+define i32 @fold_addimm_mulimm_c(i32 %a) {
+; CHECKV6-LABEL: fold_addimm_mulimm_c:
+; CHECKV6:       @ %bb.0:
+; CHECKV6-NEXT:    mov r1, #87
+; CHECKV6-NEXT:    mov r2, #19
+; CHECKV6-NEXT:    orr r1, r1, #5632
+; CHECKV6-NEXT:    mla r0, r0, r2, r1
+; CHECKV6-NEXT:    bx lr
+;
+; CHECKV7-LABEL: fold_addimm_mulimm_c:
+; CHECKV7:       @ %bb.0:
+; CHECKV7-NEXT:    movw r1, #5719
+; CHECKV7-NEXT:    mov r2, #19
+; CHECKV7-NEXT:    mla r0, r0, r2, r1
+; CHECKV7-NEXT:    bx lr
+  %b = add i32 %a, 301
+  %c = mul i32 %b, 19
+  ret i32 %c
+}
+
+define i32 @fold_addimm_mulimm_d(i32 %a) {
+; CHECKV6-LABEL: fold_addimm_mulimm_d:
+; CHECKV6:       @ %bb.0:
+; CHECKV6-NEXT:    mvn r1, #86
+; CHECKV6-NEXT:    mov r2, #19
+; CHECKV6-NEXT:    sub r1, r1, #5632
+; CHECKV6-NEXT:    mla r0, r0, r2, r1
+; CHECKV6-NEXT:    bx lr
+;
+; CHECKV7-LABEL: fold_addimm_mulimm_d:
+; CHECKV7:       @ %bb.0:
+; CHECKV7-NEXT:    mov r1, #19
+; CHECKV7-NEXT:    mul r0, r0, r1
+; CHECKV7-NEXT:    movw r1, #5719
+; CHECKV7-NEXT:    sub r0, r0, r1
+; CHECKV7-NEXT:    bx lr
+  %b = add i32 %a, -301
+  %c = mul i32 %b, 19
+  ret i32 %c
+}
+
+define i32 @fold_addimm_mulimm_g(i32 %a) {
+; CHECKV6-LABEL: fold_addimm_mulimm_g:
+; CHECKV6:       @ %bb.0:
+; CHECKV6-NEXT:    mov r1, #15
+; CHECKV6-NEXT:    mov r2, #253
+; CHECKV6-NEXT:    orr r1, r1, #63488
+; CHECKV6-NEXT:    mla r0, r0, r2, r1
+; CHECKV6-NEXT:    bx lr
+;
+; CHECKV7-LABEL: fold_addimm_mulimm_g:
+; CHECKV7:       @ %bb.0:
+; CHECKV7-NEXT:    movw r1, #63503
+; CHECKV7-NEXT:    mov r2, #253
+; CHECKV7-NEXT:    mla r0, r0, r2, r1
+; CHECKV7-NEXT:    bx lr
+  %b = add i32 %a, 251
+  %c = mul i32 %b, 253
+  ret i32 %c
+}
+
+define i32 @fold_addimm_mulimm_h(i32 %a) {
+; CHECKV6-LABEL: fold_addimm_mulimm_h:
+; CHECKV6:       @ %bb.0:
+; CHECKV6-NEXT:    mvn r1, #14
+; CHECKV6-NEXT:    mov r2, #253
+; CHECKV6-NEXT:    sub r1, r1, #63488
+; CHECKV6-NEXT:    mla r0, r0, r2, r1
+; CHECKV6-NEXT:    bx lr
+;
+; CHECKV7-LABEL: fold_addimm_mulimm_h:
+; CHECKV7:       @ %bb.0:
+; CHECKV7-NEXT:    mov r1, #253
+; CHECKV7-NEXT:    mul r0, r0, r1
+; CHECKV7-NEXT:    movw r1, #63503
+; CHECKV7-NEXT:    sub r0, r0, r1
+; CHECKV7-NEXT:    bx lr
+  %b = add i32 %a, -251
+  %c = mul i32 %b, 253
+  ret i32 %c
+}
+
+define i32 @fold_addimm_mulimm_i(i32 %a) {
+; CHECKV6-LABEL: fold_addimm_mulimm_i:
+; CHECKV6:       @ %bb.0:
+; CHECKV6-NEXT:    mov r2, #97
+; CHECKV6-NEXT:    ldr r1, .LCPI6_0
+; CHECKV6-NEXT:    orr r2, r2, #256
+; CHECKV6-NEXT:    mla r0, r0, r2, r1
+; CHECKV6-NEXT:    bx lr
+; CHECKV6-NEXT:    .p2align 2
+; CHECKV6-NEXT:  @ %bb.1:
+; CHECKV6-NEXT:  .LCPI6_0:
+; CHECKV6-NEXT:    .long 88603 @ 0x15a1b
+;
+; CHECKV7-LABEL: fold_addimm_mulimm_i:
+; CHECKV7:       @ %bb.0:
+; CHECKV7-NEXT:    movw r1, #23067
+; CHECKV7-NEXT:    movw r2, #353
+; CHECKV7-NEXT:    movt r1, #1
+; CHECKV7-NEXT:    mla r0, r0, r2, r1
+; CHECKV7-NEXT:    bx lr
+  %b = add i32 %a, 251
+  %c = mul i32 %b, 353
+  ret i32 %c
+}
+
+define i32 @fold_addimm_mulimm_j(i32 %a) {
+; CHECKV6-LABEL: fold_addimm_mulimm_j:
+; CHECKV6:       @ %bb.0:
+; CHECKV6-NEXT:    mov r2, #97
+; CHECKV6-NEXT:    ldr r1, .LCPI7_0
+; CHECKV6-NEXT:    orr r2, r2, #256
+; CHECKV6-NEXT:    mla r0, r0, r2, r1
+; CHECKV6-NEXT:    bx lr
+; CHECKV6-NEXT:    .p2align 2
+; CHECKV6-NEXT:  @ %bb.1:
+; CHECKV6-NEXT:  .LCPI7_0:
+; CHECKV6-NEXT:    .long 4294878693 @ 0xfffea5e5
+;
+; CHECKV7-LABEL: fold_addimm_mulimm_j:
+; CHECKV7:       @ %bb.0:
+; CHECKV7-NEXT:    movw r1, #42469
+; CHECKV7-NEXT:    movw r2, #353
+; CHECKV7-NEXT:    movt r1, #65534
+; CHECKV7-NEXT:    mla r0, r0, r2, r1
+; CHECKV7-NEXT:    bx lr
+  %b = add i32 %a, -251
+  %c = mul i32 %b, 353
+  ret i32 %c
+}