Fix for bug 23996 - Fix incorrect/inefficient pushw encodings for x86-64 targets

[DavidKreitzer]

Summary

The main problem that this patch fixes is that the "pushw imm8" instruction form is not currently supported for x86_64 targets.

In the process of fixing that bug I did some minor cleanup:

(1) Re-grouped the "push imm" opcodes so that the pushw (supported on both 32- and 64-bit), pushl (32-bit only), and pushq (64-bit only) opcodes are together.

(2) Consolidated PUSHi16 and PUSH64i16. These two opcodes currently do the same thing, but for 32-bit only and 64-bit only, respectively. I enabled PUSHi16 for 64-bit, at which point PUSH64i16 became redundant. Thanks to Michael Kuperstein for noticing this opportunity.

(3) Retooled the relax-arith.s test to use llvm-objdump -d instead of llvm-readobj.

[• rafael]

LGTM, but please do commit as two patches, where the first one just
converts the tests to use llvm-objdump.

[• rafael]

Change to use llvm-objdump LGTM. Please do that first so that the rest
of the patch is easier to read.

Checking the patch itself now.

lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

static unsigned getRelaxedOpcodeArith(unsigned Op) {
   case X86::CMP32mi8: return X86::CMP32mi;
   case X86::CMP64ri8: return X86::CMP64ri32;
   case X86::CMP64mi8: return X86::CMP64mi32;
 
     // PUSH
   case X86::PUSH32i8:  return X86::PUSHi32;
   case X86::PUSH16i8:  return X86::PUSHi16;
   case X86::PUSH64i8:  return X86::PUSH64i32;
-  case X86::PUSH64i16: return X86::PUSH64i32;
   }
 }
 
 static unsigned getRelaxedOpcode(unsigned Op) {
   unsigned R = getRelaxedOpcodeArith(Op);
   if (R != Op)
     return R;
   return getRelaxedOpcodeBranch(Op);

lib/Target/X86/X86InstrInfo.td

 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
                  IIC_PUSH_MEM>, OpSize16;
 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
                  IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
                  IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
 
 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
-                   "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
-                   Requires<[Not64BitMode]>;
+                   "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
+def PUSHi16  : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
+                   "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
+
 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
                    "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
                    Requires<[Not64BitMode]>;
-def PUSHi16  : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
-                   "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
-                   Requires<[Not64BitMode]>;
 def PUSHi32  : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
                    "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
                    Requires<[Not64BitMode]>;
 } // mayStore, SchedRW
 }
 
 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
     SchedRW = [WriteLoad] in {
def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
                  IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>;
 } // mayStore, SchedRW
 }
 
 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
     SchedRW = [WriteStore] in {
 def PUSH64i8   : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
                     "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
-def PUSH64i16  : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
-                    "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
-                    Requires<[In64BitMode]>;
 def PUSH64i32  : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
                     "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
                     Requires<[In64BitMode]>;
 }
 
 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
 def POPF64   : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
                OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;

test/MC/ELF/relax-arith.s

-// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck  %s
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-objdump -d - | FileCheck  %s
 
 // Test that we correctly relax these instructions into versions that use
 // 16 or 32 bit immediate values.
 
 bar:
-// CHECK:      Name: imul
-// CHECK:      SectionData (
-// CHECK-NEXT:   0000: 6669DB00 0066691C 25000000 00000069
-// CHECK-NEXT:   0010: DB000000 00691C25 00000000 00000000
-// CHECK-NEXT:   0020: 4869DB00 00000048 691C2500 00000000
-// CHECK-NEXT:   0030: 000000
-// CHECK-NEXT: )
-        .section imul
+// CHECK:      Disassembly of section imul:
+// CHECK-NEXT: imul:
+// CHECK-NEXT:   0: 66 69 db 00 00                       imulw $0, %bx, %bx
+// CHECK-NEXT:   5: 66 69 1c 25 00 00 00 00 00 00        imulw $0, 0, %bx
+// CHECK-NEXT:   f: 69 db 00 00 00 00                    imull $0, %ebx, %ebx
+// CHECK-NEXT:  15: 69 1c 25 00 00 00 00 00 00 00 00     imull $0, 0, %ebx
+// CHECK-NEXT:  20: 48 69 db 00 00 00 00                 imulq $0, %rbx, %rbx
+// CHECK-NEXT:  27: 48 69 1c 25 00 00 00 00 00 00 00 00  imulq $0, 0, %rbx
+        .section imul,"x"
         imul $foo, %bx,  %bx
         imul $foo, bar,  %bx
         imul $foo, %ebx, %ebx
         imul $foo, bar,  %ebx
         imul $foo, %rbx, %rbx
         imul $foo, bar,  %rbx
 
-
-// CHECK:      Name: and
-// CHECK:      SectionData (
-// CHECK-NEXT:   0000: 6681E300 00668124 25000000 00000081
-// CHECK-NEXT:   0010: E3000000 00812425 00000000 00000000
-// CHECK-NEXT:   0020: 4881E300 00000048 81242500 00000000
-// CHECK-NEXT:   0030: 000000
-// CHECK-NEXT: )
-        .section and
+// CHECK:      Disassembly of section and:
+// CHECK-NEXT: and:
+// CHECK-NEXT:   0: 66 81 e3 00 00                       andw $0, %bx
+// CHECK-NEXT:   5: 66 81 24 25 00 00 00 00 00 00        andw $0, 0
+// CHECK-NEXT:   f: 81 e3 00 00 00 00                    andl $0, %ebx
+// CHECK-NEXT:  15: 81 24 25 00 00 00 00 00 00 00 00     andl $0, 0
+// CHECK-NEXT:  20: 48 81 e3 00 00 00 00                 andq $0, %rbx
+// CHECK-NEXT:  27: 48 81 24 25 00 00 00 00 00 00 00 00  andq $0, 0
+        .section and,"x"
         and  $foo, %bx
         andw $foo, bar
         and  $foo, %ebx
         andl $foo, bar
         and  $foo, %rbx
         andq $foo, bar
 
-// CHECK:      Name: or
-// CHECK:      SectionData (
-// CHECK-NEXT:   0000: 6681CB00 0066810C 25000000 00000081
-// CHECK-NEXT:   0010: CB000000 00810C25 00000000 00000000
-// CHECK-NEXT:   0020: 4881CB00 00000048 810C2500 00000000
-// CHECK-NEXT:   0030: 000000
-// CHECK-NEXT: )
-        .section or
+// CHECK:      Disassembly of section or:
+// CHECK-NEXT: or:
+// CHECK-NEXT:   0: 66 81 cb 00 00                       orw $0, %bx
+// CHECK-NEXT:   5: 66 81 0c 25 00 00 00 00 00 00        orw $0, 0
+// CHECK-NEXT:   f: 81 cb 00 00 00 00                    orl $0, %ebx
+// CHECK-NEXT:  15: 81 0c 25 00 00 00 00 00 00 00 00     orl $0, 0
+// CHECK-NEXT:  20: 48 81 cb 00 00 00 00                 orq $0, %rbx
+// CHECK-NEXT:  27: 48 81 0c 25 00 00 00 00 00 00 00 00  orq $0, 0
+        .section or,"x"
         or  $foo, %bx
         orw $foo, bar
         or  $foo, %ebx
         orl $foo, bar
         or  $foo, %rbx
         orq $foo, bar
 
-// CHECK:      Name: xor
-// CHECK:      SectionData (
-// CHECK-NEXT:   0000: 6681F300 00668134 25000000 00000081
-// CHECK-NEXT:   0010: F3000000 00813425 00000000 00000000
-// CHECK-NEXT:   0020: 4881F300 00000048 81342500 00000000
-// CHECK-NEXT:   0030: 000000
-// CHECK-NEXT: )
-        .section xor
+// CHECK:      Disassembly of section xor:
+// CHECK-NEXT: xor:
+// CHECK-NEXT:   0: 66 81 f3 00 00                       xorw $0, %bx
+// CHECK-NEXT:   5: 66 81 34 25 00 00 00 00 00 00        xorw $0, 0
+// CHECK-NEXT:   f: 81 f3 00 00 00 00                    xorl $0, %ebx
+// CHECK-NEXT:  15: 81 34 25 00 00 00 00 00 00 00 00     xorl $0, 0
+// CHECK-NEXT:  20: 48 81 f3 00 00 00 00                 xorq $0, %rbx
+// CHECK-NEXT:  27: 48 81 34 25 00 00 00 00 00 00 00 00  xorq $0, 0
+        .section xor,"x"
         xor  $foo, %bx
         xorw $foo, bar
         xor  $foo, %ebx
         xorl $foo, bar
         xor  $foo, %rbx
         xorq $foo, bar
 
-// CHECK:      Name: add
-// CHECK:      SectionData (
-// CHECK-NEXT:   0000: 6681C300 00668104 25000000 00000081
-// CHECK-NEXT:   0010: C3000000 00810425 00000000 00000000
-// CHECK-NEXT:   0020: 4881C300 00000048 81042500 00000000
-// CHECK-NEXT:   0030: 000000
-// CHECK-NEXT: )
-        .section add
+// CHECK:      Disassembly of section add:
+// CHECK-NEXT: add:
+// CHECK-NEXT:   0: 66 81 c3 00 00                       addw $0, %bx
+// CHECK-NEXT:   5: 66 81 04 25 00 00 00 00 00 00        addw $0, 0
+// CHECK-NEXT:   f: 81 c3 00 00 00 00                    addl $0, %ebx
+// CHECK-NEXT:  15: 81 04 25 00 00 00 00 00 00 00 00     addl $0, 0
+// CHECK-NEXT:  20: 48 81 c3 00 00 00 00                 addq $0, %rbx
+// CHECK-NEXT:  27: 48 81 04 25 00 00 00 00 00 00 00 00  addq $0, 0
+        .section add,"x"
         add  $foo, %bx
         addw $foo, bar
         add  $foo, %ebx
         addl $foo, bar
         add  $foo, %rbx
         addq $foo, bar
 
-// CHECK:      Name: sub
-// CHECK:      SectionData (
-// CHECK-NEXT:   000: 6681EB00 0066812C 25000000 00000081
-// CHECK-NEXT:   010: EB000000 00812C25 00000000 00000000
-// CHECK-NEXT:   020: 4881EB00 00000048 812C2500 00000000
-// CHECK-NEXT:   030: 000000
-// CHECK-NEXT: )
-        .section sub
+// CHECK:      Disassembly of section sub:
+// CHECK-NEXT: sub:
+// CHECK-NEXT:   0: 66 81 eb 00 00                       subw $0, %bx
+// CHECK-NEXT:   5: 66 81 2c 25 00 00 00 00 00 00        subw $0, 0
+// CHECK-NEXT:   f: 81 eb 00 00 00 00                    subl $0, %ebx
+// CHECK-NEXT:  15: 81 2c 25 00 00 00 00 00 00 00 00     subl $0, 0
+// CHECK-NEXT:  20: 48 81 eb 00 00 00 00                 subq $0, %rbx
+// CHECK-NEXT:  27: 48 81 2c 25 00 00 00 00 00 00 00 00  subq $0, 0
+        .section sub,"x"
         sub  $foo, %bx
         subw $foo, bar
         sub  $foo, %ebx
         subl $foo, bar
         sub  $foo, %rbx
         subq $foo, bar
 
-// CHECK:      Name: cmp
-// CHECK:      SectionData (
-// CHECK-NEXT:   0000: 6681FB00 0066813C 25000000 00000081
-// CHECK-NEXT:   0010: FB000000 00813C25 00000000 00000000
-// CHECK-NEXT:   0020: 4881FB00 00000048 813C2500 00000000
-// CHECK-NEXT:   0030: 000000
-// CHECK-NEXT: )
-        .section cmp
+// CHECK:      Disassembly of section cmp:
+// CHECK-NEXT: cmp:
+// CHECK-NEXT:   0: 66 81 fb 00 00                       cmpw $0, %bx
+// CHECK-NEXT:   5: 66 81 3c 25 00 00 00 00 00 00        cmpw $0, 0
+// CHECK-NEXT:   f: 81 fb 00 00 00 00                    cmpl $0, %ebx
+// CHECK-NEXT:  15: 81 3c 25 00 00 00 00 00 00 00 00     cmpl $0, 0
+// CHECK-NEXT:  20: 48 81 fb 00 00 00 00                 cmpq $0, %rbx
+// CHECK-NEXT:  27: 48 81 3c 25 00 00 00 00 00 00 00 00  cmpq $0, 0
+        .section cmp,"x"
         cmp  $foo, %bx
         cmpw $foo, bar
         cmp  $foo, %ebx
         cmpl $foo, bar
         cmp  $foo, %rbx
         cmpq $foo, bar
+
+// CHECK:      Disassembly of section push:
+// CHECK-NEXT: push:
+// CHECK-NEXT:   0: 66 68 00 00                          pushw $0
+// CHECK-NEXT:   4: 68 00 00 00 00                       pushq $0
+        .section push,"x"
+        pushw $foo
+        push  $foo

test/MC/ELF/relax-arith2.s

 // CHECK-NEXT:  1c: 48 83 3c 25 00 00 00 00 2a    cmpq $42, 0
         .section cmp,"x"
         cmp  $-128, %bx
         cmpw $127, bar
         cmp  $0, %ebx
         cmpl $1, bar
         cmp  $-1, %rbx
         cmpq $42, bar
+
+// CHECK:      Disassembly of section push:
+// CHECK-NEXT: push:
+// CHECK-NEXT:   0: 66 6a 80                      pushw $-128
+// CHECK-NEXT:   3: 66 6a 7f                      pushw $127
+// CHECK-NEXT:   6: 6a 80                         pushq $-128
+// CHECK-NEXT:   8: 6a 7f                         pushq $127
+        .section push,"x"
+        pushw $-128
+        pushw $127
+        push  $-128
+        push  $127

test/MC/ELF/relax-arith4.s

+// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | llvm-objdump -d - | FileCheck  %s
+
+// Test for proper instruction relaxation behavior for the push $imm
+// instruction forms. This is the 32-bit version of the push $imm tests from
+// relax-arith.s and relax-arith2.s.
+
+// CHECK:      Disassembly of section push8:
+// CHECK-NEXT: push8:
+// CHECK-NEXT:   0: 66 6a 80                      pushw $-128
+// CHECK-NEXT:   3: 66 6a 7f                      pushw $127
+// CHECK-NEXT:   6: 6a 80                         pushl $-128
+// CHECK-NEXT:   8: 6a 7f                         pushl $127
+        .section push8,"x"
+        pushw $-128
+        pushw $127
+        push  $-128
+        push  $127
+
+// CHECK:      Disassembly of section push32:
+// CHECK-NEXT: push32:
+// CHECK-NEXT:   0: 66 68 00 00                   pushw $0
+// CHECK-NEXT:   4: 68 00 00 00 00                pushl $0
+        .section push32,"x"
+        pushw $foo
+        push  $foo