AMDGPU/SI: There are no implicit kernel args in the amdhsa ABI

[arsenm]

LGTM

lib/Target/AMDGPU/AMDGPUSubtarget.h

unsigned getMaxWavesPerCU() const {
 
     // FIXME: Not sure what this is for other subtagets.
     llvm_unreachable("do not know max waves per CU for this subtarget.");
   }
 
   bool enableSubRegLiveness() const override {
     return true;
   }
+
+  /// \brief Returns the offset in bytes from the start of the input buffer
+  ///        of the first explicit kernel argument.
+  unsigned getExplicitKernelArgOffset() const {
+    return isAmdHsaOS() ? 0 : 36;
+  }
+
 };
 
 } // End namespace llvm
 
 #endif

lib/Target/AMDGPU/SIISelLowering.cpp

for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
     }
 
     CCValAssign &VA = ArgLocs[ArgIdx++];
     MVT VT = VA.getLocVT();
 
     if (VA.isMemLoc()) {
       VT = Ins[i].VT;
       EVT MemVT = Splits[i].VT;
-      const unsigned Offset = 36 + VA.getLocMemOffset();
+      const unsigned Offset = Subtarget->getExplicitKernelArgOffset() +
+                              VA.getLocMemOffset();
       // The first 36 bytes of the input buffer contains information about
       // thread group and global sizes.
       SDValue Arg = LowerParameter(DAG, VT, MemVT,  DL, DAG.getRoot(),
                                    Offset, Ins[i].Flags.isSExt());
 
       const PointerType *ParamTy =
         dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
       if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&

test/CodeGen/AMDGPU/hsa.ll

 ; HSA: .hsa_code_object_version 1,0
 ; HSA: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
 
 ; HSA: {{^}}simple:
 ; HSA: .section        .hsa.version
 ; HSA-NEXT: .ascii  "HSA Code Unit:0.0:AMD:0.1:GFX8.1:0"
 ; Test that the amd_kernel_code_t object is emitted
 ; HSA: .asciz
+; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[0:1], 0x0
 ; Make sure we are setting the ATC bit:
 ; HSA: s_mov_b32 s[[HI:[0-9]]], 0x100f000
 ; HSA: buffer_store_dword v{{[0-9]+}}, s[0:[[HI]]], 0
 
 define void @simple(i32 addrspace(1)* %out) {
 entry:
   store i32 0, i32 addrspace(1)* %out
   ret void
 }