[mips] MFC0, MTC0 changes, COP0 register class definition.

[sdardis]

Summary

Defined a new register class for coprocessor 0's registers.

The instruction definitions for DMTC0, DMFC0, MFC0 and MTC0 have been changed to reflect this.

[dsanders]

The change looks correct to me but the patch lacks appropriate test cases. Could you add them?

lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp

82–83 ↗

(On Diff #28022)

Tiny nit: Could you add a small comment that the FPU is COP1? This will make the ordering of the if-statements obvious.

[sdardis]

Tests for mfc0, mtc0, and double word variants in the disassembler.
Reginfo usage test for COP0.

Is there any else required?

Thanks.

[sdardis]

Apologies, last submission had a broken test.

[dsanders]

Thanks. The tests need expanding on a bit (mostly copy/paste into each ISA's test file) and the commit message needs improving (particularly the subject line) but after that it will LGTM. I'm aware you don't have commit access yet, so could you update the revision and I'll commit from there.

To elaborate on the tests that are needed: For the disassembler, the tests you've added need to be duplicated in each ISA's test (test/MC/Disassembler/Mips/$isa/valid-$isa.txt and test/MC/Disassembler/Mips/$isa/valid-$isa-el.txt for big/little endian respectively). I believe that mfc0/mtc0 also need to be included in the tests for the 64-bit ISA's since they are still valid instructions. The tests are laid out like this to make it easy to inspect the differences between the ISA's and manually check against documentation. These files should be sorted by opcode.

For the assembler, we also need to test the encoding is correct. The existing tests for this are in test/MC/Mips/*/valid.s (one for each ISA). These files are sorted alphabetically to make it easy to verify against the documentation and inspect the ISA differences using diff. Lastly, we also need to add to test/MC/Mips/$isa1/invalid-$isa2.s which tests that $isa1 rejects things that were valid for $isa2. In this case, we just need to update the existing test/MC/Mips/*/invalid-mips64.s to check that dmfc0/dmtc0 are rejected with the correct error message. If they are rejected but with the wrong error message then there are also invalid-*-xfail.txt tests that can be used.

lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp

84 ↗

(On Diff #28357)

Nit: LLVM uses '//' comments.

[sdardis]

Added tests, addressed nit.

[sdardis]

Apologies for spam attached wrong revision, this is the correct one.

[dsanders]

LGTM. I'm aware you don't have commit access yet so I'll commit this shortly.

I realize I said that disassembler tests are supposed to be sorted by opcode but it looks like they're sorted by mnemonic. You've made the correct change despite my mistake. Thanks.

[dsanders]

In the commit, I've fixed a couple issues that came up when running 'ninja check'.

• Some little endian disassembler tests failed because they had the same opcode as big endian. I've byte-swapped them.
• Two disassembler tests failed because their expectation was different for the same opcode as the other ISA's.

I also marked DMFC0 as being part of MIPS3 like the other DM[FT]C0's.

lib/Target/Mips/MipsAsmPrinter.h

bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
                                    const MachineInstr *MI);
 
   // Emit PseudoReturn, PseudoReturn64, PseudoIndirectBranch,
   // and PseudoIndirectBranch64 as a JR, JR_MM, JALR, or JALR64 as appropriate
   // for the target.
   void emitPseudoIndirectBranch(MCStreamer &OutStreamer,
                                 const MachineInstr *MI);
 
+  void emitERet(MCStreamer &OutStreamer,
+                                const MachineInstr *MI);
+
   // lowerOperand - Convert a MachineOperand into the equivalent MCOperand.
   bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp);
 
   /// MCP - Keep a pointer to constantpool entries of the current
   /// MachineFunction.
   const MachineConstantPool *MCP;
 
   /// InConstantPool - Maintain state when emitting a sequence of constant

lib/Target/Mips/MipsAsmPrinter.cpp

void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
   }
 
   lowerOperand(MI->getOperand(0), MCOp);
   TmpInst0.addOperand(MCOp);
 
   EmitToStreamer(OutStreamer, TmpInst0);
 }
 
+void MipsAsmPrinter::emitERet(MCStreamer &OutStreamer,
+                              const MachineInstr *MI) {
+  MCInst TmpInst0;
+  TmpInst0.setOpcode(Mips::ERET);
+  EmitToStreamer(OutStreamer, TmpInst0);
+
+}
+
 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   MipsTargetStreamer &TS = getTargetStreamer();
   TS.forbidModuleDirective();
 
   if (MI->isDebugValue()) {
     SmallString<128> Str;
     raw_svector_ostream OS(Str);
 
do {
     if (I->getOpcode() == Mips::PseudoReturn ||
         I->getOpcode() == Mips::PseudoReturn64 ||
         I->getOpcode() == Mips::PseudoIndirectBranch ||
         I->getOpcode() == Mips::PseudoIndirectBranch64) {
       emitPseudoIndirectBranch(*OutStreamer, &*I);
       continue;
     }
 
+    if (I->getOpcode() == Mips::ERet) {
+      emitERet(*OutStreamer, &*I);
+      continue;
+    }
+
     // The inMips16Mode() test is not permanent.
     // Some instructions are marked as pseudo right now which
     // would make the test fail for the wrong reason but
     // that will be fixed soon. We need this here because we are
     // removing another test for this situation downstream in the
     // callchain.
     //
     if (I->isPseudo() && !Subtarget->inMips16Mode()

lib/Target/Mips/MipsCallingConv.td

 
 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
                                    GP_64, (sequence "S%u_64", 7, 0))>;
 
 def CSR_Mips16RetHelper :
   CalleeSavedRegs<(add V0, V1, FP,
                    (sequence "A%u", 3, 0), (sequence "S%u", 7, 0),
                    (sequence "D%u", 15, 10))>;
+
+def CSR_Interrupt_32R6 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
+                                                      (sequence "S%u", 7, 0),
+                                                      (sequence "V%u", 1, 0),
+                                                      (sequence "T%u", 9, 0),
+                                                      RA, FP, GP, AT)>;
+
+def CSR_Interrupt_32 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
+                                                      (sequence "S%u", 7, 0),
+                                                      (sequence "V%u", 1, 0),
+                                                      (sequence "T%u", 9, 0),
+                                                      RA, FP, GP, AT, LO0, HI0)>;
+
+def CSR_Interrupt_64R6 :
+  CalleeSavedRegs<(add (sequence "A%u_64", 3, 0), (sequence "V%u_64", 1, 0),
+                   (sequence "S%u_64", 7, 0), (sequence "T%u_64", 9, 0),
+                   RA_64, FP_64, GP_64, AT_64)>;
+
+def CSR_Interrupt_64 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0),
+                                                     (sequence "S%u_64", 7, 0),
+                                                     (sequence "T%u_64", 9, 0),
+                                                     (sequence "V%u_64", 1, 0),
+                                                     RA_64, FP_64, GP_64,
+                                                     AT_64, LO0_64, HI0_64)>;

lib/Target/Mips/MipsISelLowering.h

enum NodeType : unsigned {
       CMovFP_F,
 
       // FP-to-int truncation node.
       TruncIntFP,
 
       // Return
       Ret,
 
+      // Exception Return
+      ERet,
+
+      // Software Exception Return.
       EH_RETURN,
 
       // Node used to extract integer from accumulator.
       MFHI,
       MFLO,
 
       // Node used to insert integers to accumulator.
       MTLOHI,
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                         LLVMContext &Context) const override;
 
     SDValue LowerReturn(SDValue Chain,
                         CallingConv::ID CallConv, bool isVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
                         const SmallVectorImpl<SDValue> &OutVals,
                         SDLoc dl, SelectionDAG &DAG) const override;
 
+    SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
+                                SDLoc DL, SelectionDAG &DAG) const;
+
     bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
 
     // Inline asm support
     ConstraintType
       getConstraintType(const std::string &Constraint) const override;
 
     /// Examine constraint string and operand type and determine a weight value.
     /// The operand object must already have been set up with the operand type.

lib/Target/Mips/MipsISelLowering.cpp

const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case MipsISD::FIRST_NUMBER:      break;
   case MipsISD::JmpLink:           return "MipsISD::JmpLink";
   case MipsISD::TailCall:          return "MipsISD::TailCall";
   case MipsISD::Hi:                return "MipsISD::Hi";
   case MipsISD::Lo:                return "MipsISD::Lo";
   case MipsISD::GPRel:             return "MipsISD::GPRel";
   case MipsISD::ThreadPointer:     return "MipsISD::ThreadPointer";
   case MipsISD::Ret:               return "MipsISD::Ret";
+  case MipsISD::ERet:              return "MipsISD::ERet";
   case MipsISD::EH_RETURN:         return "MipsISD::EH_RETURN";
   case MipsISD::FPBrcond:          return "MipsISD::FPBrcond";
   case MipsISD::FPCmp:             return "MipsISD::FPCmp";
   case MipsISD::CMovFP_T:          return "MipsISD::CMovFP_T";
   case MipsISD::CMovFP_F:          return "MipsISD::CMovFP_F";
   case MipsISD::TruncIntFP:        return "MipsISD::TruncIntFP";
   case MipsISD::MFHI:              return "MipsISD::MFHI";
   case MipsISD::MFLO:              return "MipsISD::MFLO";
MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
   if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) {
     if (Type == MVT::i32)
       return true;
   }
   return IsSigned;
 }
 
 SDValue
+MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
+                                         SDLoc DL, SelectionDAG &DAG) const {
+
+  MachineFunction&MF = DAG.getMachineFunction();
+  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
+
+  MipsFI->setISR();
+
+  return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
+}
+
+SDValue
 MipsTargetLowering::LowerReturn(SDValue Chain,
                                 CallingConv::ID CallConv, bool IsVarArg,
                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
                                 const SmallVectorImpl<SDValue> &OutVals,
                                 SDLoc DL, SelectionDAG &DAG) const {
   // CCValAssign - represent the assignment of
   // the return value to a location
   SmallVector<CCValAssign, 16> RVLocs;
MipsTargetLowering::LowerReturn(SDValue Chain,
   }
 
   RetOps[0] = Chain;  // Update chain.
 
   // Add the flag if we have it.
   if (Flag.getNode())
     RetOps.push_back(Flag);
 
-  // Return on Mips is always a "jr $ra"
+  // Return for interrupts overrides the normal return mechanism.
+  if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt"))
+    return LowerInterruptReturn(RetOps, DL, DAG);
+
+  // Standard Return on Mips is a "jr $ra"
   return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
 }
 
 //===----------------------------------------------------------------------===//
 //                           Mips Inline Assembly Support
 //===----------------------------------------------------------------------===//
 
 /// getConstraintType - Given a constraint letter, return the type of

lib/Target/Mips/MipsInstrInfo.td

 
 // Thread pointer
 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
 
 // Return
 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
                      [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
 
+def MipsERet : SDNode<"MipsISD::ERet", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
+
 // These are target-independent nodes, but have target-specific formats.
 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
                            [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
 def callseq_end   : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
                            [SDNPHasChain, SDNPSideEffect,
                             SDNPOptInGlue, SDNPOutGlue]>;
 
 // Nodes used to extract LO/HI registers.

 //===----------------------------------------------------------------------===//
 // Pseudo instructions
 //===----------------------------------------------------------------------===//
 
 // Return RA.
 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
 
+let isReturn=1, isTerminator=1, isBarrier=1, hasCtrlDep=1 in
+def ERet : PseudoSE<(outs), (ins), [(MipsERet)]>;
+
 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
                                   [(callseq_start timm:$amt)]>;
 def ADJCALLSTACKUP   : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                                   [(callseq_end timm:$amt1, timm:$amt2)]>;
 }
 
 let usesCustomInserter = 1 in {

lib/Target/Mips/MipsMachineFunction.h

 };
 
 /// MipsFunctionInfo - This class is derived from MachineFunction private
 /// Mips target-specific information for each MachineFunction.
 class MipsFunctionInfo : public MachineFunctionInfo {
 public:
   MipsFunctionInfo(MachineFunction &MF)
       : MF(MF), SRetReturnReg(0), GlobalBaseReg(0), Mips16SPAliasReg(0),
-        VarArgsFrameIndex(0), CallsEhReturn(false), SaveS2(false),
-        MoveF64ViaSpillFI(-1) {}
+        VarArgsFrameIndex(0), CallsEhReturn(false), ISR(false),
+        SaveS2(false), MoveF64ViaSpillFI(-1){}
 
   ~MipsFunctionInfo();
 
   unsigned getSRetReturnReg() const { return SRetReturnReg; }
   void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
 
   bool globalBaseRegSet() const;
   unsigned getGlobalBaseReg();
public:
 
   bool callsEhReturn() const { return CallsEhReturn; }
   void setCallsEhReturn() { CallsEhReturn = true; }
 
   void createEhDataRegsFI();
   int getEhDataRegFI(unsigned Reg) const { return EhDataRegFI[Reg]; }
   bool isEhDataRegFI(int FI) const;
 
+  // Function with the "interrupt" attribute require extra handling
+  // with prologue, epilogue and additional spill slots.
+  bool isISR() const { return ISR; }
+  void setISR() { ISR = true; }
+  void createISRRegFI();
+  int getISRRegFI(unsigned Reg) const { return ISRDataRegFI[Reg]; }
+  bool isISRRegFI(int FI) const;
+
   /// \brief Create a MachinePointerInfo that has a MipsCallEntr object
   /// representing a GOT entry for an external function.
   MachinePointerInfo callPtrInfo(StringRef Name);
 
   /// \brief Create a MachinePointerInfo that has a MipsCallEntr object
   /// representing a GOT entry for a global function.
   MachinePointerInfo callPtrInfo(const GlobalValue *Val);
 
private:
   unsigned IncomingArgSize;
 
   /// CallsEhReturn - Whether the function calls llvm.eh.return.
   bool CallsEhReturn;
 
   /// Frame objects for spilling eh data registers.
   int EhDataRegFI[4];
 
+  /// ISR - Whether the function is an Interrupt Service Routine.
+  bool ISR;
+
+  /// Frame objects for spilling C0_STATUS, C0_EPC
+  int ISRDataRegFI[2];
+
   // saveS2
   bool SaveS2;
 
   /// FrameIndex for expanding BuildPairF64 nodes to spill and reload when the
   /// O32 FPXX ABI is enabled. -1 is used to denote invalid index.
   int MoveF64ViaSpillFI;
 
   /// MipsCallEntry maps.
   StringMap<std::unique_ptr<const MipsCallEntry>> ExternalCallEntries;
   ValueMap<const GlobalValue *, std::unique_ptr<const MipsCallEntry>>
       GlobalCallEntries;
 };
 
 } // end of namespace llvm
 
 #endif

lib/Target/Mips/MipsMachineFunction.cpp

const TargetRegisterClass *RC =
             ? &Mips::GPR64RegClass
             : &Mips::GPR32RegClass;
 
     EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
         RC->getAlignment(), false);
   }
 }
 
+void MipsFunctionInfo::createISRRegFI() {
+  for (int I = 0; I < 2; ++I) {
+    const TargetRegisterClass *RC =
+        static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64()
+            ? &Mips::GPR64RegClass
+            : &Mips::GPR32RegClass;
+
+    ISRDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
+         RC->getAlignment(), true);
+  }
+}
+
 bool MipsFunctionInfo::isEhDataRegFI(int FI) const {
   return CallsEhReturn && (FI == EhDataRegFI[0] || FI == EhDataRegFI[1]
                         || FI == EhDataRegFI[2] || FI == EhDataRegFI[3]);
 }
 
+bool MipsFunctionInfo::isISRRegFI(int FI) const {
+  return ISR && (FI == ISRDataRegFI[0] || FI == ISRDataRegFI[1]);
+}
+
 MachinePointerInfo MipsFunctionInfo::callPtrInfo(StringRef Name) {
   std::unique_ptr<const MipsCallEntry> &E = ExternalCallEntries[Name];
 
   if (!E)
     E = llvm::make_unique<MipsCallEntry>(Name);
 
   return MachinePointerInfo(E.get());
 }

lib/Target/Mips/MipsRegisterInfo.cpp

 
 //===----------------------------------------------------------------------===//
 // Callee Saved Registers methods
 //===----------------------------------------------------------------------===//
 
 /// Mips Callee Saved Registers
 const MCPhysReg *
 MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
+
   const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
+  const Function *F = MF->getFunction();
+  if (F->hasFnAttribute("interrupt")){
+    if (Subtarget.hasMips64()){
+       if (Subtarget.hasMips64r6())
+         return CSR_Interrupt_64R6_SaveList;
+       else
+         return CSR_Interrupt_64_SaveList;
+    } else {
+       if (Subtarget.hasMips32r6())
+         return CSR_Interrupt_32R6_SaveList;
+       else
+         return CSR_Interrupt_32_SaveList;
+    }
+  }
+
   if (Subtarget.isSingleFloat())
     return CSR_SingleFloatOnly_SaveList;
 
   if (Subtarget.isABI_N64())
     return CSR_N64_SaveList;
 
   if (Subtarget.isABI_N32())
     return CSR_N32_SaveList;

lib/Target/Mips/MipsSEFrameLowering.h

bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  const std::vector<CalleeSavedInfo> &CSI,
                                  const TargetRegisterInfo *TRI) const override;
 
   bool hasReservedCallFrame(const MachineFunction &MF) const override;
 
   void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
                                             RegScavenger *RS) const override;
   unsigned ehDataReg(unsigned I) const;
-};
 
+private:
+  void emitInterruptEpilogueStub(MachineFunction &MF,
+                             MachineBasicBlock &MBB) const;
+  void emitInterruptPrologueStub(MachineFunction &MF,
+                             MachineBasicBlock &MBB) const; 
+};
 } // End llvm namespace
 
 #endif

lib/Target/Mips/MipsSEFrameLowering.cpp

void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
   TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
 
   // emit ".cfi_def_cfa_offset StackSize"
   unsigned CFIIndex = MMI.addFrameInst(
       MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
       .addCFIIndex(CFIIndex);
 
+  if (MF.getFunction()->hasFnAttribute("interrupt"))
+    emitInterruptPrologueStub(MF, MBB);
+
   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
 
   if (CSI.size()) {
     // Find the instruction past the last instruction that saves a callee-saved
     // register to the stack.
     for (unsigned i = 0; i < CSI.size(); ++i)
       ++MBBI;
 
if (RegInfo.needsStackRealignment(MF)) {
         BuildMI(MBB, MBBI, dl, TII.get(ADDu), BP)
           .addReg(SP)
           .addReg(ZERO);
       }
     }
   }
 }
 
+void MipsSEFrameLowering::emitInterruptPrologueStub(MachineFunction &MF,
+                                                MachineBasicBlock &MBB) const {
+  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
+
+  const MipsSEInstrInfo &TII =
+      *static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo());
+  const MipsRegisterInfo &RegInfo =
+      *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());
+
+  MachineBasicBlock::iterator MBBI = MBB.begin();
+  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
+
+  // Report error if in unsupported MIPS16 mode or pre-r2 MIPS.
+  if (!STI.hasMips32r2())
+    report_fatal_error(
+        "\"interrupt\" attribute is not supported on pre-r2 MIPS targets.");
+
+  if ((STI.getRelocationModel() != Reloc::Static))
+    report_fatal_error("\"interrupt\" attribute is only supported for the "
+                       "static relocation model on MIPS at the present time.");
+
+  if (!STI.isABI_O32() || STI.hasMips64())
+    report_fatal_error("\"interrupt\" attribute is only supported for the "
+                       "O32 ABI on MIPS32 at the present time.");
+
+  // Perform ISR handling like GCC
+  StringRef IntKind = MF.getFunction()->getFnAttribute("interrupt")
+    .getValueAsString();
+  const TargetRegisterClass *PtrRc = &Mips::GPR32RegClass;
+
+  // EIC interrupt handling needs to read the Cause register to disable
+  // interrupts.
+  if (IntKind == "eic") {
+    // Coprocessor registers are always live per se.
+    MBB.addLiveIn(Mips::COP013);
+    BuildMI(MBB, MBBI, dl, TII.get(Mips::MFC0), Mips::K0)
+      .addReg(Mips::COP013).addImm(0)
+      .setMIFlag(MachineInstr::FrameSetup);
+
+    BuildMI(MBB, MBBI, dl, TII.get(Mips::EXT), Mips::K0).addReg(Mips::K0)
+      .addImm(10).addImm(6).setMIFlag(MachineInstr::FrameSetup);
+
+  }
+
+  // Fetch and spill EPC
+  MBB.addLiveIn(Mips::COP014);
+  BuildMI(MBB, MBBI, dl, TII.get(Mips::MFC0), Mips::K1).addReg(Mips::COP014)
+    .addImm(0).setMIFlag(MachineInstr::FrameSetup);
+
+  TII.storeRegToStack(MBB, MBBI, Mips::K1, false, MipsFI->getISRRegFI(0),
+                          PtrRc, &RegInfo, 0);
+
+  // Fetch and Spill Status
+  MBB.addLiveIn(Mips::COP012);
+  BuildMI(MBB, MBBI, dl, TII.get(Mips::MFC0), Mips::K1).addReg(Mips::COP012)
+    .addImm(0).setMIFlag(MachineInstr::FrameSetup);
+
+  TII.storeRegToStack(MBB, MBBI, Mips::K1, false, MipsFI->getISRRegFI(1),
+                          PtrRc, &RegInfo, 0);
+
+  // Build the setup for masking off interrupts. Non EIC need to be masked
+  // off with zero, EIC from the Cause register.
+  unsigned InsPosition = 8;
+  unsigned InsSize = 0;
+  unsigned SrcReg = Mips::ZERO;
+
+  // If the interrupt we're tied to is the EIC, switch the source for the
+  // masking off interrupts to the cause register.
+  if (IntKind == "eic") {
+    SrcReg = Mips::K0;
+    InsPosition = 10;
+    InsSize = 6;
+  } else if (IntKind == "sw0")
+    InsSize = 1;
+  else if (IntKind == "sw1")
+    InsSize = 2;
+  else if (IntKind == "hw0")
+    InsSize = 3;
+  else if (IntKind == "hw1")
+    InsSize = 4;
+  else if (IntKind == "hw2")
+    InsSize = 5;
+  else if (IntKind == "hw3")
+    InsSize = 6;
+  else if (IntKind == "hw4")
+    InsSize = 7;
+  else if (IntKind == "hw5")
+    InsSize = 8;
+  else
+    llvm_unreachable("Unknown Mips interrupt type!");
+
+  BuildMI(MBB, MBBI, dl, TII.get(Mips::INS), Mips::K1).addReg(SrcReg)
+    .addImm(InsPosition).addImm(InsSize).addReg(Mips::K1)
+    .setMIFlag(MachineInstr::FrameSetup);
+
+  // Mask off KSU, ERL, EXL
+  BuildMI(MBB, MBBI, dl, TII.get(Mips::INS), Mips::K1).addReg(Mips::ZERO)
+    .addImm(1).addImm(4).addReg(Mips::K1).setMIFlag(MachineInstr::FrameSetup);
+
+  // Disable the FPU as we are not spilling those register sets.
+  if (!STI.useSoftFloat())
+    BuildMI(MBB, MBBI, dl, TII.get(Mips::INS), Mips::K1).addReg(Mips::ZERO)
+      .addImm(29).addImm(1).addReg(Mips::K1).setMIFlag(MachineInstr::FrameSetup);
+
+  // Set the new status
+  BuildMI(MBB, MBBI, dl, TII.get(Mips::MTC0), Mips::COP012).addReg(Mips::K1)
+    .addImm(0)
+    .setMIFlag(MachineInstr::FrameSetup);
+}
+
 void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
                                        MachineBasicBlock &MBB) const {
   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
   MachineFrameInfo *MFI            = MF.getFrameInfo();
   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 
   const MipsSEInstrInfo &TII =
       *static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo());
if (MipsFI->callsEhReturn()) {
 
     // Insert instructions that restore eh data registers.
     for (int J = 0; J < 4; ++J) {
       TII.loadRegFromStackSlot(MBB, I, ABI.GetEhDataReg(J),
                                MipsFI->getEhDataRegFI(J), RC, &RegInfo);
     }
   }
 
+  if (MF.getFunction()->hasFnAttribute("interrupt"))
+    emitInterruptEpilogueStub(MF, MBB);
+
   // Get the number of bytes from FrameInfo
   uint64_t StackSize = MFI->getStackSize();
 
   if (!StackSize)
     return;
 
   // Adjust stack.
   TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
 }
 
+void MipsSEFrameLowering::emitInterruptEpilogueStub(MachineFunction &MF,
+                                       MachineBasicBlock &MBB) const {
+
+  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
+  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
+  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
+
+  const MipsSEInstrInfo &TII =
+      *static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo());
+  const MipsRegisterInfo &RegInfo =
+      *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());
+
+  // Perform ISR handling like GCC
+  const TargetRegisterClass *PtrRc = &Mips::GPR32RegClass;
+
+  // Disable Interrupts.
+  BuildMI(MBB, MBBI, dl, TII.get(Mips::DI), Mips::ZERO);
+  BuildMI(MBB, MBBI, dl, TII.get(Mips::EHB));
+
+  // Restore EPC
+  TII.loadRegFromStackSlot(MBB, MBBI, Mips::K1, MipsFI->getISRRegFI(0),
+                          PtrRc, &RegInfo);
+  BuildMI(MBB, MBBI, dl, TII.get(Mips::MTC0), Mips::COP014).addReg(Mips::K1)
+    .addImm(0);
+
+  // Restore Status
+  TII.loadRegFromStackSlot(MBB, MBBI, Mips::K1, MipsFI->getISRRegFI(1),
+                           PtrRc, &RegInfo);
+  BuildMI(MBB, MBBI, dl, TII.get(Mips::MTC0), Mips::COP012)
+    .addReg(Mips::K1).addImm(0);
+
+}
 bool MipsSEFrameLowering::
 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator MI,
                           const std::vector<CalleeSavedInfo> &CSI,
                           const TargetRegisterInfo *TRI) const {
   MachineFunction *MF = MBB.getParent();
   MachineBasicBlock *EntryBlock = MF->begin();
   const TargetInstrInfo &TII = *STI.getInstrInfo();
 
   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
     // Add the callee-saved register as live-in. Do not add if the register is
     // RA and return address is taken, because it has already been added in
     // method MipsTargetLowering::LowerRETURNADDR.
     // It's killed at the spill, unless the register is RA and return address
     // is taken.
     unsigned Reg = CSI[i].getReg();
     bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
         && MF->getFrameInfo()->isReturnAddressTaken();
     if (!IsRAAndRetAddrIsTaken)
       EntryBlock->addLiveIn(Reg);
 
+    // Handle LO, HI for ISRs.
+    bool IsLOOrHI = (Reg == Mips::LO0 || Reg == Mips::LO0_64
+        || Reg == Mips::HI0 || Reg == Mips::HI0_64);
+    const Function * Func = MBB.getParent()->getFunction();
+    if (IsLOOrHI && Func->hasFnAttribute("interrupt")){
+      DebugLoc dl;
+      if (MI != MBB.end()) dl = MI->getDebugLoc();
+
+      if (Reg == Mips::HI0 || Reg == Mips::LO0){
+        if (Reg == Mips::HI0)
+          BuildMI(MBB, MI, dl, TII.get(Mips::MFLO), Mips::K0)
+            .setMIFlag(MachineInstr::FrameSetup);
+        else
+          BuildMI(MBB, MI, dl, TII.get(Mips::MFHI), Mips::K0)
+            .setMIFlag(MachineInstr::FrameSetup);
+
+        Reg = Mips::K0;
+      } else {
+       if (Reg == Mips::HI0_64)
+         BuildMI(MBB, MI, dl, TII.get(Mips::MFLO64), Mips::K0_64)
+           .setMIFlag(MachineInstr::FrameSetup);
+       else
+         BuildMI(MBB, MI, dl, TII.get(Mips::MFHI64), Mips::K0_64)
+           .setMIFlag(MachineInstr::FrameSetup);
+
+       Reg = Mips::K0_64;
+     }
+    }
+
     // Insert the spill to the stack frame.
     bool IsKill = !IsRAAndRetAddrIsTaken;
     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
     TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
                             CSI[i].getFrameIdx(), RC, TRI);
   }
 
   return true;
processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
   // Mark $s7 as used if function has dedicated base pointer.
   if (hasBP(MF))
     MRI.setPhysRegUsed(BP);
 
   // Create spill slots for eh data registers if function calls eh_return.
   if (MipsFI->callsEhReturn())
     MipsFI->createEhDataRegsFI();
 
+  // Create spill slots for COP0 registers if function is an ISR.
+  if (MipsFI->isISR())
+    MipsFI->createISRRegFI();
+
   // Expand pseudo instructions which load, store or copy accumulators.
   // Add an emergency spill slot if a pseudo was expanded.
   if (ExpandPseudo(MF).expand()) {
     // The spill slot should be half the size of the accumulator. If target is
     // mips64, it should be 64-bit, otherwise it should be 32-bt.
     const TargetRegisterClass *RC = STI.hasMips64() ?
       &Mips::GPR64RegClass : &Mips::GPR32RegClass;
     int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),

lib/Target/Mips/MipsSEISelLowering.cpp

 }
 
 bool MipsSETargetLowering::isEligibleForTailCallOptimization(
     const CCState &CCInfo, unsigned NextStackOffset,
     const MipsFunctionInfo &FI) const {
   if (!EnableMipsTailCalls)
     return false;
 
+  // Exception has to be cleared with eret.
+  if (FI.isISR())
+    return false;
+
   // Return false if either the callee or caller has a byval argument.
   if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg())
     return false;
 
   // Return true if the callee's argument area is no larger than the
   // caller's.
   return NextStackOffset <= FI.getIncomingArgSize();
 }

lib/Target/Mips/MipsSEInstrInfo.h

unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator II, DebugLoc DL,
                          unsigned *NewImm) const;
 
 private:
   unsigned getAnalyzableBrOpc(unsigned Opc) const override;
 
   void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
 
+  void expandERet(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
+
   std::pair<bool, bool> compareOpndSize(unsigned Opc,
                                         const MachineFunction &MF) const;
 
   void expandPseudoMFHiLo(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                           unsigned NewOpc) const;
 
   void expandPseudoMTLoHi(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                           unsigned LoOpc, unsigned HiOpc,

lib/Target/Mips/MipsSEInstrInfo.cpp

storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
                 int64_t Offset) const {
   DebugLoc DL;
   if (I != MBB.end()) DL = I->getDebugLoc();
   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
 
   unsigned Opc = 0;
 
+  const Function * Func = MBB.getParent()->getFunction();
+  if (Func->hasFnAttribute("interrupt")){
+    if (Mips::HI32RegClass.hasSubClassEq(RC)){
+        BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
+        SrcReg = Mips::K0;
+    } else if (Mips::HI64RegClass.hasSubClassEq(RC)){
+        BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
+        SrcReg = Mips::K0_64;
+    } else if (Mips::LO32RegClass.hasSubClassEq(RC)){
+        BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
+        SrcReg = Mips::K0;
+    } else if (Mips::LO64RegClass.hasSubClassEq(RC)){
+        BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
+        SrcReg = Mips::K0_64;
+    }
+  }
+
   if (Mips::GPR32RegClass.hasSubClassEq(RC))
     Opc = Mips::SW;
   else if (Mips::GPR64RegClass.hasSubClassEq(RC))
     Opc = Mips::SD;
   else if (Mips::ACC64RegClass.hasSubClassEq(RC))
     Opc = Mips::STORE_ACC64;
   else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
     Opc = Mips::STORE_ACC64DSP;
storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
   else if (RC->hasType(MVT::v16i8))
     Opc = Mips::ST_B;
   else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
     Opc = Mips::ST_H;
   else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
     Opc = Mips::ST_W;
   else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
     Opc = Mips::ST_D;
+  else if (Mips::LO32RegClass.hasSubClassEq(RC))
+    Opc = Mips::SW;
+  else if (Mips::LO64RegClass.hasSubClassEq(RC))
+    Opc = Mips::SD;
+  else if (Mips::HI32RegClass.hasSubClassEq(RC))
+    Opc = Mips::SW;
+  else if (Mips::HI64RegClass.hasSubClassEq(RC))
+    Opc = Mips::SD;
 
   assert(Opc && "Register class not handled!");
   BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
     .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
 }
 
 void MipsSEInstrInfo::
 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                  unsigned DestReg, int FI, const TargetRegisterClass *RC,
                  const TargetRegisterInfo *TRI, int64_t Offset) const {
   DebugLoc DL;
   if (I != MBB.end()) DL = I->getDebugLoc();
   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
   unsigned Opc = 0;
 
+
+  const Function * Func = MBB.getParent()->getFunction();
+  bool reqIndirectLoad = Func->hasFnAttribute("interrupt")
+      && (DestReg == Mips::LO0 || DestReg == Mips::LO0_64
+          || DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
+
   if (Mips::GPR32RegClass.hasSubClassEq(RC))
     Opc = Mips::LW;
   else if (Mips::GPR64RegClass.hasSubClassEq(RC))
     Opc = Mips::LD;
   else if (Mips::ACC64RegClass.hasSubClassEq(RC))
     Opc = Mips::LOAD_ACC64;
   else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
     Opc = Mips::LOAD_ACC64DSP;
loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
   else if (RC->hasType(MVT::v16i8))
     Opc = Mips::LD_B;
   else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
     Opc = Mips::LD_H;
   else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
     Opc = Mips::LD_W;
   else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
     Opc = Mips::LD_D;
+  else if (Mips::HI32RegClass.hasSubClassEq(RC))
+    Opc = Mips::LW;
+  else if (Mips::HI64RegClass.hasSubClassEq(RC))
+    Opc = Mips::LD;
+  else if (Mips::LO32RegClass.hasSubClassEq(RC))
+    Opc = Mips::LW;
+  else if (Mips::LO64RegClass.hasSubClassEq(RC))
+    Opc = Mips::LD;
 
   assert(Opc && "Register class not handled!");
+
+  if (!reqIndirectLoad)
     BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
       .addMemOperand(MMO);
+  else {
+
+    unsigned Reg = Mips::K0;
+    unsigned LdOp = Mips::MTLO;
+    if (DestReg == Mips::HI0) LdOp = Mips::MTHI;
+
+    if (DestReg == Mips::HI0_64 || DestReg == Mips::LO0_64){
+      Reg = Mips::K0_64;
+      if (DestReg == Mips::HI0_64)
+        LdOp = Mips::MTHI64;
+      else
+        LdOp = Mips::MTLO64;
+    }
+
+    BuildMI(MBB, I, DL, get(Opc), Reg).addFrameIndex(FI).addImm(Offset)
+       .addMemOperand(MMO);
+    BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
+  }
 }
 
 bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
   MachineBasicBlock &MBB = *MI->getParent();
   bool isMicroMips = Subtarget.inMicroMipsMode();
   unsigned Opc;
 
   switch(MI->getDesc().getOpcode()) {
   default:
     return false;
   case Mips::RetRA:
     expandRetRA(MBB, MI);
     break;
+  case Mips::ERet:
+    expandERet(MBB, MI);
+    break;
   case Mips::PseudoMFHI:
     Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
     expandPseudoMFHiLo(MBB, MI, Opc);
     break;
   case Mips::PseudoMFLO:
     Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
     expandPseudoMFHiLo(MBB, MI, Opc);
     break;
void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator I) const {
   if (Subtarget.isGP64bit())
     BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
         .addReg(Mips::RA_64);
   else
     BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)).addReg(Mips::RA);
 }
 
+void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB,
+                                  MachineBasicBlock::iterator I) const {
+  BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERet));
+}
+
 std::pair<bool, bool>
 MipsSEInstrInfo::compareOpndSize(unsigned Opc,
                                  const MachineFunction &MF) const {
   const MCInstrDesc &Desc = get(Opc);
   assert(Desc.NumOperands == 2 && "Unary instruction expected.");
   const MipsRegisterInfo *RI = &getRegisterInfo();
   unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize();
   unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize();

lib/Target/Mips/MipsSERegisterInfo.cpp

void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
   int MaxCSFI = -1;
 
   if (CSI.size()) {
     MinCSFI = CSI[0].getFrameIdx();
     MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
   }
 
   bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex);
-
+  bool ISRRegFI = MipsFI->isISRRegFI(FrameIndex);
   // The following stack frame objects are always referenced relative to $sp:
   //  1. Outgoing arguments.
   //  2. Pointer to dynamically allocated stack space.
   //  3. Locations for callee-saved registers.
   //  4. Locations for eh data registers.
+  //  5. Locations for ISR saved CP0 12, 14 registers.
   // Everything else is referenced relative to whatever register
   // getFrameRegister() returns.
   unsigned FrameReg;
 
-  if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI)
+  if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI)
+    || EhDataRegFI || ISRRegFI)
        FrameReg = ABI.GetStackPtr();
   else if (RegInfo->needsStackRealignment(MF)) {
     if (MFI->hasVarSizedObjects() && !MFI->isFixedObjectIndex(FrameIndex))
       FrameReg = ABI.GetBasePtr();
     else if (MFI->isFixedObjectIndex(FrameIndex))
       FrameReg = getFrameRegister(MF);
     else
       FrameReg = ABI.GetStackPtr();
   } else

test/CodeGen/Mips/interrupt-attr-fail.ll

+; RUN: llc -mcpu=mips32 -march=mipsel -relocation-model=static -o - %s | FileCheck --check-prefix=CHECK %s
+; XFAIL: *
+
+define void @_mips_isr_sw0() #0 {
+  call void bitcast (void (...)* @write to void ()*)()
+}
+
+declare void @write(...)
+
+attributes #0 = { "interrupt"="sw0" }
+

test/CodeGen/Mips/interrupt-attr.ll

+; RUN: llc -mcpu=mips32r2 -march=mipsel -relocation-model=static -o - %s | FileCheck --check-prefix=CHECK %s
+
+
+define void @_mips_isr_sw0() #0 {
+; CHECK: mfc0   $27, $14, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: mfc0   $27, $12, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: ins    $27, $zero, 8, 1
+; CHECK: ins    $27, $zero, 1, 4
+; CHECK: ins    $27, $zero, 29, 1
+; CHECK: mtc0   $27, $12, 0
+  ; Must save all registers
+; CHECK: sw      $7, {{[0-9]+}}($sp)
+; CHECK: sw      $6, {{[0-9]+}}($sp)
+; CHECK: sw      $5, {{[0-9]+}}($sp)
+; CHECK: sw      $4, {{[0-9]+}}($sp)
+; CHECK: sw      $3, {{[0-9]+}}($sp)
+; CHECK: sw      $2, {{[0-9]+}}($sp)
+; CHECK: sw      $25, {{[0-9]+}}($sp)
+; CHECK: sw      $24, {{[0-9]+}}($sp)
+; CHECK: sw      $15, {{[0-9]+}}($sp)
+; CHECK: sw      $14, {{[0-9]+}}($sp)
+; CHECK: sw      $13, {{[0-9]+}}($sp)
+; CHECK: sw      $12, {{[0-9]+}}($sp)
+; CHECK: sw      $11, {{[0-9]+}}($sp)
+; CHECK: sw      $10, {{[0-9]+}}($sp)
+; CHECK: sw      $9, {{[0-9]+}}($sp)
+; CHECK: sw      $8, {{[0-9]+}}($sp)            # 4-byte Folded Spill
+; CHECK: sw      $ra, {{[0-9]+}}($sp)            # 4-byte Folded Spill
+; HECK: sw      $fp, {{[0-9]+}}($sp)            # 4-byte Folded Spill
+; CHECK: sw      $gp, {{[0-9]+}}($sp)            # 4-byte Folded Spill
+; CHECK: sw      $1, {{[0-9]+}}($sp)            # 4-byte Folded Spill
+; CHECK: mfhi    $26
+; CHECK: sw      $26, {{[0-9]+}}($sp)
+; CHECK: mflo    $26
+; CHECK: sw      $26, {{[0-9]+}}($sp)
+  call void bitcast (void (...)* @write to void ()*)()
+; CHECK: lw      $26, {{[0-9]+}}($sp)
+; CHECK: mthi    $26
+; CHECK: lw      $26, {{[0-9]+}}($sp)
+; CHECK: mtlo    $26
+; CHECK: lw      $1, {{[0-9]+}}($sp)
+; CHECK: lw      $gp, {{[0-9]+}}($sp)
+; HECK: lw      $fp, {{[0-9]+}}($sp) # 4-byte Folded Reload
+; CHECK: lw      $ra, {{[0-9]+}}($sp) # 4-byte Folded Reload
+; CHECK: lw      $8, {{[0-9]+}}($sp)
+; CHECK: lw      $9, {{[0-9]+}}($sp)
+; CHECK: lw      $10, {{[0-9]+}}($sp)
+; CHECK: lw      $11, {{[0-9]+}}($sp)
+; CHECK: lw      $12, {{[0-9]+}}($sp)
+; CHECK: lw      $13, {{[0-9]+}}($sp)
+; CHECK: lw      $14, {{[0-9]+}}($sp)
+; CHECK: lw      $15, {{[0-9]+}}($sp)
+; CHECK: lw      $24, {{[0-9]+}}($sp)
+; CHECK: lw      $25, {{[0-9]+}}($sp)
+; CHECK: lw      $2, {{[0-9]+}}($sp)
+; CHECK: lw      $3, {{[0-9]+}}($sp)
+; CHECK: lw      $4, {{[0-9]+}}($sp)
+; CHECK: lw      $5, {{[0-9]+}}($sp)
+; CHECK: lw      $6, {{[0-9]+}}($sp)
+; CHECK: lw      $7, {{[0-9]+}}($sp)
+; CHECK: di
+; CHECK: ehb
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $14, 0
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $12, 0
+; CHECK: eret
+  ret void
+}
+
+declare void @write(...)
+
+define void @_mips_isr_sw1() #2 {
+entry:
+; CHECK: mfc0   $27, $14, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: mfc0   $27, $12, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: ins    $27, $zero, 8, 2
+; CHECK: ins    $27, $zero, 1, 4
+; CHECK: ins    $27, $zero, 29, 1
+; CHECK: mtc0   $27, $12, 0
+  ret void
+; CHECK: di
+; CHECK: ehb
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $14, 0
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $12, 0
+; CHECK: eret
+ }
+
+
+define void @_mips_isr_hw0() #3 {
+entry:
+; CHECK: mfc0   $27, $14, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: mfc0   $27, $12, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: ins    $27, $zero, 8, 3
+; CHECK: ins    $27, $zero, 1, 4
+; CHECK: ins    $27, $zero, 29, 1
+; CHECK: mtc0   $27, $12, 0
+  ret void
+; CHECK: di
+; CHECK: ehb
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $14, 0
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $12, 0
+; CHECK: eret
+ }
+
+
+define void @_mips_isr_hw1() #4 {
+entry:
+; CHECK: mfc0   $27, $14, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: mfc0   $27, $12, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: ins    $27, $zero, 8, 4
+; CHECK: ins    $27, $zero, 1, 4
+; CHECK: ins    $27, $zero, 29, 1
+; CHECK: mtc0   $27, $12, 0
+  ret void
+; CHECK: di
+; CHECK: ehb
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $14, 0
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $12, 0
+; CHECK: eret
+ }
+
+
+define void @_mips_isr_hw2() #5 {
+entry:
+; CHECK: mfc0   $27, $14, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: mfc0   $27, $12, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: ins    $27, $zero, 8, 5
+; CHECK: ins    $27, $zero, 1, 4
+; CHECK: ins    $27, $zero, 29, 1
+; CHECK: mtc0   $27, $12, 0
+  ret void
+; CHECK: di
+; CHECK: ehb
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $14, 0
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $12, 0
+; CHECK: eret
+ }
+
+
+define void @_mips_isr_hw3() #6 {
+entry:
+; CHECK: mfc0   $27, $14, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: mfc0   $27, $12, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: ins    $27, $zero, 8, 6
+; CHECK: ins    $27, $zero, 1, 4
+; CHECK: ins    $27, $zero, 29, 1
+; CHECK: mtc0   $27, $12, 0
+  ret void
+; CHECK: di
+; CHECK: ehb
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $14, 0
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $12, 0
+; CHECK: eret
+ }
+
+
+define void @_mips_isr_hw4() #7 {
+entry:
+; CHECK: mfc0   $27, $14, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: mfc0   $27, $12, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: ins    $27, $zero, 8, 7
+; CHECK: ins    $27, $zero, 1, 4
+; CHECK: ins    $27, $zero, 29, 1
+; CHECK: mtc0   $27, $12, 0
+  ret void
+; CHECK: di
+; CHECK: ehb
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $14, 0
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $12, 0
+; CHECK: eret
+ }
+
+
+define void @_mips_isr_hw5() #8 {
+entry:
+; CHECK: mfc0   $27, $14, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: mfc0   $27, $12, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: ins    $27, $zero, 8, 8
+; CHECK: ins    $27, $zero, 1, 4
+; CHECK: ins    $27, $zero, 29, 1
+; CHECK: mtc0   $27, $12, 0
+  ret void
+; CHECK: di
+; CHECK: ehb
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $14, 0
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $12, 0
+; CHECK: eret
+ }
+
+
+define void @_mips_isr_eic() #9 {
+entry:
+; CHECK: mfc0   $26, $13, 0
+; CHECK: ext    $26, $26, 10, 6
+; CHECK: mfc0   $27, $14, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: mfc0   $27, $12, 0
+; CHECK: sw     $27, {{[0-9]+}}($sp)
+; CHECK: ins    $27, $26, 10, 6
+; CHECK: ins    $27, $zero, 1, 4
+; CHECK: ins    $27, $zero, 29, 1
+; CHECK: mtc0   $27, $12, 0
+  ret void
+; CHECK: di
+; CHECK: ehb
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $14, 0
+; CHECK: lw      $27, {{[0-9]+}}($sp)
+; CHECK: mtc0    $27, $12, 0
+; CHECK: eret
+ }
+
+attributes #0 = { "interrupt"="sw0" }
+attributes #2 = { "interrupt"="sw1" }
+attributes #3 = { "interrupt"="hw0" }
+attributes #4 = { "interrupt"="hw1" }
+attributes #5 = { "interrupt"="hw2" }
+attributes #6 = { "interrupt"="hw3" }
+attributes #7 = { "interrupt"="hw4" }
+attributes #8 = { "interrupt"="hw5" }
+attributes #9 = { "interrupt"="eic" }