Refactor: Simplify boolean conditional return statements in lib/Target/R600

[LegalizeAdulthood]

Summary

Use clang-tidy to simplify boolean conditional return statements

[craig.topper]

lib/Target/R600/R600InstrInfo.cpp

916

Push the negate through.

lib/Target/R600/R600Packetizer.cpp

215

Push the negate through

[LegalizeAdulthood]

lib/Target/R600/R600InstrInfo.cpp

916

Fixed.

lib/Target/R600/R600Packetizer.cpp

215

Fixed.

[LegalizeAdulthood]

Update from comments, clang-format

[LegalizeAdulthood]

clang-format

[• tstellarAMD]

LGTM.

[LegalizeAdulthood]

I do not have commit access, so someone else will need to commit this. Let me know if it needs rebasing.

Patch by Richard Thomson.

[LegalizeAdulthood]

Discarding due to inaction by reviewers.

[arsenm]

r262536 with fixups for trunk

lib/Target/R600/AMDGPUISelDAGToDAG.cpp

if (checkPrivateAddress(N->getMemOperand())) {
     // Check to make sure we are not a constant pool load or a constant load
     // that is marked as a private load
     if (isCPLoad(N) || isConstantLoad(N, -1)) {
       return false;
     }
   }
 
   const Value *MemVal = N->getMemOperand()->getValue();
-  if (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
+  return !checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
          !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
          !checkType(MemVal, AMDGPUAS::FLAT_ADDRESS) &&
          !checkType(MemVal, AMDGPUAS::REGION_ADDRESS) &&
          !checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS) &&
          !checkType(MemVal, AMDGPUAS::PARAM_D_ADDRESS) &&
-      !checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS)) {
-    return true;
-  }
-  return false;
+         !checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS);
 }
 
 const char *AMDGPUDAGToDAGISel::getPassName() const {
   return "AMDGPU DAG->DAG Pattern Instruction Selection";
 }
 
 #ifdef DEBUGTMP
 #undef INT64_C

lib/Target/R600/AMDGPUISelLowering.cpp

SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
   llvm_unreachable("Unhandled constant initializer");
 }
 
 static bool hasDefinedInitializer(const GlobalValue *GV) {
   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
   if (!GVar || !GVar->hasInitializer())
     return false;
 
-  if (isa<UndefValue>(GVar->getInitializer()))
-    return false;
-
-  return true;
+  return !isa<UndefValue>(GVar->getInitializer());
 }
 
 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
                                                  SDValue Op,
                                                  SelectionDAG &DAG) const {
 
   const DataLayout *TD = getDataLayout();
   GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);

lib/Target/R600/R600InstrInfo.cpp

R600InstrInfo::isPredicable(MachineInstr *MI) const {
   if (MI->getOpcode() == AMDGPU::KILLGT) {
     return false;
   } else if (MI->getOpcode() == AMDGPU::CF_ALU) {
     // If the clause start in the middle of MBB then the MBB has more
     // than a single clause, unable to predicate several clauses.
     if (MI->getParent()->begin() != MachineBasicBlock::iterator(MI))
       return false;
     // TODO: We don't support KC merging atm
-    if (MI->getOperand(3).getImm() != 0 || MI->getOperand(4).getImm() != 0)
-      return false;
-    return true;
+    return MI->getOperand(3).getImm() == 0 && MI->getOperand(4).getImm() == 0;
   } else if (isVector(*MI)) {
     return false;
   } else {
     return AMDGPUInstrInfo::isPredicable(MI);
   }
 }
 
 

lib/Target/R600/R600Packetizer.cpp

bool isSoloInstruction(MachineInstr *MI) override {
     if (TII->isVector(*MI))
       return true;
     if (!TII->isALUInstr(MI->getOpcode()))
       return true;
     if (MI->getOpcode() == AMDGPU::GROUP_BARRIER)
       return true;
     // XXX: This can be removed once the packetizer properly handles all the
     // LDS instruction group restrictions.
-    if (TII->isLDSInstr(MI->getOpcode()))
-      return true;
-    return false;
+    return TII->isLDSInstr(MI->getOpcode());
   }
 
   // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
   // together.
   bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override {
     MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
     if (getSlot(MII) == getSlot(MIJ))
       ConsideredInstUsesAlreadyWrittenVectorElement = true;
if (SUJ->isSucc(SUI)) {
         return false;
       }
     }
 
     bool ARDef = TII->definesAddressRegister(MII) ||
                  TII->definesAddressRegister(MIJ);
     bool ARUse = TII->usesAddressRegister(MII) ||
                  TII->usesAddressRegister(MIJ);
-    if (ARDef && ARUse)
-      return false;
-
-    return true;
+    return !ARDef || !ARUse;
   }
 
   // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
   // and SUJ.
   bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override {
     return false;
   }
 

lib/Target/R600/SIInsertWaits.cpp

if (TII->isDS(MI.getOpcode())) {
     if (Data && Op.isIdenticalTo(*Data))
       return true;
 
     MachineOperand *Data0 = TII->getNamedOperand(MI, AMDGPU::OpName::data0);
     if (Data0 && Op.isIdenticalTo(*Data0))
       return true;
 
     MachineOperand *Data1 = TII->getNamedOperand(MI, AMDGPU::OpName::data1);
-    if (Data1 && Op.isIdenticalTo(*Data1))
-      return true;
-
-    return false;
+    return Data1 && Op.isIdenticalTo(*Data1);
   }
 
   // NOTE: This assumes that the value operand is before the
   // address operand, and that there is only one value operand.
   for (MachineInstr::mop_iterator I = MI.operands_begin(),
        E = MI.operands_end(); I != E; ++I) {
 
     if (I->isReg() && I->isUse())

lib/Target/R600/SIInstrInfo.cpp

if (NumLoads > 4)
     return false;
 
   if (isDS(Opc0) && isDS(Opc1))
     return true;
 
   if (isSMRD(Opc0) && isSMRD(Opc1))
     return true;
 
-  if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1)))
-    return true;
-
-  return false;
+  return (isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1));
 }
 
 void
 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator MI, DebugLoc DL,
                          unsigned DestReg, unsigned SrcReg,
                          bool KillSrc) const {
 
bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
   if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
     return true;
 
   // EXEC register uses the constant bus.
   if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
     return true;
 
   // SGPRs use the constant bus
-  if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
-      (!MO.isImplicit() &&
-      (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
-       AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
-    return true;
-  }
-
-  return false;
+  return MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
+         (!MO.isImplicit() && (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
+                               AMDGPU::SGPR_64RegClass.contains(MO.getReg())));
 }
 
 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
                                     StringRef &ErrInfo) const {
   uint16_t Opcode = MI->getOpcode();
   const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
   int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
   int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);

lib/Target/R600/SIShrinkInstructions.cpp

static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII,
   // src0 isn't using any modifiers.
   if (TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers))
     return false;
 
   // Check output modifiers
   if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod))
     return false;
 
-  if (TII->hasModifiersSet(MI, AMDGPU::OpName::clamp))
-    return false;
-
-  return true;
+  return !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp);
 }
 
 /// \brief This function checks \p MI for operands defined by a move immediate
 /// instruction and then folds the literal constant into the instruction if it
 /// can.  This function assumes that \p MI is a VOP1, VOP2, or VOPC instruction
 /// and will only fold literal constants if we are still in SSA.
 static void foldImmediates(MachineInstr &MI, const SIInstrInfo *TII,
                            MachineRegisterInfo &MRI, bool TryToCommute = true) {