Refactor: Simplify boolean conditional return statements in lib/Target/Hexagon

[LegalizeAdulthood]

Summary

Use clang-tidy to simplify boolean conditional return statements

[craig.topper]

lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

413

Operators should be on end of previous line.

[LegalizeAdulthood]

lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

413

Fixed.

[LegalizeAdulthood]

Update from comments, clang-format

[LegalizeAdulthood]

Update to latest

lib/Target/Hexagon/HexagonCopyToCombine.cpp

static bool areCombinableOperations(const TargetRegisterInfo *TRI,
   unsigned LoOpc = LowRegInst->getOpcode();
   (void)HiOpc; // Fix compiler warning
   (void)LoOpc; // Fix compiler warning
   assert((HiOpc == Hexagon::A2_tfr || HiOpc == Hexagon::A2_tfrsi) &&
          (LoOpc == Hexagon::A2_tfr || LoOpc == Hexagon::A2_tfrsi) &&
          "Assume individual instructions are of a combinable type");
 
   // There is no combine of two constant extended values.
-  if (isGreaterThanNBitTFRI<8>(HighRegInst) &&
-      isGreaterThanNBitTFRI<6>(LowRegInst))
-    return false;
-
-  return true;
+  return !(isGreaterThanNBitTFRI<8>(HighRegInst) &&
+           isGreaterThanNBitTFRI<6>(LowRegInst));
 }
 
 static bool isEvenReg(unsigned Reg) {
   assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
          Hexagon::IntRegsRegClass.contains(Reg));
   return (Reg - Hexagon::R0) % 2 == 0;
 }
 

lib/Target/Hexagon/HexagonEarlyIfConv.cpp

if (FP.JoinB) {
     }
   }
   DEBUG(dbgs() << "Total number of extra muxes from converted phis: "
                << TotalPh << "\n");
   if (TotalIn+TotalPh >= SizeLimit+Spare)
     return false;
 
   DEBUG(dbgs() << "Total number of predicate registers: " << PredDefs << "\n");
-  if (PredDefs > 4)
-    return false;
-
-  return true;
+  return PredDefs <= 4;
 }
 
 
 bool HexagonEarlyIfConversion::visitBlock(MachineBasicBlock *B,
       MachineLoop *L) {
   bool Changed = false;
 
   // Visit all dominated blocks from the same loop first, then process B.

lib/Target/Hexagon/HexagonExpandCondsets.cpp

 
 
 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
       unsigned Exec) {
   ReferenceMap::iterator F = Map.find(RR.Reg);
   if (F == Map.end())
     return false;
   unsigned Mask = getMaskForSub(RR.Sub) | Exec;
-  if (Mask & F->second)
-    return true;
-  return false;
+  return static_cast<bool>(Mask & F->second);
 }
 
 
 LiveInterval::iterator HexagonExpandCondsets::nextSegment(LiveInterval &LI,
       SlotIndex S) {
   for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
     if (I->start >= S)
       return I;

lib/Target/Hexagon/HexagonFrameLowering.cpp

 }
 
 
 bool HexagonFrameLowering::needsAligna(const MachineFunction &MF) const {
   const MachineFrameInfo *MFI = MF.getFrameInfo();
   if (!MFI->hasVarSizedObjects())
     return false;
   unsigned MaxA = MFI->getMaxAlignment();
-  if (MaxA <= getStackAlignment())
-    return false;
-  return true;
+  return MaxA > getStackAlignment();
 }
 
 
 const MachineInstr *HexagonFrameLowering::getAlignaInstr(
       const MachineFunction &MF) const {
   for (auto &B : MF)
     for (auto &I : B)
       if (I.getOpcode() == Hexagon::ALIGNA)

lib/Target/Hexagon/HexagonHardwareLoops.cpp

for (MachineRegisterInfo::use_instr_nodbg_iterator I = MRI->use_instr_nodbg_begin(Reg),
     // range check.
     if ((Cmp & Comparison::G) || Cmp == Comparison::NE)
       return false;
   }
 
   // OK - this is a hack that needs to be improved. We really need to analyze
   // the instructions performed on the initial value. This works on the simplest
   // cases only.
-  if (!Def->isCopy() && !Def->isPHI())
-    return false;
-
-  return true;
+  return !(!Def->isCopy() && !Def->isPHI());
 }
 
 bool HexagonHardwareLoops::checkForImmediate(const MachineOperand &MO,
                                              int64_t &Val) const {
   if (MO.isImm()) {
     Val = MO.getImm();
     return true;
   }

lib/Target/Hexagon/HexagonISelLowering.cpp

HexagonTargetLowering::LowerReturn(SDValue Chain,
 
   return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
 }
 
 bool HexagonTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
   // If either no tail call or told not to tail call at all, don't.
   auto Attr =
       CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
-  if (!CI->isTailCall() || Attr.getValueAsString() == "true")
-    return false;
-
-  return true;
+  return !(!CI->isTailCall() || Attr.getValueAsString() == "true");
 }
 
 /// LowerCallResult - Lower the result values of an ISD::CALL into the
 /// appropriate copies out of appropriate physical registers.  This assumes that
 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
 /// being lowered. Returns a SDNode with the same number of values as the
 /// ISD::CALL.
 SDValue

lib/Target/Hexagon/HexagonInstrInfo.cpp

switch (MI->getOpcode())
     //                      +-----------------------------+
     //                           Double Dot New Store
     //
   }
 }
 
 
 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
-  if (isNewValue(MI) && isBranch(MI))
-    return true;
-  return false;
+  return isNewValue(MI) && isBranch(MI);
 }
 
 bool HexagonInstrInfo::isNewValueJump(Opcode_t Opcode) const {
   return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
 }
 
 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
   return (getAddrMode(MI) == HexagonII::PostInc);
bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
   // dbg_value followed by an IT will result in the IT instruction being
   // considered a scheduling hazard, which is wrong. It should be the actual
   // instruction preceding the dbg_value instruction(s), just like it is
   // when debug info is not present.
   if (MI->isDebugValue())
     return false;
 
   // Terminators and labels can't be scheduled around.
-  if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
-    return true;
-
-  return false;
+  return MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm();
 }
 
 bool HexagonInstrInfo::isConstExtended(const MachineInstr *MI) const {
   const uint64_t F = MI->getDesc().TSFlags;
   unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
   if (isExtended) // Instruction must be extended.
     return true;
 
case HexagonII::BaseImmOffset :
       // Load/store with base+offset addressing mode can be converted into
       // base+register offset addressing mode. However left shift operand should
       // be set to 0.
       NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
       break;
     default:
       return false;
     }
-    if (NonExtOpcode < 0)
-      return false;
-    return true;
+    return NonExtOpcode >= 0;
   }
   return false;
 }
 
 // Returns opcode of the non-extended equivalent instruction.
 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
 
   // Check if the instruction has a register form that uses register in place

lib/Target/Hexagon/HexagonMachineScheduler.cpp

 /// can dispatch per cycle.
 ///
 /// TODO: Also check whether the SU must start a new group.
 bool ConvergingVLIWScheduler::VLIWSchedBoundary::checkHazard(SUnit *SU) {
   if (HazardRec->isEnabled())
     return HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard;
 
   unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
-  if (IssueCount + uops > SchedModel->getIssueWidth())
-    return true;
-
-  return false;
+  return IssueCount + uops > SchedModel->getIssueWidth();
 }
 
 void ConvergingVLIWScheduler::VLIWSchedBoundary::releaseNode(SUnit *SU,
                                                      unsigned ReadyCycle) {
   if (ReadyCycle < MinReadyCycle)
     MinReadyCycle = ReadyCycle;
 
   // Check for interlocks first. For the purpose of other heuristics, an

lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
   return isCondInst(MI) || QII->mayBeNewStore(MI);
 }
 
 bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
   const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
   const MCInstrDesc& TID = MI->getDesc();
                                     // bug 5670: until that is fixed,
                                     // this portion is disabled.
-  if (   TID.isConditionalBranch()  // && !IsRegisterJump(MI)) ||
+  return TID.isConditionalBranch()  // && !IsRegisterJump(MI)) ||
       || QII->isConditionalTransfer(MI)
       || QII->isConditionalALU32(MI)
       || QII->isConditionalLoad(MI)
-      || QII->isConditionalStore(MI)) {
-    return true;
-  }
-  return false;
+      || QII->isConditionalStore(MI);
 }
 
 
 // Promote an instructiont to its .new form.
 // At this time, we have already made a call to CanPromoteToDotNew
 // and made sure that it can *indeed* be promoted.
 bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
                         SDep::Kind DepType, MachineBasicBlock::iterator &MII,