Fix several issue in arm single stepping and stack unwinding

[tberghammer]

Summary

Fix several issue in arm single stepping and stack unwinding

• Improve instruction emulation for the following instructions: ADD, B, CMP, LDR, LDRB, SUB, TB
• Fix prologue restoration code with calculating correct offset for the new rows and restoring saved register values also next to the CFA

[clayborg]

Looks good.

[tberghammer]

Abandon because of an upcoming patch fixing this issue and several other issue also

source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp

#endif
 
     if (ConditionPassed(opcode))
     {
         const addr_t sp = ReadCoreReg (SP_REG, &success);
         if (!success)
             return false;
         uint32_t imm32; // the immediate operand
         uint32_t d;
-        //bool setflags = false; // Add this back if/when support eEncodingT3 eEncodingA1
+        bool setflags;
         switch (encoding) 
         {
             case eEncodingT1:
                 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm8:'00', 32);
                 d = Bits32 (opcode, 10, 8);
                 imm32 = (Bits32 (opcode, 7, 0) << 2);
-                  
+                setflags = false;
                 break;
                   
             case eEncodingT2:
                 // d = 13; setflags = FALSE; imm32 = ZeroExtend(imm7:'00', 32);
                 d = 13;
-                imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32)
-                  
+                imm32 = ThumbImm7Scaled (opcode); // imm32 = ZeroExtend(imm7:'00', 32)
+                setflags = false;
+                break;
+
+            case eEncodingT3:
+                // d = UInt(Rd); setflags = (S == "1"); imm32 = ThumbExpandImm(i:imm3:imm8);
+                d = Bits32 (opcode, 11, 8);
+                imm32 = ThumbExpandImm (opcode);
+                setflags = Bit32 (opcode, 20);
+
+                // if Rd == "1111" && S == "1" then SEE CMN (immediate);
+                if (d == 15 && setflags == 1)
+                    return false; // CMN (immediate) not yet supported
+
+                // if d == 15 && S == "0" then UNPREDICTABLE;
+                if (d == 15 && setflags == 0)
+                    return false;
                 break;
                   
             default:
                 return false;
         }
-        addr_t sp_offset = imm32;
-        addr_t addr = sp + sp_offset; // the adjusted stack pointer value
+        // (result, carry, overflow) = AddWithCarry(R[n], imm32, '0'); 
+        AddWithCarryResult res = AddWithCarry (sp, imm32, 0);
         
         EmulateInstruction::Context context;
         if (d == 13)
             context.type = EmulateInstruction::eContextAdjustStackPointer;
         else
             context.type = EmulateInstruction::eContextRegisterPlusOffset;
 
         RegisterInfo sp_reg;
         GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
-        context.SetRegisterPlusOffset (sp_reg, sp_offset);
+        context.SetRegisterPlusOffset (sp_reg, res.result - sp);
     
         if (d == 15)
         {
-            if (!ALUWritePC (context, addr))
+            if (!ALUWritePC (context, res.result))
                 return false;
         }
         else
         {
-            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, addr))
-                return false;
-            
-            // Add this back if/when support eEncodingT3 eEncodingA1
-            //if (setflags)
-            //{
-            //    APSR.N = result<31>;
-            //    APSR.Z = IsZeroBit(result);
-            //    APSR.C = carry;
-            //    APSR.V = overflow;
-            //}
+            //R[d] = result; 
+            //if setflags then
+                //APSR.N = result<31>;  
+                //APSR.Z = IsZeroBit(result); 
+                //APSR.C = carry;  
+                //APSR.V = overflow;
+            if (!WriteCoreRegOptionalFlags (context, res.result, d, setflags, res.carry_out, res.overflow))
+                return false;
         }
     }
     return true;
 }
 
 // An add operation to adjust the SP.
 // ADD (SP plus register)
 bool
if (ConditionPassed(opcode))
         switch (encoding) {
         case eEncodingT1:
             // The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
             imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1);
             target = pc + imm32;
             context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
             break;
         case eEncodingT2:
-            imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0));
+            imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0) << 1);
             target = pc + imm32;
             context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
             break;
         case eEncodingT3:
             // The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
             {
+            if (Bits32(opcode, 25, 23) == 7)
+                return false; // See Branches and miscellaneous control on page A6-235.
+
             uint32_t S = Bit32(opcode, 26);
             uint32_t imm6 = Bits32(opcode, 21, 16);
             uint32_t J1 = Bit32(opcode, 13);
             uint32_t J2 = Bit32(opcode, 11);
             uint32_t imm11 = Bits32(opcode, 10, 0);
             uint32_t imm21 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1);
             imm32 = llvm::SignExtend32<21>(imm21);
             target = pc + imm32;
if is_tbh then
         halfwords = UInt(MemU[R[n]+LSL(R[m],1), 2]);
     else
         halfwords = UInt(MemU[R[n]+R[m], 1]);
     BranchWritePC(PC + 2*halfwords);
 #endif
 
     bool success = false;
 
+    if (ConditionPassed(opcode))
+    {
         uint32_t Rn;     // the base register which contains the address of the table of branch lengths
         uint32_t Rm;     // the index register which contains an integer pointing to a byte/halfword in the table
         bool is_tbh;     // true if table branch halfword
         switch (encoding) {
         case eEncodingT1:
             Rn = Bits32(opcode, 19, 16);
             Rm = Bits32(opcode, 3, 0);
             is_tbh = BitIsSet(opcode, 4);
             if (Rn == 13 || BadReg(Rm))
                 return false;
             if (InITBlock() && !LastInITBlock())
                 return false;
             break;
         default:
             return false;
         }
 
         // Read the address of the table from the operand register Rn.
         // The PC can be used, in which case the table immediately follows this instruction.
-    uint32_t base = ReadCoreReg(Rm, &success);
+        uint32_t base = ReadCoreReg(Rn, &success);
         if (!success)
             return false;
 
         // the table index
         uint32_t index = ReadCoreReg(Rm, &success);
         if (!success)
             return false;
 
         // the offsetted table address
         addr_t addr = base + (is_tbh ? index*2 : index);
 
         // PC-relative offset to branch forward
         EmulateInstruction::Context context;
         context.type = EmulateInstruction::eContextTableBranchReadMemory;
         uint32_t offset = MemURead(context, addr, is_tbh ? 2 : 1, 0, &success) * 2;
         if (!success)
             return false;
 
         const uint32_t pc = ReadCoreReg(PC_REG, &success);
         if (!success)
             return false;
 
         // target address
         addr_t target = pc + offset;
         context.type = EmulateInstruction::eContextRelativeBranchImmediate;
         context.SetISAAndImmediateSigned (eModeThumb, 4 + offset);
 
         if (!BranchWritePC(context, target))
             return false;
+    }
 
     return true;
 }
 
 // This instruction adds an immediate value to a register value, and writes the result to the destination register.  
 // It can optionally update the condition flags based on the result.
 bool
 EmulateInstructionARM::EmulateADDImmThumb (const uint32_t opcode, const ARMEncoding encoding)
if (ConditionPassed(opcode))
                 n = Bits32 (opcode, 10, 8);
                 setflags = !InITBlock();
                 imm32 = Bits32 (opcode, 7, 0);
                 
                 break;
                 
             case eEncodingT3:
                 // if Rd == '1111' && S == '1' then SEE CMN (immediate); 
-                // if Rn == '1101' then SEE ADD (SP plus immediate); 
                 // d = UInt(Rd); n = UInt(Rn); setflags = (S == '1'); imm32 = ThumbExpandImm(i:imm3:imm8); 
                 d = Bits32 (opcode, 11, 8);
                 n = Bits32 (opcode, 19, 16);
                 setflags = BitIsSet (opcode, 20);
                 imm32 = ThumbExpandImm_C (opcode, APSR_C, carry_out);
-                
+                // if Rn == '1101' then SEE ADD (SP plus immediate); 
+                if (n == 13)
+                    return EmulateADDSPImm(opcode, eEncodingT3);
+                
                 // if BadReg(d) || n == 15 then UNPREDICTABLE;
                 if (BadReg (d) || (n == 15))
                     return false;
                 
                 break;
                 
             case eEncodingT4:
             {
                 // if Rn == '1111' then SEE ADR; 
-                // if Rn == '1101' then SEE ADD (SP plus immediate); 
                 // d = UInt(Rd); n = UInt(Rn); setflags = FALSE; imm32 = ZeroExtend(i:imm3:imm8, 32); 
                 d = Bits32 (opcode, 11, 8);
                 n = Bits32 (opcode, 19, 16);
                 setflags = false;
                 uint32_t i = Bit32 (opcode, 26);
                 uint32_t imm3 = Bits32 (opcode, 14, 12);
                 uint32_t imm8 = Bits32 (opcode, 7, 0);
                 imm32 = (i << 11) | (imm3 << 8) | imm8;
                 
+                // if Rn == '1101' then SEE ADD (SP plus immediate); 
+                if (n == 13)
+                    return EmulateADDSPImm(opcode, eEncodingT4);
+
                 // if BadReg(d) then UNPREDICTABLE;
                 if (BadReg (d))
                     return false;
                     
                 break;
             }   
             default:
                 return false;
case eEncodingT2:
         Rm = Bits32(opcode, 6, 3);
         shift_t = SRType_LSL;
         shift_n = 0;
         if (Rn < 8 && Rm < 8)
             return false;
         if (Rn == 15 || Rm == 15)
             return false;
         break;
+    case eEncodingT3:
+        Rn = Bits32(opcode, 19, 16);
+        Rm = Bits32(opcode, 3, 0);
+        shift_n = DecodeImmShiftThumb(opcode, shift_t);
+        if (Rn == 15 || BadReg(Rm))
+            return false;
+        break;
     case eEncodingA1:
         Rn = Bits32(opcode, 19, 16);
         Rm = Bits32(opcode, 3, 0);
         shift_n = DecodeImmShiftARM(opcode, shift_t);
         break;
     default:
         return false;
     }
if (ConditionPassed(opcode))
 
         address = (index ? offset_addr : base);
 
         RegisterInfo base_reg;
         GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rn, base_reg);
         if (wback)
         {
             EmulateInstruction::Context ctx;
+            if (Rn == 13)
+            {
+                ctx.type = eContextAdjustStackPointer;
+                ctx.SetImmediateSigned((int32_t) (offset_addr - base));
+            }
+            else if (Rn == GetFramePointerRegisterNumber())
+            {
+                ctx.type = eContextSetFramePointer;
+                ctx.SetRegisterPlusOffset (base_reg, (int32_t) (offset_addr - base));
+            }
+            else
+            {
                 ctx.type = EmulateInstruction::eContextAdjustBaseRegister;
                 ctx.SetRegisterPlusOffset (base_reg, (int32_t) (offset_addr - base));
+            }
+            
 
             if (!WriteRegisterUnsigned (ctx, eRegisterKindDWARF, dwarf_r0 + Rn, offset_addr))
                 return false;
         }
 
         // Prepare to write to the Rt register.
         EmulateInstruction::Context context;
         context.type = EmulateInstruction::eContextRegisterLoad;
if (ConditionPassed(opcode))
                 // index = TRUE; add = TRUE; wback = FALSE;
                 index = true;
                 add = true;
                 wback= false;
                   
                 break;
                   
             case eEncodingT2:
-                // if Rt == '1111' then SEE PLD; 
-                // if Rn == '1111' then SEE LDRB (literal); 
                 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); 
                 t = Bits32 (opcode, 15, 12);
                 n = Bits32 (opcode, 19, 16);
                 imm32 = Bits32 (opcode, 11, 0);
                   
                 // index = TRUE; add = TRUE; wback = FALSE; 
                 index = true;
                 add = true;
                 wback = false;
-                  
+                // if Rt == '1111' then SEE PLD; 
+                if (t == 15)
+                    return false; // PLD is not implemented yet
+
+                // if Rn == '1111' then SEE LDRB (literal); 
+                if (n == 15)
+                    return EmulateLDRBLiteral(opcode, eEncodingT1);
+
                 // if t == 13 then UNPREDICTABLE;
                 if (t == 13)
                     return false;
                   
                 break;
                   
             case eEncodingT3:
-                // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD; 
-                // if Rn == '1111' then SEE LDRB (literal); 
                 // if P == '1' && U == '1' && W == '0' then SEE LDRBT; 
                 // if P == '0' && W == '0' then UNDEFINED;
                 if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
                     return false;
                   
-                  // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
                 t = Bits32 (opcode, 15, 12);
                 n = Bits32 (opcode, 19, 16);
                 imm32 = Bits32 (opcode, 7, 0);
                   
                 // index = (P == '1'); add = (U == '1'); wback = (W == '1'); 
                 index = BitIsSet (opcode, 10);
                 add = BitIsSet (opcode, 9);
                 wback = BitIsSet (opcode, 8);
-                  
+                // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD; 
+                if (t == 15)
+                    return false; // PLD is not implemented yet
+
+                // if Rn == '1111' then SEE LDRB (literal); 
+                if (n == 15)
+                    return EmulateLDRBLiteral(opcode, eEncodingT1);
+
                 // if BadReg(t) || (wback && n == t) then UNPREDICTABLE;
                 if (BadReg (t) || (wback && (n == t)))
                     return false;
                   
                 break;
                   
             default:
                 return false;
#endif
     if (ConditionPassed(opcode))
     {
         uint32_t t;
         uint32_t imm32;
         bool add;
         switch (encoding)
         {
             case eEncodingT1:
-                // if Rt == '1111' then SEE PLD; 
                 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1'); 
                 t = Bits32 (opcode, 15, 12);
                 imm32 = Bits32 (opcode, 11, 0);
                 add = BitIsSet (opcode, 23);
-                  
+                // if Rt == '1111' then SEE PLD; 
+                if (t == 15)
+                    return false; // PLD is not implemented yet
+                  
                 // if t == 13 then UNPREDICTABLE;
                 if (t == 13)
                     return false;
                   
                 break;
                   
             case eEncodingA1:
                 // t == UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1'); 
if (ConditionPassed(opcode))
                 wback = false;
                   
                 // (shift_t, shift_n) = (SRType_LSL, 0);
                 shift_t = SRType_LSL;
                 shift_n = 0;
                 break;
                   
             case eEncodingT2:
-                // if Rt == '1111' then SEE PLD; 
-                // if Rn == '1111' then SEE LDRB (literal); 
                 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); 
                 t = Bits32 (opcode, 15, 12);
                 n = Bits32 (opcode, 19, 16);
                 m = Bits32 (opcode, 3, 0);
                   
                 // index = TRUE; add = TRUE; wback = FALSE; 
                 index = true;
                 add = true;
                 wback = false;
                   
                 // (shift_t, shift_n) = (SRType_LSL, UInt(imm2)); 
                 shift_t = SRType_LSL;
                 shift_n = Bits32 (opcode, 5, 4);
-                  
+                // if Rt == '1111' then SEE PLD; 
+                if (t == 15)
+                    return false; // PLD is not implemented yet
+
+                // if Rn == '1111' then SEE LDRB (literal); 
+                if (n == 15)
+                    return EmulateLDRBLiteral(opcode, eEncodingT1);
+                  
                 // if t == 13 || BadReg(m) then UNPREDICTABLE;
                 if ((t == 13) || BadReg (m))
                     return false;
                 break;
                   
             case eEncodingA1:
             {
                 // if P == '0' && W == '1' then SEE LDRBT; 
if (ConditionPassed(opcode))
                   
                 // (shift_t, shift_n) = (SRType_LSL, 0);
                 shift_t = SRType_LSL;
                 shift_n = 0;
                   
                 break;
                   
             case eEncodingT2:
-                // if Rd == ﾔ1111ﾕ && S == ﾔ1ﾕ then SEE CMP (register);
-                // if Rn == ﾔ1101ﾕ then SEE SUB (SP minus register);
-                // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == ﾔ1ﾕ);
+                // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S =="1");
                 d = Bits32 (opcode, 11, 8);
                 n = Bits32 (opcode, 19, 16);
                 m = Bits32 (opcode, 3, 0);
                 setflags = BitIsSet (opcode, 20);
-                  
+                // if Rd == "1111" && S == "1" then SEE CMP (register);
+                if (d == 15 && setflags == 1)
+                    return EmulateCMPImm (opcode, eEncodingT3);
+                  
+                // if Rn == "1101" then SEE SUB (SP minus register);
+                if (n == 13)
+                    return EmulateSUBSPReg (opcode, eEncodingT1);
+
                 // (shift_t, shift_n) = DecodeImmShift(type, imm3:imm2);
                 shift_n = DecodeImmShiftThumb (opcode, shift_t);
                   
                 // if d == 13 || (d == 15 && S == '0') || n == 15 || BadReg(m) then UNPREDICTABLE;
                 if ((d == 13) || ((d == 15) && BitIsClear (opcode, 20)) || (n == 15) || BadReg (m))
                     return false;
                   
                 break;
g_thumb_opcodes[] =
         { 0xfff08f00, 0xeb100f00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm> {,<shift>}"},
         // cmp (immediate)
         { 0xfffff800, 0x00002800, ARMvAll,       eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMPImm, "cmp<c> <Rn>, #imm8"},
         { 0xfbf08f00, 0xf1b00f00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMPImm, "cmp<c>.w <Rn>, #<const>"},
         // cmp (register) (Rn and Rm both from r0-r7)
         { 0xffffffc0, 0x00004280, ARMvAll,       eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm>"},
         // cmp (register) (Rn and Rm not both from r0-r7)
         { 0xffffff00, 0x00004500, ARMvAll,       eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm>"},
+        { 0xfff08f00, 0xebb00f00, ARMvAll,       eEncodingT3, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMPReg, "cmp<c>.w <Rn>, <Rm> {, <shift>}"},
         // asr (immediate)
         { 0xfffff800, 0x00001000, ARMvAll,       eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateASRImm, "asrs|asr<c> <Rd>, <Rm>, #imm"},
         { 0xffef8030, 0xea4f0020, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRImm, "asr{s}<c>.w <Rd>, <Rm>, #imm"},
         // asr (register)
         { 0xffffffc0, 0x00004100, ARMvAll,       eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateASRReg, "asrs|asr<c> <Rdn>, <Rm>"},
         { 0xffe0f0f0, 0xfa40f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRReg, "asr{s}<c>.w <Rd>, <Rn>, <Rm>"},
         // lsl (immediate)
         { 0xfffff800, 0x00000000, ARMvAll,       eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLSLImm, "lsls|lsl<c> <Rd>, <Rm>, #imm"},

source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp

if (range.GetByteSize() > 0 &&
                 // Make a copy of the current instruction Row and save it in m_curr_row
                 // so we can add updates as we process the instructions.  
                 UnwindPlan::RowSP last_row = unwind_plan.GetLastRow();
                 UnwindPlan::Row *newrow = new UnwindPlan::Row;
                 if (last_row.get())
                     *newrow = *last_row.get();
                 m_curr_row.reset(newrow);
 
-                // Once we've seen the initial prologue instructions complete, save a
-                // copy of the CFI at that point into prologue_completed_row for possible
-                // use later.
-                int instructions_since_last_prologue_insn = 0;     // # of insns since last CFI was update
-
-                bool reinstate_prologue_next_instruction = false;  // Next iteration, re-install the prologue row of CFI
-
-                bool last_instruction_restored_return_addr_reg = false;  // re-install the prologue row of CFI if the next instruction is a branch immediate
-
-                bool return_address_register_has_been_saved = false; // if we've seen the ra register get saved yet
-
-                UnwindPlan::RowSP prologue_completed_row;          // copy of prologue row of CFI
+                // Once we've seen the initial prologue instructions complete,
+                // save a copy of the CFI and the register values at that
+                // point into prologue_completed_row and into
+                // prologue_completed_register_values for possible use later.
+                int instructions_since_last_prologue_insn = 0;          // # of insns since last CFI was update
+                bool reinstate_prologue_next_instruction = false;       // Next iteration, re-install the prologue row of CFI
+                bool last_instruction_restored_return_addr_reg = false; // re-install the prologue row of CFI if the next instruction is a branch immediate
+                bool return_address_register_has_been_saved = false;    // if we've seen the ra register get saved yet
+                UnwindPlan::RowSP prologue_completed_row;               // copy of prologue row of CFI
+                RegisterValueMap prologue_completed_register_values;    // copy of register values at the end of the prologue
 
                 // cache the pc register number (in whatever register numbering this UnwindPlan uses) for
                 // quick reference during instruction parsing.
                 uint32_t pc_reg_num = LLDB_INVALID_REGNUM;
                 RegisterInfo pc_reg_info;
                 if (m_inst_emulator_ap->GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, pc_reg_info))
                     pc_reg_num = pc_reg_info.kinds[unwind_plan.GetRegisterKind()];
                 else
if (range.GetByteSize() > 0 &&
                         if (reinstate_prologue_next_instruction
                             || (m_curr_insn_is_branch_immediate && last_instruction_restored_return_addr_reg))
                         {
                             if (log && log->GetVerbose())
                                 log->Printf("UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly -- Reinstating prologue instruction set");
                             UnwindPlan::Row *newrow = new UnwindPlan::Row;
                             *newrow = *prologue_completed_row.get();
                             m_curr_row.reset(newrow);
+                            if (reinstate_prologue_next_instruction)
                                 m_curr_row->SetOffset (inst->GetAddress().GetFileAddress() - base_addr);
+                            else
+                                m_curr_row->SetOffset (inst->GetAddress().GetFileAddress() + inst->GetOpcode().GetByteSize() - base_addr);
                             unwind_plan.AppendRow(m_curr_row);
 
                             newrow = new UnwindPlan::Row;
                             *newrow = *m_curr_row.get();
                             m_curr_row.reset(newrow);
+                            m_register_values = prologue_completed_register_values;
+
 
                             reinstate_prologue_next_instruction = false;
                             last_instruction_restored_return_addr_reg = false; 
                             m_curr_insn_is_branch_immediate = false;
                         }
 
                         // clear both of these if either one wasn't set
                         if (last_instruction_restored_return_addr_reg)
if (range.GetByteSize() > 0 &&
 
                         // Stop updating the prologue instructions if we've seen 8 non-prologue instructions
                         // in a row.
                         if (instructions_since_last_prologue_insn++ < 8)
                         {
                             UnwindPlan::Row *newrow = new UnwindPlan::Row;
                             *newrow = *m_curr_row.get();
                             prologue_completed_row.reset(newrow);
+                            prologue_completed_register_values = m_register_values;
                             if (log && log->GetVerbose())
                                 log->Printf("UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly -- saving a copy of the current row as the prologue row.");
                         }
                     }
                 }
             }
             // FIXME: The DisassemblerLLVMC has a reference cycle and won't go away if it has any active instructions.
             // I'll fix that but for now, just clear the list and it will go away nicely.
//            }
                     m_curr_row->SetRegisterLocationToSame (reg_num, must_replace);
                     m_curr_row_modified = true;
                     m_curr_insn_part_of_epilogue = true;
                 }
             }
             break;
 
         case EmulateInstruction::eContextSetFramePointer:
-            if (!m_fp_is_cfa)
             {
                 m_fp_is_cfa = true;
                 m_cfa_reg_info = *reg_info;
                 const uint32_t cfa_reg_num = reg_info->kinds[m_unwind_plan_ptr->GetRegisterKind()];
                 assert (cfa_reg_num != LLDB_INVALID_REGNUM);
                 m_curr_row->GetCFAValue().SetIsRegisterPlusOffset(cfa_reg_num, m_initial_sp -
                         reg_value.GetAsUInt64());
                 m_curr_row_modified = true;