This implements the assemble and disassemble support of RISCV Vector extension Zvlsseg instructions, base on the 0.9 spec version.
Details
Diff Detail
- Repository
- rG LLVM Github Monorepo
Event Timeline
| llvm/lib/Target/RISCV/RISCV.td | ||
|---|---|---|
| 152 | def FeatureStdExtZvlsseg
: SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true",
"'Zvlsseg' (Vector segment load/store instructions)",
[FeatureStdExtV]>; | |
| llvm/lib/Target/RISCV/RISCVInstrInfoV.td | ||
| 131 | RVInstVLU<nf, width.Value{3}, MOPLDUnitStride, lumop, width.Value{2-0} | |
| 137 | RVInstVLS<nf, width.Value{3}, MOPLDStrided, width.Value{2-0} | |
| 145 | RVInstVLX<nf, width.Value{3}, MOPLDIndexed, width.Value{2-0} | |
| 180 | Remove sumop. | |
| 182 | RVInstVSU<nf, width.Value{3}, MOPSTUnitStride, SUMOPUnitStride, width.Value{2-0}, | |
| 188 | RVInstVSS<nf, width.Value{3}, MOPSTStrided, width.Value{2-0}, (outs), | |
| 193 | Remove mop | |
| 194 | RVInstVSX<nf, width.Value{3}, MOPSTIndexedOrder, width.Value{2-0}, (outs), | |
| 956 | HasStdExtZvlsseg is enough. | |
| 976 | Remove SUMOPUnitStride. | |
| 1014 | Remove MOPSTIndexedOrder. | |
| llvm/test/MC/RISCV/rvv/zvlsseg.s | ||
| 2 | +experimental-zvlsseg is enough. | |
| 15 | CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions) | |
def FeatureStdExtZvlsseg : SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true", "'Zvlsseg' (Vector segment load/store instructions)", [FeatureStdExtV]>;