Vector bitwise selects are matched by pseudo VBSP instruction
and expanded to VBSL/VBIT/VBIF after register allocation
depend on operands registers to minimize extra copies.
This looks nice and clean, from what I can tell.
This wasn't true, I guess? Can you make sure we have tests for vbif and vbit encodings, and they look alright. Something in test/MC/ARM and test/MC/Disassembler/ARM.