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[ARM] VBIT/VBIF support added.
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Authored by ilinpv on Tue, Jul 14, 4:31 PM.

Details

Summary

Vector bitwise selects are matched by pseudo VBSP instruction
and expanded to VBSL/VBIT/VBIF after register allocation
depend on operands registers to minimize extra copies.

Diff Detail

Event Timeline

ilinpv created this revision.Tue, Jul 14, 4:31 PM

This looks nice and clean, from what I can tell.

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
1868

NewOpc

llvm/lib/Target/ARM/ARMInstrNEON.td
5512

This wasn't true, I guess? Can you make sure we have tests for vbif and vbit encodings, and they look alright. Something in test/MC/ARM and test/MC/Disassembler/ARM.

ilinpv updated this revision to Diff 278332.Wed, Jul 15, 5:10 PM

vbit/vbif encoding tests added.

ilinpv marked 2 inline comments as done.Wed, Jul 15, 5:11 PM
dmgreen accepted this revision.Thu, Jul 16, 12:38 AM

LGTM. Thanks.

This revision is now accepted and ready to land.Thu, Jul 16, 12:38 AM