[ARM] VBIT/VBIF support added.

[ilinpv]

Summary

Vector bitwise selects are matched by pseudo VBSP instruction
and expanded to VBSL/VBIT/VBIF after register allocation
depend on operands registers to minimize extra copies.

[dmgreen]

This looks nice and clean, from what I can tell.

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

1868

NewOpc

llvm/lib/Target/ARM/ARMInstrNEON.td

5512

This wasn't true, I guess? Can you make sure we have tests for vbif and vbit encodings, and they look alright. Something in test/MC/ARM and test/MC/Disassembler/ARM.

[ilinpv]

vbit/vbif encoding tests added.

[dmgreen]

LGTM. Thanks.

[ilinpv]

The patch landed b9a6fb64281b6836e565ee39fb0d543bf184fd88

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator MBBI,
                                MachineBasicBlock::iterator &NextMBBI) {
   MachineInstr &MI = *MBBI;
   unsigned Opcode = MI.getOpcode();
   switch (Opcode) {
     default:
       return false;
 
+    case ARM::VBSPd:
+    case ARM::VBSPq: {
+      Register DstReg = MI.getOperand(0).getReg();
+      if (DstReg == MI.getOperand(3).getReg()) {
+        // Expand to VBIT
+        unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq;
+        BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
+            .add(MI.getOperand(0))
+            .add(MI.getOperand(3))
+            .add(MI.getOperand(2))
+            .add(MI.getOperand(1))
+            .addImm(MI.getOperand(4).getImm())
+            .add(MI.getOperand(5));
+      } else if (DstReg == MI.getOperand(2).getReg()) {
+        // Expand to VBIF
+        unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq;
+        BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
+            .add(MI.getOperand(0))
+            .add(MI.getOperand(2))
+            .add(MI.getOperand(3))
+            .add(MI.getOperand(1))
+            .addImm(MI.getOperand(4).getImm())
+            .add(MI.getOperand(5));
+      } else {
+        // Expand to VBSL
+        unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq;
+        if (DstReg == MI.getOperand(1).getReg()) {
+          BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
+              .add(MI.getOperand(0))
+              .add(MI.getOperand(1))
+              .add(MI.getOperand(2))
+              .add(MI.getOperand(3))
+              .addImm(MI.getOperand(4).getImm())
+              .add(MI.getOperand(5));
+        } else {
+          // Use move to satisfy constraints
+          unsigned MoveOpc = Opcode == ARM::VBSPd ? ARM::VORRd : ARM::VORRq;
+          BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MoveOpc))
+              .addReg(DstReg,
+                      RegState::Define |
+                          getRenamableRegState(MI.getOperand(0).isRenamable()))
+              .add(MI.getOperand(1))
+              .add(MI.getOperand(1))
+              .addImm(MI.getOperand(4).getImm())
+              .add(MI.getOperand(5));
+          BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
+              .add(MI.getOperand(0))
+              .addReg(DstReg,
+                      RegState::Kill |
+                          getRenamableRegState(MI.getOperand(0).isRenamable()))
+              .add(MI.getOperand(2))
+              .add(MI.getOperand(3))
+              .addImm(MI.getOperand(4).getImm())
+              .add(MI.getOperand(5));
+        }
+      }
+      MI.eraseFromParent();
+      return true;
+    }
+
     case ARM::TCRETURNdi:
     case ARM::TCRETURNri: {
       MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
       assert(MBBI->isReturn() &&
              "Can only insert epilog into returning blocks");
       unsigned RetOpcode = MBBI->getOpcode();
       DebugLoc dl = MBBI->getDebugLoc();
       const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(

llvm/lib/Target/ARM/ARMISelLowering.h

enum NodeType : unsigned {
       // Bit-field insert
       BFI,
 
       // Vector OR with immediate
       VORRIMM,
       // Vector AND with NOT of immediate
       VBICIMM,
 
-      // Vector bitwise select
-      VBSL,
+      // Pseudo vector bitwise select
+      VBSP,
 
       // Pseudo-instruction representing a memory copy using ldm/stm
       // instructions.
       MEMCPY,
 
       // V8.1MMainline condition select
       CSINV, // Conditional select invert.
       CSNEG, // Conditional select negate.

llvm/lib/Target/ARM/ARMISelLowering.cpp

const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case ARMISD::QADD16b:       return "ARMISD::QADD16b";
   case ARMISD::QSUB16b:       return "ARMISD::QSUB16b";
   case ARMISD::QADD8b:        return "ARMISD::QADD8b";
   case ARMISD::QSUB8b:        return "ARMISD::QSUB8b";
   case ARMISD::BUILD_VECTOR:  return "ARMISD::BUILD_VECTOR";
   case ARMISD::BFI:           return "ARMISD::BFI";
   case ARMISD::VORRIMM:       return "ARMISD::VORRIMM";
   case ARMISD::VBICIMM:       return "ARMISD::VBICIMM";
-  case ARMISD::VBSL:          return "ARMISD::VBSL";
+  case ARMISD::VBSP:          return "ARMISD::VBSP";
   case ARMISD::MEMCPY:        return "ARMISD::MEMCPY";
   case ARMISD::VLD1DUP:       return "ARMISD::VLD1DUP";
   case ARMISD::VLD2DUP:       return "ARMISD::VLD2DUP";
   case ARMISD::VLD3DUP:       return "ARMISD::VLD3DUP";
   case ARMISD::VLD4DUP:       return "ARMISD::VLD4DUP";
   case ARMISD::VLD1_UPD:      return "ARMISD::VLD1_UPD";
   case ARMISD::VLD2_UPD:      return "ARMISD::VLD2_UPD";
   case ARMISD::VLD3_UPD:      return "ARMISD::VLD3_UPD";
if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
             // Ensure that the bit width of the constants are the same and that
             // the splat arguments are logical inverses as per the pattern we
             // are trying to simplify.
             if (SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
                 SplatBits0 == ~SplatBits1) {
                 // Canonicalize the vector type to make instruction selection
                 // simpler.
                 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
-                SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
+                SDValue Result = DAG.getNode(ARMISD::VBSP, dl, CanonicalVT,
                                              N0->getOperand(1),
                                              N0->getOperand(0),
                                              N1->getOperand(0));
                 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
             }
         }
     }
   }

llvm/lib/Target/ARM/ARMInstrNEON.td

 
 def NEONvqrshrnsImm  : SDNode<"ARMISD::VQRSHRNsIMM", SDTARMVSHXIMM>;
 def NEONvqrshrnuImm  : SDNode<"ARMISD::VQRSHRNuIMM", SDTARMVSHXIMM>;
 def NEONvqrshrnsuImm : SDNode<"ARMISD::VQRSHRNsuIMM", SDTARMVSHXIMM>;
 
 def NEONvsliImm      : SDNode<"ARMISD::VSLIIMM", SDTARMVSHINSIMM>;
 def NEONvsriImm      : SDNode<"ARMISD::VSRIIMM", SDTARMVSHINSIMM>;
 
-def NEONvbsl      : SDNode<"ARMISD::VBSL",
+def NEONvbsp      : SDNode<"ARMISD::VBSP",
                            SDTypeProfile<1, 3, [SDTCisVec<0>,
                                                 SDTCisSameAs<0, 1>,
                                                 SDTCisSameAs<0, 2>,
                                                 SDTCisSameAs<0, 3>]>>;
 
 def SDTARMVEXT    : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
                                          SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
 def NEONvext      : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
def : Pat<(v8i16 (saddsat
             (v8i16 (VQRDMLAHslv8i16 (v8i16 QPR:$src1),
                                     (v8i16 QPR:$src2),
                                     (v4i16 (EXTRACT_SUBREG
                                              QPR:$src3,
                                              (DSubReg_i16_reg imm:$lane))),
                                     (SubReg_i16_lane imm:$lane)))>;
   def : Pat<(v4i32 (saddsat
                      (v4i32 QPR:$src1),
-                     (v4i32 (int_arm_neon_vqrdmulh 
+                     (v4i32 (int_arm_neon_vqrdmulh
                               (v4i32 QPR:$src2),
-                              (v4i32 (ARMvduplane (v4i32 QPR:$src3), 
+                              (v4i32 (ARMvduplane (v4i32 QPR:$src3),
                                                    imm:$lane)))))),
             (v4i32 (VQRDMLAHslv4i32 (v4i32 QPR:$src1),
                                     (v4i32 QPR:$src2),
                                     (v2i32 (EXTRACT_SUBREG
                                              QPR:$src3,
                                              (DSubReg_i32_reg imm:$lane))),
                                     (SubReg_i32_lane imm:$lane)))>;
 
def : Pat<(v4i16 (ssubsat
                                                    imm:$lane)))))),
             (v4i16 (VQRDMLSHslv4i16 DPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane))>;
   def : Pat<(v2i32 (ssubsat
                      (v2i32 DPR:$src1),
                      (v2i32 (int_arm_neon_vqrdmulh
                               (v2i32 DPR:$Vn),
                               (v2i32 (ARMvduplane (v2i32 DPR_VFP2:$Vm),
                                                    imm:$lane)))))),
-            (v2i32 (VQRDMLSHslv2i32 DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, 
+            (v2i32 (VQRDMLSHslv2i32 DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm,
                                     imm:$lane))>;
   def : Pat<(v8i16 (ssubsat
                      (v8i16 QPR:$src1),
                      (v8i16 (int_arm_neon_vqrdmulh
                               (v8i16 QPR:$src2),
-                              (v8i16 (ARMvduplane (v8i16 QPR:$src3), 
+                              (v8i16 (ARMvduplane (v8i16 QPR:$src3),
                                                    imm:$lane)))))),
             (v8i16 (VQRDMLSHslv8i16 (v8i16 QPR:$src1),
                                     (v8i16 QPR:$src2),
-                                    (v4i16 (EXTRACT_SUBREG 
+                                    (v4i16 (EXTRACT_SUBREG
                                              QPR:$src3,
                                              (DSubReg_i16_reg imm:$lane))),
                                     (SubReg_i16_lane imm:$lane)))>;
   def : Pat<(v4i32 (ssubsat
                      (v4i32 QPR:$src1),
                      (v4i32 (int_arm_neon_vqrdmulh
                               (v4i32 QPR:$src2),
                               (v4i32 (ARMvduplane (v4i32 QPR:$src3),
                                                     imm:$lane)))))),
             (v4i32 (VQRDMLSHslv4i32 (v4i32 QPR:$src1),
                                     (v4i32 QPR:$src2),
-                                    (v2i32 (EXTRACT_SUBREG 
+                                    (v2i32 (EXTRACT_SUBREG
                                              QPR:$src3,
                                              (DSubReg_i32_reg imm:$lane))),
                                     (SubReg_i32_lane imm:$lane)))>;
 }
 //   VQDMLAL  : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
 defm VQDMLAL  : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
                             "vqdmlal", "s", null_frag>;
 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", null_frag>;
def  VMVNq    : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
                      (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
                      "vmvn", "$Vd, $Vm", "",
                      [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
 let Predicates = [HasNEON] in {
 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
 }
 
-//   VBSL     : Vector Bitwise Select
-def  VBSLd    : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
-                     (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
-                     N3RegFrm, IIC_VCNTiD,
-                     "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
-                     [(set DPR:$Vd,
-                           (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
+// The TwoAddress pass will not go looking for equivalent operations
+// with different register constraints; it just inserts copies.
+// That is why pseudo VBSP implemented. Is is expanded later into
+// VBIT/VBIF/VBSL taking into account register constraints to avoid copies.
+def  VBSPd
+  : PseudoNeonI<(outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
+                IIC_VBINiD, "",
+                      (v2i32 (NEONvbsp DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
 let Predicates = [HasNEON] in {
 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 DPR:$src1),
                                    (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))),
-          (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>;
+          (VBSPd DPR:$src1, DPR:$Vn, DPR:$Vm)>;
 def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 DPR:$src1),
                                     (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))),
-          (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>;
+          (VBSPd DPR:$src1, DPR:$Vn, DPR:$Vm)>;
 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 DPR:$src1),
                                     (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))),
-          (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>;
+          (VBSPd DPR:$src1, DPR:$Vn, DPR:$Vm)>;
 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 DPR:$src1),
                                     (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))),
-          (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>;
+          (VBSPd DPR:$src1, DPR:$Vn, DPR:$Vm)>;
 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 DPR:$src1),
                                     (v1i64 DPR:$Vn), (v1i64 DPR:$Vm))),
-          (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>;
+          (VBSPd DPR:$src1, DPR:$Vn, DPR:$Vm)>;
 
 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
                      (and DPR:$Vm, (vnotd DPR:$Vd)))),
-          (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
+          (VBSPd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
 
 def : Pat<(v1i64 (or (and DPR:$Vn, DPR:$Vd),
                      (and DPR:$Vm, (vnotd DPR:$Vd)))),
-          (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
+          (VBSPd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
 }
 
-def  VBSLq    : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
-                     (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
-                     N3RegFrm, IIC_VCNTiQ,
-                     "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
-                     [(set QPR:$Vd,
-                           (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
-
+def  VBSPq
+  : PseudoNeonI<(outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
+                IIC_VBINiQ, "",
+                      (v4i32 (NEONvbsp QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
 let Predicates = [HasNEON] in {
 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 QPR:$src1),
                                    (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))),
-          (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>;
+          (VBSPq QPR:$src1, QPR:$Vn, QPR:$Vm)>;
 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 QPR:$src1),
                                     (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))),
-          (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>;
+          (VBSPq QPR:$src1, QPR:$Vn, QPR:$Vm)>;
 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 QPR:$src1),
                                     (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))),
-          (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>;
+          (VBSPq QPR:$src1, QPR:$Vn, QPR:$Vm)>;
 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 QPR:$src1),
                                     (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))),
-          (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>;
+          (VBSPq QPR:$src1, QPR:$Vn, QPR:$Vm)>;
 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 QPR:$src1),
                                     (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))),
-          (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>;
+          (VBSPq QPR:$src1, QPR:$Vn, QPR:$Vm)>;
 
 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
                      (and QPR:$Vm, (vnotq QPR:$Vd)))),
-          (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
+          (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
 def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd),
                      (and QPR:$Vm, (vnotq QPR:$Vd)))),
-          (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
+          (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
 }
 
+//   VBSL     : Vector Bitwise Select
+def  VBSLd    : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
+                     (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
+                     N3RegFrm, IIC_VBINiD,
+                     "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
+                     []>;
+
+def  VBSLq    : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
+                     (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
+                     N3RegFrm, IIC_VBINiQ,
+                     "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
+                     []>;
+
 //   VBIF     : Vector Bitwise Insert if False
 //              like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
-// FIXME: This instruction's encoding MAY NOT BE correct.
 def  VBIFd    : N3VX<1, 0, 0b11, 0b0001, 0, 1,
                      (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
                      N3RegFrm, IIC_VBINiD,
                      "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
                      []>;
 def  VBIFq    : N3VX<1, 0, 0b11, 0b0001, 1, 1,
                      (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
                      N3RegFrm, IIC_VBINiQ,
                      "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
                      []>;
 
 //   VBIT     : Vector Bitwise Insert if True
 //              like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
-// FIXME: This instruction's encoding MAY NOT BE correct.
 def  VBITd    : N3VX<1, 0, 0b10, 0b0001, 0, 1,
                      (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
                      N3RegFrm, IIC_VBINiD,
                      "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
                      []>;
 def  VBITq    : N3VX<1, 0, 0b10, 0b0001, 1, 1,
                      (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
                      N3RegFrm, IIC_VBINiQ,
                      "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
                      []>;
 
-// VBIT/VBIF are not yet implemented.  The TwoAddress pass will not go looking
-// for equivalent operations with different register constraints; it just
-// inserts copies.
-
 // Vector Absolute Differences.
 
 //   VABD     : Vector Absolute Difference
 defm VABDs    : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
                            IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
                            "vabd", "s", int_arm_neon_vabds, 1>;
 defm VABDu    : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
                            IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
def : Pat<(v2i64 (zextloadvi8 addrmode6:$addr)),
         (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
            (VLD1LNd16 addrmode6:$addr,
                       (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
   def : Pat<(v2i64 (sextloadvi8 addrmode6:$addr)),
         (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
            (VLD1LNd16 addrmode6:$addr,
                       (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
 }
-// The following patterns are basically a copy of the patterns above, 
+// The following patterns are basically a copy of the patterns above,
 // however with an additional VREV16d instruction to convert data
 // loaded by VLD1LN into proper vector format in big endian mode.
 let Predicates = [HasNEON,IsBE] in {
   def : Pat<(v2i64 (extloadvi8 addrmode6:$addr)),
         (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
            (!cast<Instruction>("VREV16d8")
              (VLD1LNd16 addrmode6:$addr,
                         (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0))>;

llvm/lib/Target/ARM/ARMScheduleA57.td

 
 // ASIMD FP round to integral
 def : InstRW<[A57Write_5cyc_1V], (instregex
   "VRINT(AN|MN|NN|PN|XN|ZN)(Df|Qf|Dh|Qh)")>;
 
 // --- 3.16 ASIMD Miscellaneous Instructions ---
 
 // ASIMD bitwise insert
-def : InstRW<[A57Write_3cyc_1V], (instregex "VBIF", "VBIT", "VBSL")>;
+def : InstRW<[A57Write_3cyc_1V], (instregex "VBIF", "VBIT", "VBSL", "VBSP")>;
 
 // ASIMD count
 def : InstRW<[A57Write_3cyc_1V], (instregex "VCLS", "VCLZ", "VCNT")>;
 
 // ASIMD duplicate, core reg: 8cyc "L, F0/F1"
 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "VDUP(8|16|32)(d|q)")>;
 
 // ASIMD duplicate, scalar: 3cyc "F0/F1"

llvm/lib/Target/ARM/ARMScheduleR52.td

def : InstRW<[R52Write2FPALU_F4, R52Read_F1, R52Read_F1],
                                             (instregex "VADDL", "VADDW", "VSUBL", "VSUBW")>;
 
 def : InstRW<[R52WriteFPALU_F3, R52Read_F2, R52Read_F2], (instregex "(VAND|VBIC|VEOR)d")>;
 def : InstRW<[R52Write2FPALU_F3, R52Read_F2, R52Read_F2], (instregex "(VAND|VBIC|VEOR)q")>;
 
 def : InstRW<[R52WriteFPALU_F3, R52Read_F2], (instregex "VBICi(v4i16|v2i32)")>;
 def : InstRW<[R52Write2FPALU_F3, R52Read_F2], (instregex "VBICi(v8i16|v4i32)")>;
 
-def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL)d")>;
-def : InstRW<[R52Write2FPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL)q")>;
+def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL|VBSP)d")>;
+def : InstRW<[R52Write2FPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL|VBSP)q")>;
 
 def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1],
       (instregex "(VCEQ|VCGE|VCGT|VCLE|VCLT|VCLZ|VCMP|VCMPE|VCNT)")>;
 def : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1],
       (instregex "VCVT", "VSITO", "VUITO", "VTO")>;
 
 def : InstRW<[R52WriteFPALU_F3, R52Read_ISS], (instregex "VDUP(8|16|32)d")>;
 def : InstRW<[R52Write2FPALU_F3, R52Read_ISS], (instregex "VDUP(8|16|32)q")>;

llvm/lib/Target/ARM/ARMScheduleSwift.td

let SchedModel = SwiftModel in {
   def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; }
   def : InstRW<[WriteNoop], (instregex "t2IT", "IT")>;
 
   // 4.2.28 Advanced SIMD, Integer, 2 cycle
   def : InstRW<[SwiftWriteP0TwoCycle],
         (instregex "VADDv", "VSUBv", "VNEG(s|f|v)", "VADDL", "VSUBL",
                    "VADDW", "VSUBW", "VHADD", "VHSUB", "VRHADD", "VPADDi",
                    "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",
-                   "VSHL", "VSHR(s|u)", "VSHLL", "VQSHL(s|u)", "VBIF",
-                   "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
+                   "VSHL", "VSHR(s|u)", "VSHLL", "VQSHL(s|u)", "VBIF", "VBIT",
+                   "VBSL", "VBSP", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
 
   def : InstRW<[SwiftWriteP1TwoCycle],
         (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
 
   // 4.2.29 Advanced SIMD, Integer, 4 cycle
   // 4.2.30 Advanced SIMD, Integer with Accumulate
   def : InstRW<[SwiftWriteP0FourCycle],
         (instregex "VABA", "VABAL", "VPADAL", "VRSRA", "VSRA", "VACGE", "VACGT",

llvm/test/CodeGen/ARM/fcopysign.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -disable-post-ra -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=SOFT
 ; RUN: llc < %s -disable-post-ra -mtriple=armv7-gnueabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s -check-prefix=HARD
 
 ; rdar://8984306
 define float @test1(float %x, float %y) nounwind {
 ; SOFT-LABEL: test1:
 ; SOFT:       @ %bb.0: @ %entry
 ; SOFT-NEXT:    lsr r1, r1, #31
 ; SOFT-NEXT:    bfi r0, r1, #31, #1
 ; SOFT-NEXT:    bx lr
 ;
 ; HARD-LABEL: test1:
 ; HARD:       @ %bb.0: @ %entry
-; HARD-NEXT:    vmov.f32 s4, s1
+; HARD-NEXT:    vmov.f32 s2, s1
 ; HARD-NEXT:    @ kill: def $s0 killed $s0 def $d0
-; HARD-NEXT:    vmov.i32 d1, #0x80000000
-; HARD-NEXT:    vbsl d1, d2, d0
-; HARD-NEXT:    vmov.f32 s0, s2
+; HARD-NEXT:    vmov.i32 d16, #0x80000000
+; HARD-NEXT:    vbit d0, d1, d16
+; HARD-NEXT:    @ kill: def $s0 killed $s0 killed $d0
 ; HARD-NEXT:    bx lr
 entry:
 
   %0 = tail call float @copysignf(float %x, float %y) nounwind readnone
   ret float %0
 }
 
 define double @test2(double %x, double %y) nounwind {
 ; SOFT-LABEL: test2:
 ; SOFT:       @ %bb.0: @ %entry
 ; SOFT-NEXT:    lsr r2, r3, #31
 ; SOFT-NEXT:    bfi r1, r2, #31, #1
 ; SOFT-NEXT:    bx lr
 ;
 ; HARD-LABEL: test2:
 ; HARD:       @ %bb.0: @ %entry
 ; HARD-NEXT:    vmov.i32 d16, #0x80000000
 ; HARD-NEXT:    vshl.i64 d16, d16, #32
-; HARD-NEXT:    vbsl d16, d1, d0
-; HARD-NEXT:    vorr d0, d16, d16
+; HARD-NEXT:    vbit d0, d1, d16
 ; HARD-NEXT:    bx lr
 entry:
 
   %0 = tail call double @copysign(double %x, double %y) nounwind readnone
   ret double %0
 }
 
 define double @test3(double %x, double %y, double %z) nounwind {
 ; SOFT-LABEL: test3:
 ; SOFT:       @ %bb.0: @ %entry
 ; SOFT-NEXT:    vmov d16, r2, r3
 ; SOFT-NEXT:    vmov d17, r0, r1
 ; SOFT-NEXT:    vmul.f64 d16, d17, d16
 ; SOFT-NEXT:    vmov.i32 d17, #0x80000000
 ; SOFT-NEXT:    vshl.i64 d17, d17, #32
 ; SOFT-NEXT:    vldr d18, [sp]
-; SOFT-NEXT:    vbsl d17, d18, d16
-; SOFT-NEXT:    vmov r0, r1, d17
+; SOFT-NEXT:    vbit d16, d18, d17
+; SOFT-NEXT:    vmov r0, r1, d16
 ; SOFT-NEXT:    bx lr
 ;
 ; HARD-LABEL: test3:
 ; HARD:       @ %bb.0: @ %entry
 ; HARD-NEXT:    vmul.f64 d16, d0, d1
 ; HARD-NEXT:    vmov.i32 d17, #0x80000000
-; HARD-NEXT:    vshl.i64 d0, d17, #32
+; HARD-NEXT:    vshl.i64 d17, d17, #32
+; HARD-NEXT:    vorr d0, d17, d17
 ; HARD-NEXT:    vbsl d0, d2, d16
 ; HARD-NEXT:    bx lr
 entry:
   %0 = fmul double %x, %y
   %1 = tail call double @copysign(double %0, double %z) nounwind readnone
   ret double %1
 }
 
 ; rdar://9287902
 define float @test4() nounwind {
 ; SOFT-LABEL: test4:
 ; SOFT:       @ %bb.0: @ %entry
 ; SOFT-NEXT:    push {lr}
 ; SOFT-NEXT:    bl _bar
 ; SOFT-NEXT:    vmov d16, r0, r1
 ; SOFT-NEXT:    vcvt.f32.f64 s0, d16
 ; SOFT-NEXT:    vmov.i32 d17, #0x80000000
 ; SOFT-NEXT:    vshr.u64 d16, d16, #32
 ; SOFT-NEXT:    vmov.f32 d18, #5.000000e-01
-; SOFT-NEXT:    vbsl d17, d16, d18
-; SOFT-NEXT:    vadd.f32 d0, d0, d17
+; SOFT-NEXT:    vbif d16, d18, d17
+; SOFT-NEXT:    vadd.f32 d0, d0, d16
 ; SOFT-NEXT:    vmov r0, s0
 ; SOFT-NEXT:    pop {lr}
 ;
 ; HARD-LABEL: test4:
 ; HARD:       @ %bb.0: @ %entry
 ; HARD-NEXT:    .save {r11, lr}
 ; HARD-NEXT:    push {r11, lr}
 ; HARD-NEXT:    bl bar
 ; HARD-NEXT:    vmov d16, r0, r1
 ; HARD-NEXT:    vcvt.f32.f64 s0, d16
-; HARD-NEXT:    vmov.i32 d1, #0x80000000
+; HARD-NEXT:    vmov.i32 d17, #0x80000000
 ; HARD-NEXT:    vshr.u64 d16, d16, #32
-; HARD-NEXT:    vmov.f32 s4, #5.000000e-01
-; HARD-NEXT:    vbsl d1, d16, d2
+; HARD-NEXT:    vmov.f32 s2, #5.000000e-01
+; HARD-NEXT:    vbit d1, d16, d17
 ; HARD-NEXT:    vadd.f32 s0, s0, s2
 ; HARD-NEXT:    pop {r11, pc}
 entry:
   %0 = tail call double (...) @bar() nounwind
   %1 = fptrunc double %0 to float
   %2 = tail call float @copysignf(float 5.000000e-01, float %1) nounwind readnone
   %3 = fadd float %1, %2
   ret float %3
 }
 
 declare double @bar(...)
 declare double @copysign(double, double) nounwind
 declare float @copysignf(float, float) nounwind

llvm/test/CodeGen/ARM/fp16-promote.ll

define void @test_maximum(half* %p) #0 {
   %c = fcmp ugt half %a, 1.0
   %r = select i1 %c, half %a, half 1.0
   store half %r, half* %p
   ret void
 }
 
 ; CHECK-FP16-LABEL: test_copysign:
 ; CHECK-FP16:         ldrh r2, [r0]
-; CHECK-FP16-NEXT:    vmov.i32 d0, #0x80000000
+; CHECK-FP16-NEXT:    vmov.i32 d16, #0x80000000
 ; CHECK-FP16-NEXT:    ldrh r1, [r1]
-; CHECK-FP16-NEXT:    vmov s2, r2
-; CHECK-FP16-NEXT:    vmov s4, r1
+; CHECK-FP16-NEXT:    vmov s0, r2
+; CHECK-FP16-NEXT:    vmov s2, r1
+; CHECK-FP16-NEXT:    vcvtb.f32.f16 s0, s0
 ; CHECK-FP16-NEXT:    vcvtb.f32.f16 s2, s2
-; CHECK-FP16-NEXT:    vcvtb.f32.f16 s4, s4
-; CHECK-FP16-NEXT:    vbsl d0, d2, d1
+; CHECK-FP16-NEXT:    vbit d0, d1, d16
 ; CHECK-FP16-NEXT:    vcvtb.f16.f32 s0, s0
 ; CHECK-FP16-NEXT:    vmov r1, s0
 ; CHECK-FP16-NEXT:    strh r1, [r0]
 ; CHECK-FP16-NEXT:    bx lr
 
 ; CHECK-LIBCALL-LABEL: test_copysign:
 ; CHECK-LIBCALL-VFP:         .fnstart
 ; CHECK-LIBCALL-VFP-NEXT:    .save {r4, r5, r11, lr}
 ; CHECK-LIBCALL-VFP-NEXT:    push {r4, r5, r11, lr}
 ; CHECK-LIBCALL-VFP-NEXT:    .vsave {d8, d9}
 ; CHECK-LIBCALL-VFP-NEXT:    vpush {d8, d9}
 ; CHECK-LIBCALL-VFP-NEXT:    mov r5, r0
 ; CHECK-LIBCALL-VFP-NEXT:    ldrh r0, [r0]
 ; CHECK-LIBCALL-VFP-NEXT:    mov r4, r1
 ; CHECK-LIBCALL: bl __aeabi_h2f
 ; CHECK-LIBCALL-VFP:         ldrh r1, [r4]
 ; CHECK-LIBCALL-VFP-NEXT:    vmov s18, r0
 ; CHECK-LIBCALL-VFP-NEXT:    vmov.i32 d8, #0x80000000
 ; CHECK-LIBCALL-VFP-NEXT:    mov r0, r1
 ; CHECK-LIBCALL: bl __aeabi_h2f
 ; CHECK-LIBCALL-VFP:         vmov s0, r0
-; CHECK-LIBCALL-VFP-NEXT:    vbsl d8, d0, d9
-; CHECK-LIBCALL-VFP-NEXT:    vmov r0, s16
+; CHECK-LIBCALL-VFP-NEXT:    vbif d0, d9, d8
+; CHECK-LIBCALL-VFP-NEXT:    vmov r0, s0
 ; CHECK-LIBCALL: bl __aeabi_f2h
 ; CHECK-LIBCALL-VFP:         strh r0, [r5]
 ; CHECK-LIBCALL-VFP-NEXT:    vpop {d8, d9}
 ; CHECK-LIBCALL-VFP-NEXT:    pop {r4, r5, r11, pc}
 ; CHECK-NOVFP: and
 ; CHECK-NOVFP: bic
 ; CHECK-NOVFP: orr
 define void @test_copysign(half* %p, half* %q) #0 {

llvm/test/CodeGen/ARM/vbsl-constant.ll

 }
 
 define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
 ; CHECK-LABEL: v_bslQi8:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vld1.32 {d16, d17}, [r2]
 ; CHECK-NEXT:    vmov.i8 q9, #0x3
 ; CHECK-NEXT:    vld1.32 {d20, d21}, [r0]
-; CHECK-NEXT:    vbsl q9, q10, q8
-; CHECK-NEXT:    vmov r0, r1, d18
-; CHECK-NEXT:    vmov r2, r3, d19
+; CHECK-NEXT:    vbit q8, q10, q9
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    mov pc, lr
   %tmp1 = load <16 x i8>, <16 x i8>* %A
   %tmp2 = load <16 x i8>, <16 x i8>* %B
   %tmp3 = load <16 x i8>, <16 x i8>* %C
   %tmp4 = and <16 x i8> %tmp1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   %tmp6 = and <16 x i8> %tmp3, <i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4>
   %tmp7 = or <16 x i8> %tmp4, %tmp6
   ret <16 x i8> %tmp7
 }
 
 define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
 ; CHECK-LABEL: v_bslQi16:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vld1.32 {d16, d17}, [r2]
 ; CHECK-NEXT:    vmov.i16 q9, #0x3
 ; CHECK-NEXT:    vld1.32 {d20, d21}, [r0]
-; CHECK-NEXT:    vbsl q9, q10, q8
-; CHECK-NEXT:    vmov r0, r1, d18
-; CHECK-NEXT:    vmov r2, r3, d19
+; CHECK-NEXT:    vbit q8, q10, q9
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    mov pc, lr
   %tmp1 = load <8 x i16>, <8 x i16>* %A
   %tmp2 = load <8 x i16>, <8 x i16>* %B
   %tmp3 = load <8 x i16>, <8 x i16>* %C
   %tmp4 = and <8 x i16> %tmp1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
   %tmp6 = and <8 x i16> %tmp3, <i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4>
   %tmp7 = or <8 x i16> %tmp4, %tmp6
   ret <8 x i16> %tmp7
 }
 
 define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
 ; CHECK-LABEL: v_bslQi32:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vld1.32 {d16, d17}, [r2]
 ; CHECK-NEXT:    vmov.i32 q9, #0x3
 ; CHECK-NEXT:    vld1.32 {d20, d21}, [r0]
-; CHECK-NEXT:    vbsl q9, q10, q8
-; CHECK-NEXT:    vmov r0, r1, d18
-; CHECK-NEXT:    vmov r2, r3, d19
+; CHECK-NEXT:    vbit q8, q10, q9
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    mov pc, lr
   %tmp1 = load <4 x i32>, <4 x i32>* %A
   %tmp2 = load <4 x i32>, <4 x i32>* %B
   %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp4 = and <4 x i32> %tmp1, <i32 3, i32 3, i32 3, i32 3>
   %tmp6 = and <4 x i32> %tmp3, <i32 -4, i32 -4, i32 -4, i32 -4>
   %tmp7 = or <4 x i32> %tmp4, %tmp6
   ret <4 x i32> %tmp7
 }
 
 define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind {
 ; CHECK-LABEL: v_bslQi64:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vld1.32 {d16, d17}, [r2]
 ; CHECK-NEXT:    vld1.32 {d18, d19}, [r0]
 ; CHECK-NEXT:    adr r0, LCPI7_0
 ; CHECK-NEXT:    vld1.64 {d20, d21}, [r0:128]
-; CHECK-NEXT:    vbsl q10, q9, q8
-; CHECK-NEXT:    vmov r0, r1, d20
-; CHECK-NEXT:    vmov r2, r3, d21
+; CHECK-NEXT:    vbit q8, q9, q10
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    mov pc, lr
   %tmp1 = load <2 x i64>, <2 x i64>* %A
   %tmp2 = load <2 x i64>, <2 x i64>* %B
   %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp4 = and <2 x i64> %tmp1, <i64 3, i64 3>
   %tmp6 = and <2 x i64> %tmp3, <i64 -4, i64 -4>
   %tmp7 = or <2 x i64> %tmp4, %tmp6
   ret <2 x i64> %tmp7
 }

llvm/test/CodeGen/ARM/vbsl.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
 
 ; rdar://12471808
 
 define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ; CHECK-LABEL: v_bsli8:
 ; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldr d18, [r0]
 ; CHECK-NEXT:    vldr d16, [r2]
 ; CHECK-NEXT:    vldr d17, [r1]
-; CHECK-NEXT:    vldr d18, [r0]
-; CHECK-NEXT:    vbsl d18, d17, d16
-; CHECK-NEXT:    vmov r0, r1, d18
+; CHECK-NEXT:    vbit d16, d17, d18
+; CHECK-NEXT:    vmov r0, r1, d16
 ; CHECK-NEXT:    mov pc, lr
   %tmp1 = load <8 x i8>, <8 x i8>* %A
   %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = load <8 x i8>, <8 x i8>* %C
   %tmp4 = and <8 x i8> %tmp1, %tmp2
   %tmp5 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
   %tmp6 = and <8 x i8> %tmp5, %tmp3
   %tmp7 = or <8 x i8> %tmp4, %tmp6
   ret <8 x i8> %tmp7
 }
 
 define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ; CHECK-LABEL: v_bsli16:
 ; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldr d18, [r0]
 ; CHECK-NEXT:    vldr d16, [r2]
 ; CHECK-NEXT:    vldr d17, [r1]
-; CHECK-NEXT:    vldr d18, [r0]
-; CHECK-NEXT:    vbsl d18, d17, d16
-; CHECK-NEXT:    vmov r0, r1, d18
+; CHECK-NEXT:    vbit d16, d17, d18
+; CHECK-NEXT:    vmov r0, r1, d16
 ; CHECK-NEXT:    mov pc, lr
   %tmp1 = load <4 x i16>, <4 x i16>* %A
   %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = load <4 x i16>, <4 x i16>* %C
   %tmp4 = and <4 x i16> %tmp1, %tmp2
   %tmp5 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 >
   %tmp6 = and <4 x i16> %tmp5, %tmp3
   %tmp7 = or <4 x i16> %tmp4, %tmp6
   ret <4 x i16> %tmp7
 }
 
 define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ; CHECK-LABEL: v_bsli32:
 ; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldr d18, [r0]
 ; CHECK-NEXT:    vldr d16, [r2]
 ; CHECK-NEXT:    vldr d17, [r1]
-; CHECK-NEXT:    vldr d18, [r0]
-; CHECK-NEXT:    vbsl d18, d17, d16
-; CHECK-NEXT:    vmov r0, r1, d18
+; CHECK-NEXT:    vbit d16, d17, d18
+; CHECK-NEXT:    vmov r0, r1, d16
 ; CHECK-NEXT:    mov pc, lr
   %tmp1 = load <2 x i32>, <2 x i32>* %A
   %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = load <2 x i32>, <2 x i32>* %C
   %tmp4 = and <2 x i32> %tmp1, %tmp2
   %tmp5 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 >
   %tmp6 = and <2 x i32> %tmp5, %tmp3
   %tmp7 = or <2 x i32> %tmp4, %tmp6
   ret <2 x i32> %tmp7
 }
 
 define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind {
 ; CHECK-LABEL: v_bsli64:
 ; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldr d18, [r0]
 ; CHECK-NEXT:    vldr d16, [r2]
 ; CHECK-NEXT:    vldr d17, [r1]
-; CHECK-NEXT:    vldr d18, [r0]
-; CHECK-NEXT:    vbsl d18, d17, d16
-; CHECK-NEXT:    vmov r0, r1, d18
+; CHECK-NEXT:    vbit d16, d17, d18
+; CHECK-NEXT:    vmov r0, r1, d16
 ; CHECK-NEXT:    mov pc, lr
   %tmp1 = load <1 x i64>, <1 x i64>* %A
   %tmp2 = load <1 x i64>, <1 x i64>* %B
   %tmp3 = load <1 x i64>, <1 x i64>* %C
   %tmp4 = and <1 x i64> %tmp1, %tmp2
   %tmp5 = xor <1 x i64> %tmp1, < i64 -1 >
   %tmp6 = and <1 x i64> %tmp5, %tmp3
   %tmp7 = or <1 x i64> %tmp4, %tmp6
   ret <1 x i64> %tmp7
 }
 
 define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
 ; CHECK-LABEL: v_bslQi8:
 ; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vld1.64 {d20, d21}, [r0]
 ; CHECK-NEXT:    vld1.64 {d16, d17}, [r2]
 ; CHECK-NEXT:    vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT:    vld1.64 {d20, d21}, [r0]
-; CHECK-NEXT:    vbsl q10, q9, q8
-; CHECK-NEXT:    vmov r0, r1, d20
-; CHECK-NEXT:    vmov r2, r3, d21
+; CHECK-NEXT:    vbit q8, q9, q10
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    mov pc, lr
   %tmp1 = load <16 x i8>, <16 x i8>* %A
   %tmp2 = load <16 x i8>, <16 x i8>* %B
   %tmp3 = load <16 x i8>, <16 x i8>* %C
   %tmp4 = and <16 x i8> %tmp1, %tmp2
   %tmp5 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
   %tmp6 = and <16 x i8> %tmp5, %tmp3
   %tmp7 = or <16 x i8> %tmp4, %tmp6
   ret <16 x i8> %tmp7
 }
 
 define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
 ; CHECK-LABEL: v_bslQi16:
 ; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vld1.64 {d20, d21}, [r0]
 ; CHECK-NEXT:    vld1.64 {d16, d17}, [r2]
 ; CHECK-NEXT:    vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT:    vld1.64 {d20, d21}, [r0]
-; CHECK-NEXT:    vbsl q10, q9, q8
-; CHECK-NEXT:    vmov r0, r1, d20
-; CHECK-NEXT:    vmov r2, r3, d21
+; CHECK-NEXT:    vbit q8, q9, q10
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    mov pc, lr
   %tmp1 = load <8 x i16>, <8 x i16>* %A
   %tmp2 = load <8 x i16>, <8 x i16>* %B
   %tmp3 = load <8 x i16>, <8 x i16>* %C
   %tmp4 = and <8 x i16> %tmp1, %tmp2
   %tmp5 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
   %tmp6 = and <8 x i16> %tmp5, %tmp3
   %tmp7 = or <8 x i16> %tmp4, %tmp6
   ret <8 x i16> %tmp7
 }
 
 define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
 ; CHECK-LABEL: v_bslQi32:
 ; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vld1.64 {d20, d21}, [r0]
 ; CHECK-NEXT:    vld1.64 {d16, d17}, [r2]
 ; CHECK-NEXT:    vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT:    vld1.64 {d20, d21}, [r0]
-; CHECK-NEXT:    vbsl q10, q9, q8
-; CHECK-NEXT:    vmov r0, r1, d20
-; CHECK-NEXT:    vmov r2, r3, d21
+; CHECK-NEXT:    vbit q8, q9, q10
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    mov pc, lr
   %tmp1 = load <4 x i32>, <4 x i32>* %A
   %tmp2 = load <4 x i32>, <4 x i32>* %B
   %tmp3 = load <4 x i32>, <4 x i32>* %C
   %tmp4 = and <4 x i32> %tmp1, %tmp2
   %tmp5 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 >
   %tmp6 = and <4 x i32> %tmp5, %tmp3
   %tmp7 = or <4 x i32> %tmp4, %tmp6
   ret <4 x i32> %tmp7
 }
 
 define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind {
 ; CHECK-LABEL: v_bslQi64:
 ; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vld1.64 {d20, d21}, [r0]
 ; CHECK-NEXT:    vld1.64 {d16, d17}, [r2]
 ; CHECK-NEXT:    vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT:    vld1.64 {d20, d21}, [r0]
-; CHECK-NEXT:    vbsl q10, q9, q8
-; CHECK-NEXT:    vmov r0, r1, d20
-; CHECK-NEXT:    vmov r2, r3, d21
+; CHECK-NEXT:    vbit q8, q9, q10
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    mov pc, lr
   %tmp1 = load <2 x i64>, <2 x i64>* %A
   %tmp2 = load <2 x i64>, <2 x i64>* %B
   %tmp3 = load <2 x i64>, <2 x i64>* %C
   %tmp4 = and <2 x i64> %tmp1, %tmp2
   %tmp5 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 >
   %tmp6 = and <2 x i64> %tmp5, %tmp3
   %tmp7 = or <2 x i64> %tmp4, %tmp6
   ret <2 x i64> %tmp7
 }
 
 define <8 x i8> @f1(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind readnone optsize ssp {
 ; CHECK-LABEL: f1:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr d16, [sp]
 ; CHECK-NEXT:    vmov d17, r2, r3
 ; CHECK-NEXT:    vmov d18, r0, r1
-; CHECK-NEXT:    vbsl d18, d17, d16
-; CHECK-NEXT:    vmov r0, r1, d18
+; CHECK-NEXT:    vbit d16, d17, d18
+; CHECK-NEXT:    vmov r0, r1, d16
 ; CHECK-NEXT:    mov pc, lr
   %vbsl.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind
   ret <8 x i8> %vbsl.i
 }
 
 define <4 x i16> @f2(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind readnone optsize ssp {
 ; CHECK-LABEL: f2:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr d16, [sp]
 ; CHECK-NEXT:    vmov d17, r2, r3
 ; CHECK-NEXT:    vmov d18, r0, r1
-; CHECK-NEXT:    vbsl d18, d17, d16
-; CHECK-NEXT:    vmov r0, r1, d18
+; CHECK-NEXT:    vbit d16, d17, d18
+; CHECK-NEXT:    vmov r0, r1, d16
 ; CHECK-NEXT:    mov pc, lr
   %vbsl3.i = tail call <4 x i16> @llvm.arm.neon.vbsl.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind
   ret <4 x i16> %vbsl3.i
 }
 
 define <2 x i32> @f3(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind readnone optsize ssp {
 ; CHECK-LABEL: f3:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr d16, [sp]
 ; CHECK-NEXT:    vmov d17, r2, r3
 ; CHECK-NEXT:    vmov d18, r0, r1
-; CHECK-NEXT:    vbsl d18, d17, d16
-; CHECK-NEXT:    vmov r0, r1, d18
+; CHECK-NEXT:    vbit d16, d17, d18
+; CHECK-NEXT:    vmov r0, r1, d16
 ; CHECK-NEXT:    mov pc, lr
   %vbsl3.i = tail call <2 x i32> @llvm.arm.neon.vbsl.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind
   ret <2 x i32> %vbsl3.i
 }
 
 define <2 x float> @f4(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone optsize ssp {
 ; CHECK-LABEL: f4:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr d16, [sp]
 ; CHECK-NEXT:    vmov d17, r2, r3
 ; CHECK-NEXT:    vmov d18, r0, r1
-; CHECK-NEXT:    vbsl d18, d17, d16
-; CHECK-NEXT:    vmov r0, r1, d18
+; CHECK-NEXT:    vbit d16, d17, d18
+; CHECK-NEXT:    vmov r0, r1, d16
 ; CHECK-NEXT:    mov pc, lr
   %vbsl4.i = tail call <2 x float> @llvm.arm.neon.vbsl.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind
   ret <2 x float> %vbsl4.i
 }
 
 define <16 x i8> @g1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind readnone optsize ssp {
 ; CHECK-LABEL: g1:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    add r12, sp, #16
 ; CHECK-NEXT:    vmov d19, r2, r3
-; CHECK-NEXT:    vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT:    add r12, sp, #16
 ; CHECK-NEXT:    vmov d18, r0, r1
 ; CHECK-NEXT:    mov r0, sp
+; CHECK-NEXT:    vld1.64 {d16, d17}, [r12]
 ; CHECK-NEXT:    vld1.64 {d20, d21}, [r0]
-; CHECK-NEXT:    vbsl q9, q10, q8
-; CHECK-NEXT:    vmov r0, r1, d18
-; CHECK-NEXT:    vmov r2, r3, d19
+; CHECK-NEXT:    vbit q8, q10, q9
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    mov pc, lr
   %vbsl.i = tail call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind
   ret <16 x i8> %vbsl.i
 }
 
 define <8 x i16> @g2(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind readnone optsize ssp {
 ; CHECK-LABEL: g2:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    add r12, sp, #16
 ; CHECK-NEXT:    vmov d19, r2, r3
-; CHECK-NEXT:    vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT:    add r12, sp, #16
 ; CHECK-NEXT:    vmov d18, r0, r1
 ; CHECK-NEXT:    mov r0, sp
+; CHECK-NEXT:    vld1.64 {d16, d17}, [r12]
 ; CHECK-NEXT:    vld1.64 {d20, d21}, [r0]
-; CHECK-NEXT:    vbsl q9, q10, q8
-; CHECK-NEXT:    vmov r0, r1, d18
-; CHECK-NEXT:    vmov r2, r3, d19
+; CHECK-NEXT:    vbit q8, q10, q9
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    mov pc, lr
   %vbsl3.i = tail call <8 x i16> @llvm.arm.neon.vbsl.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind
   ret <8 x i16> %vbsl3.i
 }
 
 define <4 x i32> @g3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
 ; CHECK-LABEL: g3:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    add r12, sp, #16
 ; CHECK-NEXT:    vmov d19, r2, r3
-; CHECK-NEXT:    vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT:    add r12, sp, #16
 ; CHECK-NEXT:    vmov d18, r0, r1
 ; CHECK-NEXT:    mov r0, sp
+; CHECK-NEXT:    vld1.64 {d16, d17}, [r12]
 ; CHECK-NEXT:    vld1.64 {d20, d21}, [r0]
-; CHECK-NEXT:    vbsl q9, q10, q8
-; CHECK-NEXT:    vmov r0, r1, d18
-; CHECK-NEXT:    vmov r2, r3, d19
+; CHECK-NEXT:    vbit q8, q10, q9
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    mov pc, lr
   %vbsl3.i = tail call <4 x i32> @llvm.arm.neon.vbsl.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind
   ret <4 x i32> %vbsl3.i
 }
 
 define <4 x float> @g4(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind readnone optsize ssp {
 ; CHECK-LABEL: g4:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    add r12, sp, #16
 ; CHECK-NEXT:    vmov d19, r2, r3
-; CHECK-NEXT:    vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT:    add r12, sp, #16
 ; CHECK-NEXT:    vmov d18, r0, r1
 ; CHECK-NEXT:    mov r0, sp
+; CHECK-NEXT:    vld1.64 {d16, d17}, [r12]
 ; CHECK-NEXT:    vld1.64 {d20, d21}, [r0]
-; CHECK-NEXT:    vbsl q9, q10, q8
-; CHECK-NEXT:    vmov r0, r1, d18
-; CHECK-NEXT:    vmov r2, r3, d19
+; CHECK-NEXT:    vbit q8, q10, q9
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    mov pc, lr
   %vbsl4.i = tail call <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind
   ret <4 x float> %vbsl4.i
 }
 
 define <1 x i64> @test_vbsl_s64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {
 ; CHECK-LABEL: test_vbsl_s64:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr d16, [sp]
 ; CHECK-NEXT:    vmov d17, r2, r3
 ; CHECK-NEXT:    vmov d18, r0, r1
-; CHECK-NEXT:    vbsl d18, d17, d16
-; CHECK-NEXT:    vmov r0, r1, d18
+; CHECK-NEXT:    vbit d16, d17, d18
+; CHECK-NEXT:    vmov r0, r1, d16
 ; CHECK-NEXT:    mov pc, lr
   %vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind
   ret <1 x i64> %vbsl3.i
 }
 
 define <1 x i64> @test_vbsl_u64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {
 ; CHECK-LABEL: test_vbsl_u64:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr d16, [sp]
 ; CHECK-NEXT:    vmov d17, r2, r3
 ; CHECK-NEXT:    vmov d18, r0, r1
-; CHECK-NEXT:    vbsl d18, d17, d16
-; CHECK-NEXT:    vmov r0, r1, d18
+; CHECK-NEXT:    vbit d16, d17, d18
+; CHECK-NEXT:    vmov r0, r1, d16
 ; CHECK-NEXT:    mov pc, lr
   %vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind
   ret <1 x i64> %vbsl3.i
 }
 
 define <2 x i64> @test_vbslq_s64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
 ; CHECK-LABEL: test_vbslq_s64:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    add r12, sp, #16
 ; CHECK-NEXT:    vmov d19, r2, r3
-; CHECK-NEXT:    vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT:    add r12, sp, #16
 ; CHECK-NEXT:    vmov d18, r0, r1
 ; CHECK-NEXT:    mov r0, sp
+; CHECK-NEXT:    vld1.64 {d16, d17}, [r12]
 ; CHECK-NEXT:    vld1.64 {d20, d21}, [r0]
-; CHECK-NEXT:    vbsl q9, q10, q8
-; CHECK-NEXT:    vmov r0, r1, d18
-; CHECK-NEXT:    vmov r2, r3, d19
+; CHECK-NEXT:    vbit q8, q10, q9
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    mov pc, lr
   %vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind
   ret <2 x i64> %vbsl3.i
 }
 
 define <2 x i64> @test_vbslq_u64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
 ; CHECK-LABEL: test_vbslq_u64:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    add r12, sp, #16
 ; CHECK-NEXT:    vmov d19, r2, r3
-; CHECK-NEXT:    vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT:    add r12, sp, #16
 ; CHECK-NEXT:    vmov d18, r0, r1
 ; CHECK-NEXT:    mov r0, sp
+; CHECK-NEXT:    vld1.64 {d16, d17}, [r12]
 ; CHECK-NEXT:    vld1.64 {d20, d21}, [r0]
-; CHECK-NEXT:    vbsl q9, q10, q8
-; CHECK-NEXT:    vmov r0, r1, d18
-; CHECK-NEXT:    vmov r2, r3, d19
+; CHECK-NEXT:    vbit q8, q10, q9
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    mov pc, lr
   %vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind
   ret <2 x i64> %vbsl3.i
 }
 
 declare <4 x i32> @llvm.arm.neon.vbsl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
 declare <8 x i16> @llvm.arm.neon.vbsl.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
 declare <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
 declare <2 x i32> @llvm.arm.neon.vbsl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone
 declare <4 x i16> @llvm.arm.neon.vbsl.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone
 declare <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
 declare <2 x float> @llvm.arm.neon.vbsl.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone
 declare <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
 declare <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone
 declare <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64>, <1 x i64>, <1 x i64>) nounwind readnone

llvm/test/CodeGen/ARM/vselect_imax.ll

 %T1_18 = type <4 x i1>
 define void @func_blend18(%T0_18* %loadaddr, %T0_18* %loadaddr2,
                            %T1_18* %blend, %T0_18* %storeaddr) {
 ; CHECK-LABEL: func_blend18:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    .save {r4, r5, r6, r7, r11, lr}
 ; CHECK-NEXT:    push {r4, r5, r6, r7, r11, lr}
 ; CHECK-NEXT:    vld1.64 {d22, d23}, [r0:128]!
-; CHECK-NEXT:    vld1.64 {d18, d19}, [r1:128]!
-; CHECK-NEXT:    vld1.64 {d16, d17}, [r1:128]
+; CHECK-NEXT:    vld1.64 {d16, d17}, [r1:128]!
+; CHECK-NEXT:    vld1.64 {d18, d19}, [r1:128]
 ; CHECK-NEXT:    mov r1, #0
 ; CHECK-NEXT:    vld1.64 {d20, d21}, [r0:128]
-; CHECK-NEXT:    vmov.32 r12, d16[0]
+; CHECK-NEXT:    vmov.32 r12, d18[0]
 ; CHECK-NEXT:    vmov.32 r2, d20[0]
-; CHECK-NEXT:    vmov.32 lr, d16[1]
+; CHECK-NEXT:    vmov.32 lr, d18[1]
 ; CHECK-NEXT:    vmov.32 r0, d20[1]
-; CHECK-NEXT:    vmov.32 r7, d18[0]
+; CHECK-NEXT:    vmov.32 r7, d16[0]
 ; CHECK-NEXT:    vmov.32 r5, d22[0]
 ; CHECK-NEXT:    vmov.32 r4, d22[1]
-; CHECK-NEXT:    vmov.32 r6, d17[0]
+; CHECK-NEXT:    vmov.32 r6, d19[0]
 ; CHECK-NEXT:    subs r2, r2, r12
-; CHECK-NEXT:    vmov.32 r2, d18[1]
+; CHECK-NEXT:    vmov.32 r2, d16[1]
 ; CHECK-NEXT:    sbcs r0, r0, lr
 ; CHECK-NEXT:    mov r0, #0
 ; CHECK-NEXT:    movlt r0, #1
 ; CHECK-NEXT:    cmp r0, #0
 ; CHECK-NEXT:    mvnne r0, #0
 ; CHECK-NEXT:    subs r7, r5, r7
 ; CHECK-NEXT:    vmov.32 r7, d21[0]
-; CHECK-NEXT:    vmov.32 r5, d17[1]
+; CHECK-NEXT:    vmov.32 r5, d19[1]
 ; CHECK-NEXT:    sbcs r2, r4, r2
 ; CHECK-NEXT:    vmov.32 r4, d21[1]
 ; CHECK-NEXT:    mov r2, #0
 ; CHECK-NEXT:    movlt r2, #1
 ; CHECK-NEXT:    cmp r2, #0
 ; CHECK-NEXT:    mvnne r2, #0
 ; CHECK-NEXT:    subs r7, r7, r6
 ; CHECK-NEXT:    vmov.32 r6, d23[0]
-; CHECK-NEXT:    vmov.32 r7, d19[0]
+; CHECK-NEXT:    vmov.32 r7, d17[0]
 ; CHECK-NEXT:    sbcs r5, r4, r5
 ; CHECK-NEXT:    mov r4, #0
 ; CHECK-NEXT:    movlt r4, #1
-; CHECK-NEXT:    vmov.32 r5, d19[1]
+; CHECK-NEXT:    vmov.32 r5, d17[1]
 ; CHECK-NEXT:    subs r7, r6, r7
 ; CHECK-NEXT:    vmov.32 r7, d23[1]
 ; CHECK-NEXT:    sbcs r7, r7, r5
 ; CHECK-NEXT:    movlt r1, #1
 ; CHECK-NEXT:    cmp r1, #0
 ; CHECK-NEXT:    mvnne r1, #0
 ; CHECK-NEXT:    cmp r4, #0
 ; CHECK-NEXT:    vdup.32 d25, r1
 ; CHECK-NEXT:    mvnne r4, #0
 ; CHECK-NEXT:    vdup.32 d24, r2
 ; CHECK-NEXT:    vdup.32 d27, r4
-; CHECK-NEXT:    vbsl q12, q11, q9
+; CHECK-NEXT:    vbit q8, q11, q12
 ; CHECK-NEXT:    vdup.32 d26, r0
-; CHECK-NEXT:    vbsl q13, q10, q8
-; CHECK-NEXT:    vst1.64 {d24, d25}, [r3:128]!
-; CHECK-NEXT:    vst1.64 {d26, d27}, [r3:128]
+; CHECK-NEXT:    vbit q9, q10, q13
+; CHECK-NEXT:    vst1.64 {d16, d17}, [r3:128]!
+; CHECK-NEXT:    vst1.64 {d18, d19}, [r3:128]
 ; CHECK-NEXT:    pop {r4, r5, r6, r7, r11, lr}
 ; CHECK-NEXT:    mov pc, lr
   %v0 = load %T0_18, %T0_18* %loadaddr
   %v1 = load %T0_18, %T0_18* %loadaddr2
   %c = icmp slt %T0_18 %v0, %v1
 ; COST: func_blend18
 ; COST: cost of 19 {{.*}} select
   %r = select %T1_18 %c, %T0_18 %v0, %T0_18 %v1
   store %T0_18 %r, %T0_18* %storeaddr
   ret void
 }
 %T0_19 = type <8 x i64>
 %T1_19 = type <8 x i1>
 define void @func_blend19(%T0_19* %loadaddr, %T0_19* %loadaddr2,
                            %T1_19* %blend, %T0_19* %storeaddr) {
 ; CHECK-LABEL: func_blend19:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    .save {r4, r5, r6, lr}
-; CHECK-NEXT:    push {r4, r5, r6, lr}
-; CHECK-NEXT:    mov r12, r1
-; CHECK-NEXT:    mov r2, r0
-; CHECK-NEXT:    vld1.64 {d24, d25}, [r12:128]!
-; CHECK-NEXT:    mov r6, #0
-; CHECK-NEXT:    mov lr, #0
-; CHECK-NEXT:    vld1.64 {d28, d29}, [r2:128]!
-; CHECK-NEXT:    vld1.64 {d16, d17}, [r12:128]
+; CHECK-NEXT:    .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT:    push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT:    add r2, r1, #48
+; CHECK-NEXT:    add r5, r1, #32
+; CHECK-NEXT:    vld1.64 {d16, d17}, [r2:128]
+; CHECK-NEXT:    add r2, r0, #48
+; CHECK-NEXT:    add r6, r0, #32
+; CHECK-NEXT:    mov r7, #0
 ; CHECK-NEXT:    vld1.64 {d18, d19}, [r2:128]
-; CHECK-NEXT:    add r2, r1, #32
-; CHECK-NEXT:    add r1, r1, #48
-; CHECK-NEXT:    vld1.64 {d20, d21}, [r2:128]
-; CHECK-NEXT:    add r2, r0, #32
-; CHECK-NEXT:    add r0, r0, #48
-; CHECK-NEXT:    vld1.64 {d30, d31}, [r2:128]
-; CHECK-NEXT:    vmov.32 r4, d16[0]
+; CHECK-NEXT:    vmov.32 r12, d16[0]
 ; CHECK-NEXT:    vmov.32 r2, d18[0]
-; CHECK-NEXT:    vmov.32 r12, d16[1]
-; CHECK-NEXT:    vmov.32 r5, d18[1]
-; CHECK-NEXT:    vld1.64 {d22, d23}, [r1:128]
-; CHECK-NEXT:    vmov.32 r1, d21[0]
-; CHECK-NEXT:    vld1.64 {d26, d27}, [r0:128]
-; CHECK-NEXT:    vmov.32 r0, d21[1]
-; CHECK-NEXT:    subs r2, r2, r4
-; CHECK-NEXT:    vmov.32 r4, d31[1]
-; CHECK-NEXT:    vmov.32 r2, d31[0]
-; CHECK-NEXT:    sbcs r5, r5, r12
+; CHECK-NEXT:    vmov.32 lr, d16[1]
+; CHECK-NEXT:    vmov.32 r4, d18[1]
+; CHECK-NEXT:    vld1.64 {d28, d29}, [r0:128]!
+; CHECK-NEXT:    vld1.64 {d26, d27}, [r5:128]
+; CHECK-NEXT:    vld1.64 {d30, d31}, [r6:128]
+; CHECK-NEXT:    vmov.32 r5, d17[0]
+; CHECK-NEXT:    vld1.64 {d22, d23}, [r0:128]
+; CHECK-NEXT:    vmov.32 r0, d17[1]
+; CHECK-NEXT:    vld1.64 {d24, d25}, [r1:128]!
+; CHECK-NEXT:    vld1.64 {d20, d21}, [r1:128]
+; CHECK-NEXT:    mov r1, #0
+; CHECK-NEXT:    subs r2, r2, r12
 ; CHECK-NEXT:    mov r12, #0
+; CHECK-NEXT:    vmov.32 r2, d19[0]
+; CHECK-NEXT:    sbcs r6, r4, lr
+; CHECK-NEXT:    vmov.32 r4, d24[0]
+; CHECK-NEXT:    vmov.32 r6, d19[1]
 ; CHECK-NEXT:    movlt r12, #1
 ; CHECK-NEXT:    cmp r12, #0
 ; CHECK-NEXT:    mvnne r12, #0
-; CHECK-NEXT:    vmov.32 r5, d25[0]
-; CHECK-NEXT:    subs r1, r2, r1
+; CHECK-NEXT:    subs r2, r2, r5
+; CHECK-NEXT:    vmov.32 r5, d28[0]
 ; CHECK-NEXT:    mov r2, #0
-; CHECK-NEXT:    sbcs r0, r4, r0
-; CHECK-NEXT:    vmov.32 r1, d29[0]
-; CHECK-NEXT:    vmov.32 r0, d25[1]
+; CHECK-NEXT:    sbcs r0, r6, r0
+; CHECK-NEXT:    vmov.32 r6, d28[1]
+; CHECK-NEXT:    vmov.32 r0, d24[1]
 ; CHECK-NEXT:    movlt r2, #1
-; CHECK-NEXT:    vmov.32 r4, d29[1]
 ; CHECK-NEXT:    cmp r2, #0
 ; CHECK-NEXT:    mvnne r2, #0
-; CHECK-NEXT:    vdup.32 d5, r2
-; CHECK-NEXT:    subs r1, r1, r5
-; CHECK-NEXT:    vmov.32 r5, d24[1]
-; CHECK-NEXT:    vmov.32 r1, d24[0]
-; CHECK-NEXT:    sbcs r0, r4, r0
-; CHECK-NEXT:    vmov.32 r4, d28[0]
+; CHECK-NEXT:    vdup.32 d7, r2
+; CHECK-NEXT:    vdup.32 d6, r12
+; CHECK-NEXT:    subs r5, r5, r4
+; CHECK-NEXT:    vmov.32 r4, d25[1]
+; CHECK-NEXT:    vmov.32 r5, d25[0]
+; CHECK-NEXT:    sbcs r0, r6, r0
+; CHECK-NEXT:    mov r6, #0
+; CHECK-NEXT:    vmov.32 r0, d29[0]
+; CHECK-NEXT:    movlt r6, #1
+; CHECK-NEXT:    cmp r6, #0
+; CHECK-NEXT:    mvnne r6, #0
+; CHECK-NEXT:    subs r0, r0, r5
+; CHECK-NEXT:    vmov.32 r5, d21[0]
+; CHECK-NEXT:    vmov.32 r0, d29[1]
+; CHECK-NEXT:    sbcs r0, r0, r4
+; CHECK-NEXT:    vmov.32 r4, d23[0]
 ; CHECK-NEXT:    mov r0, #0
 ; CHECK-NEXT:    movlt r0, #1
 ; CHECK-NEXT:    cmp r0, #0
 ; CHECK-NEXT:    mvnne r0, #0
 ; CHECK-NEXT:    vdup.32 d1, r0
-; CHECK-NEXT:    vmov.32 r0, d19[0]
-; CHECK-NEXT:    subs r1, r4, r1
-; CHECK-NEXT:    vmov.32 r4, d17[0]
-; CHECK-NEXT:    vmov.32 r1, d28[1]
-; CHECK-NEXT:    sbcs r1, r1, r5
-; CHECK-NEXT:    vmov.32 r5, d17[1]
-; CHECK-NEXT:    mov r1, #0
-; CHECK-NEXT:    movlt r1, #1
-; CHECK-NEXT:    cmp r1, #0
-; CHECK-NEXT:    mvnne r1, #0
-; CHECK-NEXT:    subs r0, r0, r4
-; CHECK-NEXT:    vmov.32 r0, d19[1]
-; CHECK-NEXT:    vmov.32 r4, d22[0]
-; CHECK-NEXT:    vdup.32 d0, r1
-; CHECK-NEXT:    vmov.32 r1, d22[1]
-; CHECK-NEXT:    vbsl q0, q14, q12
-; CHECK-NEXT:    sbcs r0, r0, r5
-; CHECK-NEXT:    vmov.32 r5, d26[0]
 ; CHECK-NEXT:    mov r0, #0
-; CHECK-NEXT:    movlt r0, #1
-; CHECK-NEXT:    subs r4, r5, r4
-; CHECK-NEXT:    vmov.32 r5, d20[0]
-; CHECK-NEXT:    vmov.32 r4, d26[1]
-; CHECK-NEXT:    sbcs r1, r4, r1
-; CHECK-NEXT:    vmov.32 r4, d30[0]
-; CHECK-NEXT:    mov r1, #0
-; CHECK-NEXT:    movlt r1, #1
-; CHECK-NEXT:    subs r4, r4, r5
-; CHECK-NEXT:    vmov.32 r5, d30[1]
-; CHECK-NEXT:    vmov.32 r4, d20[1]
-; CHECK-NEXT:    sbcs r4, r5, r4
-; CHECK-NEXT:    vmov.32 r5, d27[0]
-; CHECK-NEXT:    vmov.32 r4, d23[0]
-; CHECK-NEXT:    movlt r6, #1
-; CHECK-NEXT:    subs r4, r5, r4
-; CHECK-NEXT:    vmov.32 r5, d27[1]
+; CHECK-NEXT:    vdup.32 d0, r6
+; CHECK-NEXT:    vmov.32 r6, d22[0]
+; CHECK-NEXT:    vbit q12, q14, q0
+; CHECK-NEXT:    subs r5, r4, r5
 ; CHECK-NEXT:    vmov.32 r4, d23[1]
-; CHECK-NEXT:    sbcs r4, r5, r4
-; CHECK-NEXT:    movlt lr, #1
-; CHECK-NEXT:    cmp lr, #0
-; CHECK-NEXT:    mvnne lr, #0
-; CHECK-NEXT:    cmp r6, #0
-; CHECK-NEXT:    mvnne r6, #0
-; CHECK-NEXT:    cmp r1, #0
-; CHECK-NEXT:    mvnne r1, #0
+; CHECK-NEXT:    vmov.32 r5, d21[1]
+; CHECK-NEXT:    sbcs r5, r4, r5
+; CHECK-NEXT:    vmov.32 r4, d20[1]
+; CHECK-NEXT:    vmov.32 r5, d20[0]
+; CHECK-NEXT:    movlt r0, #1
 ; CHECK-NEXT:    cmp r0, #0
-; CHECK-NEXT:    vdup.32 d4, r6
 ; CHECK-NEXT:    mvnne r0, #0
-; CHECK-NEXT:    vdup.32 d3, lr
-; CHECK-NEXT:    vbsl q2, q15, q10
-; CHECK-NEXT:    vdup.32 d21, r0
+; CHECK-NEXT:    vdup.32 d5, r0
 ; CHECK-NEXT:    add r0, r3, #32
+; CHECK-NEXT:    subs r6, r6, r5
+; CHECK-NEXT:    vmov.32 r5, d26[0]
+; CHECK-NEXT:    vmov.32 r6, d22[1]
+; CHECK-NEXT:    sbcs r6, r6, r4
+; CHECK-NEXT:    mov r4, #0
+; CHECK-NEXT:    vmov.32 r6, d30[0]
+; CHECK-NEXT:    movlt r4, #1
+; CHECK-NEXT:    subs r6, r6, r5
+; CHECK-NEXT:    vmov.32 r5, d30[1]
+; CHECK-NEXT:    vmov.32 r6, d26[1]
+; CHECK-NEXT:    sbcs r6, r5, r6
+; CHECK-NEXT:    vmov.32 r5, d31[0]
+; CHECK-NEXT:    vmov.32 r6, d27[0]
+; CHECK-NEXT:    movlt r1, #1
+; CHECK-NEXT:    subs r6, r5, r6
+; CHECK-NEXT:    vmov.32 r5, d31[1]
+; CHECK-NEXT:    vmov.32 r6, d27[1]
+; CHECK-NEXT:    sbcs r6, r5, r6
+; CHECK-NEXT:    movlt r7, #1
+; CHECK-NEXT:    cmp r7, #0
+; CHECK-NEXT:    mvnne r7, #0
+; CHECK-NEXT:    cmp r1, #0
+; CHECK-NEXT:    mvnne r1, #0
+; CHECK-NEXT:    vdup.32 d3, r7
+; CHECK-NEXT:    cmp r4, #0
 ; CHECK-NEXT:    vdup.32 d2, r1
-; CHECK-NEXT:    vdup.32 d20, r12
-; CHECK-NEXT:    vbsl q1, q13, q11
-; CHECK-NEXT:    vst1.64 {d4, d5}, [r0:128]
+; CHECK-NEXT:    mvnne r4, #0
+; CHECK-NEXT:    vbit q13, q15, q1
+; CHECK-NEXT:    vdup.32 d4, r4
+; CHECK-NEXT:    vbit q10, q11, q2
+; CHECK-NEXT:    vbit q8, q9, q3
+; CHECK-NEXT:    vst1.64 {d26, d27}, [r0:128]
 ; CHECK-NEXT:    add r0, r3, #48
-; CHECK-NEXT:    vbsl q10, q9, q8
-; CHECK-NEXT:    vst1.64 {d0, d1}, [r3:128]!
-; CHECK-NEXT:    vst1.64 {d2, d3}, [r0:128]
+; CHECK-NEXT:    vst1.64 {d24, d25}, [r3:128]!
+; CHECK-NEXT:    vst1.64 {d16, d17}, [r0:128]
 ; CHECK-NEXT:    vst1.64 {d20, d21}, [r3:128]
-; CHECK-NEXT:    pop {r4, r5, r6, lr}
+; CHECK-NEXT:    pop {r4, r5, r6, r7, r11, lr}
 ; CHECK-NEXT:    mov pc, lr
   %v0 = load %T0_19, %T0_19* %loadaddr
   %v1 = load %T0_19, %T0_19* %loadaddr2
   %c = icmp slt %T0_19 %v0, %v1
 ; COST: func_blend19
 ; COST: cost of 50 {{.*}} select
   %r = select %T1_19 %c, %T0_19 %v0, %T0_19 %v1
   store %T0_19 %r, %T0_19* %storeaddr
   ret void
 }
 %T0_20 = type <16 x i64>
 %T1_20 = type <16 x i1>
 define void @func_blend20(%T0_20* %loadaddr, %T0_20* %loadaddr2,
                            %T1_20* %blend, %T0_20* %storeaddr) {
 ; CHECK-LABEL: func_blend20:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
 ; CHECK-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
 ; CHECK-NEXT:    .pad #4
 ; CHECK-NEXT:    sub sp, sp, #4
 ; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
 ; CHECK-NEXT:    vpush {d8, d9, d10, d11}
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, sp, #8
-; CHECK-NEXT:    add r9, r1, #64
-; CHECK-NEXT:    mov r2, #32
-; CHECK-NEXT:    add r8, r0, #64
-; CHECK-NEXT:    vld1.64 {d18, d19}, [r9:128], r2
-; CHECK-NEXT:    mov r10, #0
-; CHECK-NEXT:    vld1.64 {d22, d23}, [r8:128], r2
-; CHECK-NEXT:    vmov.32 r2, d19[0]
+; CHECK-NEXT:    mov r8, r1
+; CHECK-NEXT:    mov r9, r0
+; CHECK-NEXT:    vld1.64 {d16, d17}, [r8:128]!
+; CHECK-NEXT:    add r10, r0, #64
+; CHECK-NEXT:    vld1.64 {d18, d19}, [r9:128]!
+; CHECK-NEXT:    vmov.32 r2, d16[0]
 ; CHECK-NEXT:    str r3, [sp, #4] @ 4-byte Spill
-; CHECK-NEXT:    vmov.32 r7, d23[0]
-; CHECK-NEXT:    mov r3, #0
-; CHECK-NEXT:    vmov.32 r5, d19[1]
-; CHECK-NEXT:    vmov.32 r6, d23[1]
-; CHECK-NEXT:    vld1.64 {d2, d3}, [r9:128]!
-; CHECK-NEXT:    vmov.32 r12, d2[0]
-; CHECK-NEXT:    subs r2, r7, r2
-; CHECK-NEXT:    mov r7, r1
-; CHECK-NEXT:    vld1.64 {d20, d21}, [r7:128]!
-; CHECK-NEXT:    sbcs r2, r6, r5
-; CHECK-NEXT:    vmov.32 r5, d18[0]
+; CHECK-NEXT:    vmov.32 r6, d18[0]
+; CHECK-NEXT:    vmov.32 r4, d16[1]
+; CHECK-NEXT:    vmov.32 r7, d18[1]
+; CHECK-NEXT:    vmov.32 r5, d17[0]
+; CHECK-NEXT:    subs r2, r6, r2
+; CHECK-NEXT:    mov r6, #0
+; CHECK-NEXT:    vmov.32 r2, d19[0]
+; CHECK-NEXT:    sbcs r7, r7, r4
+; CHECK-NEXT:    movlt r6, #1
+; CHECK-NEXT:    vmov.32 r7, d17[1]
+; CHECK-NEXT:    subs r2, r2, r5
+; CHECK-NEXT:    vmov.32 r2, d19[1]
+; CHECK-NEXT:    sbcs r2, r2, r7
 ; CHECK-NEXT:    mov r2, #0
-; CHECK-NEXT:    vmov.32 r6, d22[0]
 ; CHECK-NEXT:    movlt r2, #1
 ; CHECK-NEXT:    cmp r2, #0
-; CHECK-NEXT:    vld1.64 {d0, d1}, [r7:128]
 ; CHECK-NEXT:    mvnne r2, #0
-; CHECK-NEXT:    vdup.32 d17, r2
-; CHECK-NEXT:    mov r2, r0
-; CHECK-NEXT:    subs r5, r6, r5
-; CHECK-NEXT:    vmov.32 r6, d22[1]
-; CHECK-NEXT:    vmov.32 r5, d18[1]
-; CHECK-NEXT:    sbcs r5, r6, r5
-; CHECK-NEXT:    mov r5, #0
-; CHECK-NEXT:    movlt r5, #1
-; CHECK-NEXT:    cmp r5, #0
-; CHECK-NEXT:    mvnne r5, #0
-; CHECK-NEXT:    vdup.32 d16, r5
-; CHECK-NEXT:    vbsl q8, q11, q9
-; CHECK-NEXT:    vld1.64 {d22, d23}, [r2:128]!
-; CHECK-NEXT:    vmov.32 r5, d21[0]
-; CHECK-NEXT:    vmov.32 r6, d23[0]
-; CHECK-NEXT:    vld1.64 {d30, d31}, [r2:128]
-; CHECK-NEXT:    vmov.32 r2, d1[0]
-; CHECK-NEXT:    vmov.32 r7, d30[0]
-; CHECK-NEXT:    subs r5, r6, r5
-; CHECK-NEXT:    vmov.32 r6, d23[1]
-; CHECK-NEXT:    vmov.32 r5, d21[1]
-; CHECK-NEXT:    sbcs r5, r6, r5
-; CHECK-NEXT:    vmov.32 r6, d22[0]
-; CHECK-NEXT:    mov r5, #0
-; CHECK-NEXT:    movlt r5, #1
-; CHECK-NEXT:    cmp r5, #0
-; CHECK-NEXT:    mvnne r5, #0
-; CHECK-NEXT:    vdup.32 d19, r5
-; CHECK-NEXT:    vmov.32 r5, d20[0]
+; CHECK-NEXT:    cmp r6, #0
+; CHECK-NEXT:    vdup.32 d21, r2
+; CHECK-NEXT:    mvnne r6, #0
+; CHECK-NEXT:    vdup.32 d20, r6
+; CHECK-NEXT:    mov r2, #32
+; CHECK-NEXT:    add r6, r1, #64
+; CHECK-NEXT:    vld1.64 {d24, d25}, [r10:128], r2
+; CHECK-NEXT:    vbit q8, q9, q10
+; CHECK-NEXT:    vld1.64 {d28, d29}, [r6:128], r2
+; CHECK-NEXT:    vmov.32 r4, d29[0]
+; CHECK-NEXT:    vmov.32 r5, d25[0]
+; CHECK-NEXT:    vld1.64 {d0, d1}, [r9:128]
+; CHECK-NEXT:    vld1.64 {d2, d3}, [r8:128]
+; CHECK-NEXT:    vld1.64 {d22, d23}, [r6:128]!
+; CHECK-NEXT:    vld1.64 {d20, d21}, [r6:128]
+; CHECK-NEXT:    vmov.32 r6, d0[0]
+; CHECK-NEXT:    vld1.64 {d18, d19}, [r10:128]!
+; CHECK-NEXT:    vmov.32 r9, d23[0]
+; CHECK-NEXT:    vmov.32 r11, d19[0]
+; CHECK-NEXT:    vmov.32 r8, d23[1]
+; CHECK-NEXT:    subs r4, r5, r4
+; CHECK-NEXT:    vmov.32 r5, d25[1]
+; CHECK-NEXT:    vmov.32 r4, d29[1]
+; CHECK-NEXT:    sbcs r4, r5, r4
+; CHECK-NEXT:    vmov.32 r5, d24[0]
+; CHECK-NEXT:    mov r4, #0
+; CHECK-NEXT:    movlt r4, #1
+; CHECK-NEXT:    cmp r4, #0
+; CHECK-NEXT:    mvnne r4, #0
+; CHECK-NEXT:    vdup.32 d5, r4
+; CHECK-NEXT:    vmov.32 r4, d28[0]
+; CHECK-NEXT:    subs r4, r5, r4
+; CHECK-NEXT:    vmov.32 r5, d24[1]
+; CHECK-NEXT:    vmov.32 r4, d28[1]
+; CHECK-NEXT:    sbcs r4, r5, r4
+; CHECK-NEXT:    vmov.32 r5, d1[0]
+; CHECK-NEXT:    mov r4, #0
+; CHECK-NEXT:    movlt r4, #1
+; CHECK-NEXT:    cmp r4, #0
+; CHECK-NEXT:    mvnne r4, #0
+; CHECK-NEXT:    vdup.32 d4, r4
+; CHECK-NEXT:    vmov.32 r4, d3[0]
+; CHECK-NEXT:    subs r4, r5, r4
+; CHECK-NEXT:    vmov.32 r5, d1[1]
+; CHECK-NEXT:    vmov.32 r4, d3[1]
+; CHECK-NEXT:    sbcs r4, r5, r4
+; CHECK-NEXT:    add r5, r1, #32
+; CHECK-NEXT:    vld1.64 {d26, d27}, [r5:128]
+; CHECK-NEXT:    add r5, r1, #48
+; CHECK-NEXT:    mov r4, #0
+; CHECK-NEXT:    add r1, r1, #80
+; CHECK-NEXT:    vld1.64 {d30, d31}, [r5:128]
+; CHECK-NEXT:    movlt r4, #1
+; CHECK-NEXT:    cmp r4, #0
+; CHECK-NEXT:    vbif q12, q14, q2
+; CHECK-NEXT:    vmov.32 r5, d2[0]
+; CHECK-NEXT:    mvnne r4, #0
+; CHECK-NEXT:    vdup.32 d29, r4
+; CHECK-NEXT:    vmov.32 r4, d31[1]
 ; CHECK-NEXT:    subs r5, r6, r5
-; CHECK-NEXT:    vmov.32 r6, d22[1]
-; CHECK-NEXT:    vmov.32 r5, d20[1]
+; CHECK-NEXT:    vmov.32 r6, d0[1]
+; CHECK-NEXT:    vmov.32 r5, d2[1]
 ; CHECK-NEXT:    sbcs r5, r6, r5
+; CHECK-NEXT:    add r6, r0, #48
 ; CHECK-NEXT:    mov r5, #0
+; CHECK-NEXT:    vld1.64 {d6, d7}, [r6:128]
 ; CHECK-NEXT:    movlt r5, #1
 ; CHECK-NEXT:    cmp r5, #0
 ; CHECK-NEXT:    mvnne r5, #0
-; CHECK-NEXT:    vdup.32 d18, r5
-; CHECK-NEXT:    add r5, r0, #32
-; CHECK-NEXT:    vbsl q9, q11, q10
-; CHECK-NEXT:    vld1.64 {d22, d23}, [r5:128]
-; CHECK-NEXT:    add r5, r1, #32
-; CHECK-NEXT:    vld1.64 {d24, d25}, [r5:128]
-; CHECK-NEXT:    vmov.32 r5, d24[0]
-; CHECK-NEXT:    vmov.32 r6, d22[0]
-; CHECK-NEXT:    vmov.32 r4, d23[0]
-; CHECK-NEXT:    vld1.64 {d20, d21}, [r8:128]!
-; CHECK-NEXT:    vmov.32 r11, d21[0]
-; CHECK-NEXT:    subs r5, r6, r5
-; CHECK-NEXT:    vmov.32 r6, d22[1]
-; CHECK-NEXT:    vmov.32 r5, d24[1]
-; CHECK-NEXT:    sbcs r5, r6, r5
-; CHECK-NEXT:    vmov.32 r6, d25[0]
-; CHECK-NEXT:    movlt r10, #1
-; CHECK-NEXT:    cmp r10, #0
-; CHECK-NEXT:    mvnne r10, #0
-; CHECK-NEXT:    subs r4, r4, r6
-; CHECK-NEXT:    vmov.32 r6, d23[1]
-; CHECK-NEXT:    vmov.32 r4, d25[1]
+; CHECK-NEXT:    vmov.32 r7, d7[0]
+; CHECK-NEXT:    vdup.32 d28, r5
+; CHECK-NEXT:    vmov.32 r5, d31[0]
+; CHECK-NEXT:    vbsl q14, q0, q1
+; CHECK-NEXT:    vmov.32 r6, d7[1]
+; CHECK-NEXT:    vmov.32 r2, d6[0]
+; CHECK-NEXT:    subs r5, r7, r5
+; CHECK-NEXT:    vmov.32 r7, d6[1]
 ; CHECK-NEXT:    sbcs r4, r6, r4
-; CHECK-NEXT:    mov r6, #0
-; CHECK-NEXT:    vmov.32 r4, d31[0]
-; CHECK-NEXT:    movlt r6, #1
-; CHECK-NEXT:    cmp r6, #0
-; CHECK-NEXT:    mvnne r6, #0
-; CHECK-NEXT:    subs r2, r4, r2
-; CHECK-NEXT:    vmov.32 r4, d31[1]
-; CHECK-NEXT:    vmov.32 r2, d1[1]
-; CHECK-NEXT:    sbcs r2, r4, r2
+; CHECK-NEXT:    vmov.32 r6, d30[0]
+; CHECK-NEXT:    vmov.32 r5, d30[1]
+; CHECK-NEXT:    mov r4, #0
+; CHECK-NEXT:    movlt r4, #1
+; CHECK-NEXT:    cmp r4, #0
+; CHECK-NEXT:    mvnne r4, #0
+; CHECK-NEXT:    vdup.32 d3, r4
+; CHECK-NEXT:    vmov.32 r4, d26[1]
+; CHECK-NEXT:    subs r2, r2, r6
+; CHECK-NEXT:    sbcs r2, r7, r5
+; CHECK-NEXT:    add r5, r0, #32
 ; CHECK-NEXT:    mov r2, #0
+; CHECK-NEXT:    vld1.64 {d0, d1}, [r5:128]
 ; CHECK-NEXT:    movlt r2, #1
 ; CHECK-NEXT:    cmp r2, #0
 ; CHECK-NEXT:    mvnne r2, #0
-; CHECK-NEXT:    vdup.32 d27, r2
-; CHECK-NEXT:    add r2, r0, #48
-; CHECK-NEXT:    vld1.64 {d4, d5}, [r2:128]
-; CHECK-NEXT:    add r2, r1, #48
+; CHECK-NEXT:    vmov.32 r6, d0[0]
+; CHECK-NEXT:    vdup.32 d2, r2
 ; CHECK-NEXT:    add r0, r0, #80
-; CHECK-NEXT:    add r1, r1, #80
-; CHECK-NEXT:    vld1.64 {d6, d7}, [r2:128]
-; CHECK-NEXT:    vmov.32 r2, d7[0]
-; CHECK-NEXT:    vmov.32 r4, d5[0]
-; CHECK-NEXT:    vmov.32 r5, d4[0]
+; CHECK-NEXT:    vmov.32 r2, d26[0]
+; CHECK-NEXT:    vbit q15, q3, q1
+; CHECK-NEXT:    vmov.32 r5, d0[1]
+; CHECK-NEXT:    vmov.32 r7, d1[0]
+; CHECK-NEXT:    vld1.64 {d2, d3}, [r10:128]
+; CHECK-NEXT:    vld1.64 {d6, d7}, [r1:128]
 ; CHECK-NEXT:    vld1.64 {d8, d9}, [r0:128]
-; CHECK-NEXT:    subs r2, r4, r2
-; CHECK-NEXT:    vmov.32 r4, d5[1]
-; CHECK-NEXT:    vmov.32 r2, d7[1]
-; CHECK-NEXT:    sbcs r2, r4, r2
-; CHECK-NEXT:    vmov.32 r4, d0[0]
+; CHECK-NEXT:    vmov.32 r1, d7[1]
+; CHECK-NEXT:    vmov.32 r10, d19[1]
+; CHECK-NEXT:    vmov.32 lr, d6[0]
+; CHECK-NEXT:    vmov.32 r3, d8[0]
+; CHECK-NEXT:    vmov.32 r12, d8[1]
+; CHECK-NEXT:    subs r2, r6, r2
+; CHECK-NEXT:    vmov.32 r6, d1[1]
+; CHECK-NEXT:    sbcs r2, r5, r4
+; CHECK-NEXT:    vmov.32 r5, d27[0]
+; CHECK-NEXT:    vmov.32 r4, d27[1]
 ; CHECK-NEXT:    mov r2, #0
 ; CHECK-NEXT:    movlt r2, #1
 ; CHECK-NEXT:    cmp r2, #0
 ; CHECK-NEXT:    mvnne r2, #0
-; CHECK-NEXT:    vdup.32 d29, r2
-; CHECK-NEXT:    vmov.32 r2, d6[1]
-; CHECK-NEXT:    subs r4, r7, r4
-; CHECK-NEXT:    vmov.32 r7, d30[1]
-; CHECK-NEXT:    vmov.32 r4, d0[1]
-; CHECK-NEXT:    sbcs r4, r7, r4
-; CHECK-NEXT:    vmov.32 r7, d4[1]
+; CHECK-NEXT:    subs r5, r7, r5
+; CHECK-NEXT:    vmov.32 r7, d7[0]
+; CHECK-NEXT:    sbcs r4, r6, r4
+; CHECK-NEXT:    vmov.32 r6, d2[0]
 ; CHECK-NEXT:    mov r4, #0
+; CHECK-NEXT:    vmov.32 r5, d2[1]
 ; CHECK-NEXT:    movlt r4, #1
 ; CHECK-NEXT:    cmp r4, #0
 ; CHECK-NEXT:    mvnne r4, #0
-; CHECK-NEXT:    vdup.32 d26, r4
-; CHECK-NEXT:    vmov.32 r4, d6[0]
-; CHECK-NEXT:    vbsl q13, q15, q0
-; CHECK-NEXT:    vld1.64 {d0, d1}, [r9:128]
-; CHECK-NEXT:    vdup.32 d31, r6
-; CHECK-NEXT:    vmov.32 r9, d3[0]
-; CHECK-NEXT:    vdup.32 d30, r10
-; CHECK-NEXT:    vmov.32 r10, d21[1]
-; CHECK-NEXT:    vbsl q15, q11, q12
-; CHECK-NEXT:    subs r4, r5, r4
-; CHECK-NEXT:    sbcs r2, r7, r2
-; CHECK-NEXT:    vmov.32 r4, d0[1]
-; CHECK-NEXT:    mov r2, #0
-; CHECK-NEXT:    movlt r2, #1
-; CHECK-NEXT:    cmp r2, #0
-; CHECK-NEXT:    mvnne r2, #0
-; CHECK-NEXT:    vdup.32 d28, r2
-; CHECK-NEXT:    vbsl q14, q2, q3
-; CHECK-NEXT:    vld1.64 {d4, d5}, [r8:128]
-; CHECK-NEXT:    vmov.32 r2, d0[0]
-; CHECK-NEXT:    vmov.32 r6, d4[0]
-; CHECK-NEXT:    vmov.32 r5, d4[1]
-; CHECK-NEXT:    vld1.64 {d6, d7}, [r1:128]
-; CHECK-NEXT:    vmov.32 r7, d7[0]
-; CHECK-NEXT:    vmov.32 r1, d7[1]
-; CHECK-NEXT:    vmov.32 lr, d5[0]
-; CHECK-NEXT:    vmov.32 r8, d3[1]
+; CHECK-NEXT:    vdup.32 d5, r4
+; CHECK-NEXT:    vdup.32 d4, r2
+; CHECK-NEXT:    vmov.32 r2, d20[0]
+; CHECK-NEXT:    vbit q13, q0, q2
+; CHECK-NEXT:    vmov.32 r4, d20[1]
 ; CHECK-NEXT:    subs r0, r6, r2
 ; CHECK-NEXT:    vmov.32 r2, d9[1]
 ; CHECK-NEXT:    sbcs r0, r5, r4
 ; CHECK-NEXT:    vmov.32 r4, d9[0]
-; CHECK-NEXT:    movlt r3, #1
-; CHECK-NEXT:    cmp r3, #0
-; CHECK-NEXT:    mvnne r3, #0
-; CHECK-NEXT:    vmov.32 r6, d8[1]
-; CHECK-NEXT:    mov r5, #0
-; CHECK-NEXT:    vmov.32 r0, d5[1]
+; CHECK-NEXT:    mov r0, #0
+; CHECK-NEXT:    vmov.32 r6, d18[0]
+; CHECK-NEXT:    movlt r0, #1
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    mvnne r0, #0
+; CHECK-NEXT:    vmov.32 r5, d18[1]
 ; CHECK-NEXT:    subs r4, r4, r7
-; CHECK-NEXT:    vmov.32 r7, d2[1]
+; CHECK-NEXT:    vmov.32 r7, d21[1]
 ; CHECK-NEXT:    sbcs r1, r2, r1
-; CHECK-NEXT:    vmov.32 r2, d8[0]
-; CHECK-NEXT:    vmov.32 r1, d6[0]
-; CHECK-NEXT:    movlt r5, #1
-; CHECK-NEXT:    vmov.32 r4, d6[1]
-; CHECK-NEXT:    cmp r5, #0
-; CHECK-NEXT:    mvnne r5, #0
-; CHECK-NEXT:    vdup.32 d11, r5
-; CHECK-NEXT:    vmov.32 r5, d20[0]
-; CHECK-NEXT:    subs r1, r2, r1
-; CHECK-NEXT:    vmov.32 r2, d1[0]
-; CHECK-NEXT:    sbcs r1, r6, r4
-; CHECK-NEXT:    vmov.32 r6, d1[1]
-; CHECK-NEXT:    vmov.32 r4, d20[1]
+; CHECK-NEXT:    vmov.32 r4, d22[1]
+; CHECK-NEXT:    vmov.32 r1, d22[0]
+; CHECK-NEXT:    mov r2, #0
+; CHECK-NEXT:    movlt r2, #1
+; CHECK-NEXT:    cmp r2, #0
+; CHECK-NEXT:    mvnne r2, #0
+; CHECK-NEXT:    vdup.32 d11, r2
+; CHECK-NEXT:    vmov.32 r2, d3[1]
+; CHECK-NEXT:    subs r1, r6, r1
+; CHECK-NEXT:    vmov.32 r6, d21[0]
+; CHECK-NEXT:    sbcs r1, r5, r4
+; CHECK-NEXT:    vmov.32 r4, d3[0]
+; CHECK-NEXT:    vmov.32 r5, d6[1]
 ; CHECK-NEXT:    mov r1, #0
 ; CHECK-NEXT:    movlt r1, #1
 ; CHECK-NEXT:    cmp r1, #0
 ; CHECK-NEXT:    mvnne r1, #0
-; CHECK-NEXT:    vdup.32 d10, r1
-; CHECK-NEXT:    mov r1, #0
-; CHECK-NEXT:    vbsl q5, q4, q3
-; CHECK-NEXT:    subs r2, lr, r2
-; CHECK-NEXT:    sbcs r0, r0, r6
-; CHECK-NEXT:    mov r0, #0
-; CHECK-NEXT:    movlt r0, #1
-; CHECK-NEXT:    subs r2, r5, r12
-; CHECK-NEXT:    sbcs r2, r4, r7
+; CHECK-NEXT:    subs r4, r4, r6
+; CHECK-NEXT:    sbcs r2, r2, r7
 ; CHECK-NEXT:    mov r2, #0
 ; CHECK-NEXT:    movlt r2, #1
-; CHECK-NEXT:    subs r7, r11, r9
-; CHECK-NEXT:    sbcs r7, r10, r8
-; CHECK-NEXT:    movlt r1, #1
-; CHECK-NEXT:    cmp r1, #0
-; CHECK-NEXT:    mvnne r1, #0
+; CHECK-NEXT:    subs r4, r11, r9
+; CHECK-NEXT:    sbcs r4, r10, r8
+; CHECK-NEXT:    mov r4, #0
+; CHECK-NEXT:    movlt r4, #1
+; CHECK-NEXT:    subs r3, r3, lr
+; CHECK-NEXT:    sbcs r3, r12, r5
+; CHECK-NEXT:    mov r3, #0
+; CHECK-NEXT:    movlt r3, #1
+; CHECK-NEXT:    cmp r3, #0
+; CHECK-NEXT:    mvnne r3, #0
+; CHECK-NEXT:    cmp r4, #0
+; CHECK-NEXT:    mvnne r4, #0
+; CHECK-NEXT:    vdup.32 d10, r3
+; CHECK-NEXT:    vdup.32 d1, r4
+; CHECK-NEXT:    vorr q2, q5, q5
 ; CHECK-NEXT:    cmp r2, #0
-; CHECK-NEXT:    vdup.32 d23, r1
+; CHECK-NEXT:    vdup.32 d0, r1
+; CHECK-NEXT:    vbsl q2, q4, q3
 ; CHECK-NEXT:    mvnne r2, #0
-; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    vbif q9, q11, q0
 ; CHECK-NEXT:    ldr r1, [sp, #4] @ 4-byte Reload
-; CHECK-NEXT:    mvnne r0, #0
-; CHECK-NEXT:    vdup.32 d22, r2
-; CHECK-NEXT:    vdup.32 d25, r0
+; CHECK-NEXT:    vdup.32 d7, r2
+; CHECK-NEXT:    vdup.32 d6, r0
 ; CHECK-NEXT:    add r0, r1, #80
-; CHECK-NEXT:    vbsl q11, q10, q1
-; CHECK-NEXT:    vdup.32 d24, r3
-; CHECK-NEXT:    vst1.64 {d10, d11}, [r0:128]
+; CHECK-NEXT:    vbit q10, q1, q3
+; CHECK-NEXT:    vst1.64 {d4, d5}, [r0:128]
 ; CHECK-NEXT:    add r0, r1, #32
-; CHECK-NEXT:    vbsl q12, q2, q0
-; CHECK-NEXT:    vst1.64 {d30, d31}, [r0:128]
+; CHECK-NEXT:    vst1.64 {d26, d27}, [r0:128]
 ; CHECK-NEXT:    add r0, r1, #48
-; CHECK-NEXT:    vst1.64 {d28, d29}, [r0:128]
+; CHECK-NEXT:    vst1.64 {d30, d31}, [r0:128]
 ; CHECK-NEXT:    add r0, r1, #64
-; CHECK-NEXT:    vst1.64 {d18, d19}, [r1:128]!
-; CHECK-NEXT:    vst1.64 {d26, d27}, [r1:128]
+; CHECK-NEXT:    vst1.64 {d16, d17}, [r1:128]!
+; CHECK-NEXT:    vst1.64 {d28, d29}, [r1:128]
 ; CHECK-NEXT:    mov r1, #32
-; CHECK-NEXT:    vst1.64 {d16, d17}, [r0:128], r1
-; CHECK-NEXT:    vst1.64 {d22, d23}, [r0:128]!
-; CHECK-NEXT:    vst1.64 {d24, d25}, [r0:128]
+; CHECK-NEXT:    vst1.64 {d24, d25}, [r0:128], r1
+; CHECK-NEXT:    vst1.64 {d18, d19}, [r0:128]!
+; CHECK-NEXT:    vst1.64 {d20, d21}, [r0:128]
 ; CHECK-NEXT:    add sp, sp, #8
 ; CHECK-NEXT:    vpop {d8, d9, d10, d11}
 ; CHECK-NEXT:    add sp, sp, #4
 ; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, r11, lr}
 ; CHECK-NEXT:    mov pc, lr
   %v0 = load %T0_20, %T0_20* %loadaddr
   %v1 = load %T0_20, %T0_20* %loadaddr2
   %c = icmp slt %T0_20 %v0, %v1
 ; COST: func_blend20
 ; COST: cost of 100 {{.*}} select
   %r = select %T1_20 %c, %T0_20 %v0, %T0_20 %v1
   store %T0_20 %r, %T0_20* %storeaddr
   ret void
 }

llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll

 define double @copysign_d(double %a, double %b) {
 ; CHECK-LABEL: copysign_d:
 ; SOFT: lsrs [[REG:r[0-9]+]], r3, #31
 ; SOFT: bfi r1, [[REG]], #31, #1
 ; VFP: lsrs [[REG:r[0-9]+]], r3, #31
 ; VFP: bfi r1, [[REG]], #31, #1
 ; NEON:         vmov.i32 d16, #0x80000000
 ; NEON-NEXT:    vshl.i64 d16, d16, #32
-; NEON-NEXT:    vbsl d16, d1, d0
-; NEON-NEXT:    vorr d0, d16, d16
+; NEON-NEXT:    vbit d0, d1, d16
 ; NEON-NEXT:    bx lr
   %1 = call double @llvm.copysign.f64(double %a, double %b)
   ret double %1
 }
 
 declare double     @llvm.floor.f64(double %Val)
 define double @floor_d(double %a) {
 ; CHECK-LABEL: floor_d:

llvm/test/CodeGen/Thumb2/float-intrinsics-float.ll

 ; CHECK-LABEL: copysign_f:
 ; NONE: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31
 ; NONE: bfi r{{[0-9]+}}, [[REG]], #31, #1
 ; SP: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31
 ; SP: bfi r{{[0-9]+}}, [[REG]], #31, #1
 ; VFP: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31
 ; VFP: bfi r{{[0-9]+}}, [[REG]], #31, #1
 ; NEON-A7:       @ %bb.0:
-; NEON-A7-NEXT:    vmov.f32 s4, s1
+; NEON-A7-NEXT:    vmov.f32 s2, s1
 ; NEON-A7-NEXT:    @ kill: def $s0 killed $s0 def $d0
-; NEON-A7-NEXT:    vmov.i32 d1, #0x80000000
-; NEON-A7-NEXT:    vbsl d1, d2, d0
-; NEON-A7-NEXT:    vmov.f32 s0, s2
+; NEON-A7-NEXT:    vmov.i32 d16, #0x80000000
+; NEON-A7-NEXT:    vbit d0, d1, d16
+; NEON-A7-NEXT:    @ kill: def $s0 killed $s0 killed $d0
 ; NEON-A7-NEXT:    bx lr
 ; NEON-A57:       @ %bb.0:
-; NEON-A57-NEXT:    vmov.f32 s4, s1
-; NEON-A57-NEXT:    vmov.i32 d1, #0x80000000
+; NEON-A57-NEXT:    vmov.f32 s2, s1
+; NEON-A57-NEXT:    vmov.i32 d16, #0x80000000
 ; NEON-A57-NEXT:    @ kill: def $s0 killed $s0 def $d0
-; NEON-A57-NEXT:    vbsl d1, d2, d0
-; NEON-A57-NEXT:    vmov.f32 s0, s2
+; NEON-A57-NEXT:    vbit d0, d1, d16
+; NEON-A57-NEXT:    @ kill: def $s0 killed $s0 killed $d0
 ; NEON-A57-NEXT:    bx lr
   %1 = call float @llvm.copysign.f32(float %a, float %b)
   ret float %1
 }
 
 declare float     @llvm.floor.f32(float %Val)
 define float @floor_f(float %a) {
 ; CHECK-LABEL: floor_f:

llvm/test/MC/ARM/neon-bitwise-encoding.s

@ CHECK: vorn  q8, q8, q9              @ encoding: [0xf2,0x01,0x70,0xf2]
   vmvn  d16, d16
   vmvn  q8, q8
 
 @ CHECK: vmvn  d16, d16                @ encoding: [0xa0,0x05,0xf0,0xf3]
 @ CHECK: vmvn  q8, q8                  @ encoding: [0xe0,0x05,0xf0,0xf3]
 
   vbsl  d18, d17, d16
   vbsl  q8, q10, q9
+  vbit  d18, d17, d16
+  vbit  q8, q10, q9
+  vbif  d18, d17, d16
+  vbif  q8, q10, q9
 
 @ CHECK: vbsl  d18, d17, d16           @ encoding: [0xb0,0x21,0x51,0xf3]
 @ CHECK: vbsl  q8, q10, q9             @ encoding: [0xf2,0x01,0x54,0xf3]
-
+@ CHECK: vbit  d18, d17, d16           @ encoding: [0xb0,0x21,0x61,0xf3]
+@ CHECK: vbit  q8, q10, q9             @ encoding: [0xf2,0x01,0x64,0xf3]
+@ CHECK: vbif  d18, d17, d16           @ encoding: [0xb0,0x21,0x71,0xf3]
+@ CHECK: vbif  q8, q10, q9             @ encoding: [0xf2,0x01,0x74,0xf3]
 
 @ Size suffices are optional.
         veor q4, q7, q3
         veor.8 q4, q7, q3
         veor.16 q4, q7, q3
         veor.32 q4, q7, q3
         veor.64 q4, q7, q3
 

llvm/test/MC/ARM/neont2-bitwise-encoding.s

@ CHECK: vorn  q8, q8, q9              @ encoding: [0x70,0xef,0xf2,0x01]
   vmvn  q8, q8
 
 @ CHECK: vmvn  d16, d16                @ encoding: [0xf0,0xff,0xa0,0x05]
 @ CHECK: vmvn  q8, q8                  @ encoding: [0xf0,0xff,0xe0,0x05]
 
 
   vbsl  d18, d17, d16
   vbsl  q8, q10, q9
+  vbit  d18, d17, d16
+  vbit  q8, q10, q9
+  vbif  d18, d17, d16
+  vbif  q8, q10, q9
 
 @ CHECK: vbsl  d18, d17, d16           @ encoding: [0x51,0xff,0xb0,0x21]
 @ CHECK: vbsl  q8, q10, q9             @ encoding: [0x54,0xff,0xf2,0x01]
+@ CHECK: vbit  d18, d17, d16           @ encoding: [0x61,0xff,0xb0,0x21]
+@ CHECK: vbit  q8, q10, q9             @ encoding: [0x64,0xff,0xf2,0x01]
+@ CHECK: vbif  d18, d17, d16           @ encoding: [0x71,0xff,0xb0,0x21]
+@ CHECK: vbif  q8, q10, q9             @ encoding: [0x74,0xff,0xf2,0x01]

llvm/test/MC/Disassembler/ARM/neon-tests.txt

 # RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mcpu=cortex-a8 | FileCheck %s
 
 # CHECK:  vbif  q15, q7, q0
 0x50 0xe1 0x7e 0xf3
 
+# CHECK:  vbit  q15, q7, q0
+0x50 0xe1 0x6e 0xf3
+
 # CHECK:  vcvt.f32.s32  q15, q0, #1
 0x50 0xee 0xff 0xf2
 
 # CHECK:  vdup.32 q3, d1[0]
 0x41 0x6c 0xb4 0xf3
 
 # CHECK:  vld1.8  {d17, d18}, [r6], r5
 0x05 0x1a 0x66 0xf4

llvm/test/MC/Disassembler/ARM/neon.txt

 0xe0 0x05 0xf0 0xf3
 # CHECK: vmvn q8, q8
 
 0xb0 0x21 0x51 0xf3
 # CHECK: vbsl d18, d17, d16
 0xf2 0x01 0x54 0xf3
 # CHECK: vbsl q8, q10, q9
 
+0xb0 0x21 0x61 0xf3
+# CHECK: vbit d18, d17, d16
+0xf2 0x01 0x64 0xf3
+# CHECK: vbit q8, q10, q9
+
+0xb0 0x21 0x71 0xf3
+# CHECK: vbif d18, d17, d16
+0xf2 0x01 0x74 0xf3
+# CHECK: vbif q8, q10, q9
 
 # CHECK: vceq.i8  d16, d16, d17
 # CHECK: vceq.i16 d16, d16, d17
 # CHECK: vceq.i32 d16, d16, d17
 # CHECK: vceq.f32 d16, d16, d17
 # CHECK: vceq.i8  q8, q8, q9
 # CHECK: vceq.i16 q8, q8, q9
 # CHECK: vceq.i32 q8, q8, q9

llvm/test/MC/Disassembler/ARM/neont2.txt

 0xf0 0xff 0xe0 0x05
 # CHECK: vmvn q8, q8
 
 0x51 0xff 0xb0 0x21
 # CHECK: vbsl d18, d17, d16
 0x54 0xff 0xf2 0x01
 # CHECK: vbsl q8, q10, q9
 
+0x61 0xff 0xb0 0x21
+# CHECK: vbit d18, d17, d16
+0x64 0xff 0xf2 0x01
+# CHECK: vbit q8, q10, q9
+
+0x71 0xff 0xb0 0x21
+# CHECK: vbif d18, d17, d16
+0x74 0xff 0xf2 0x01
+# CHECK: vbif q8, q10, q9
+
 0xfb 0xff 0x20 0x07
 # CHECK: vcvt.s32.f32 d16, d16
 0xfb 0xff 0xa0 0x07
 # CHECK: vcvt.u32.f32 d16, d16
 0xfb 0xff 0x20 0x06
 # CHECK: vcvt.f32.s32 d16, d16
 0xfb 0xff 0xa0 0x06
 # CHECK: vcvt.f32.u32 d16, d16