Fix bug while building FP16 constant vectors for AArch64

[pirama]

Summary

Building FP16 constant vectors caused the FP16 data to be bitcast to i64. This patch creates a BITCAST node with the correct value, and adds a test to verify correct handling.

[mcrosier]

LGTM.

llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp

if (!isConstant) {
         Value = WidenVector(Value, DAG);
 
       unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
       return DAG.getNode(Opcode, dl, VT, Value, Lane);
     }
 
     if (VT.getVectorElementType().isFloatingPoint()) {
       SmallVector<SDValue, 8> Ops;
-      MVT NewType =
-          (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
+      EVT EltTy = VT.getVectorElementType();
+      assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
+              "Unsupported floating-point vector type");
+      MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
       for (unsigned i = 0; i < NumElts; ++i)
         Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
       EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
       SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
       Val = LowerBUILD_VECTOR(Val, DAG);
       if (Val.getNode())
         return DAG.getNode(ISD::BITCAST, dl, VT, Val);
     }

llvm/trunk/test/CodeGen/AArch64/fp16-v4-instructions.ll

 ; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
 
 define <4 x half> @add_h(<4 x half> %a, <4 x half> %b) {
 entry:
 ; CHECK-LABEL: add_h:
 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
 ; CHECK: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
 ; CHECK: fcvtn v0.4h, [[RES]]
   %0 = fadd <4 x half> %a, %b
   ret <4 x half> %0
 }
 
 
+define <4 x half> @build_h4(<4 x half> %a) {
+entry:
+; CHECK-LABEL: build_h4:
+; CHECK: movz [[GPR:w[0-9]+]], #0x3ccd
+; CHECK: dup v0.4h, [[GPR]]
+  ret <4 x half> <half 0xH3CCD, half 0xH3CCD, half 0xH3CCD, half 0xH3CCD>
+}
+
+
 define <4 x half> @sub_h(<4 x half> %a, <4 x half> %b) {
 entry:
 ; CHECK-LABEL: sub_h:
 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
 ; CHECK: fsub [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
 ; CHECK: fcvtn v0.4h, [[RES]]
   %0 = fsub <4 x half> %a, %b