Fix the remainder of PR22762 (GDB is crashing on DW_OP_piece being used inside of DW_AT_frame_base)

[aprantl]

Summary

http://llvm.org/bugs/show_bug.cgi?id=22762
The symptom was that DW_AT_frame_base should never use a DW_OP_(bit)_piece, the bug was that AddMachineRegPiece incorrectly created pieces to describe values that occupy only a subregister. Change this to emit a bit mask instead.

I'm posting this for review because emitting the bit mask increases the size occupied for DWARF expressions for sub-registers (~5 bytes for a 32-bit subregister). Previously we would (incorrectly!) use DW_OP_piece to describe a value occupying part of a register. However, "DW_OP_piece provides a way of describing how large a part of a variable a particular DWARF location description refers to.", not the size and offset of an entire variable inside a super-register. The way that most debuggers implement DW_OP_piece this sort of works out for subregisters that are at offset 0, but it causes confusion if the expression needs to be composed (such as in DW_AT_frame_base, or if the subregister contains only a part of the variable).

[aprantl]

For completeness, here is the updated version that uses DW_OP_piece where it is safe to do so (for subregisters at offset 0). In the end it doesn't actually look all that ugly.

[dblaikie]

lib/CodeGen/AsmPrinter/DwarfDebug.cpp

1536–1544

This code looks repetitious (same as the code in addAddress) - should it be wrapped up somewhere?

lib/CodeGen/AsmPrinter/DwarfExpression.cpp

81

Maybe name this flag "MayUsePiece" - I imagine that if GDB has trouble with piece for subregs, it'd have trouble with it for anything else too?

106

Not quite sure what this asciiart is meant to add?

115

I'd phrase this the other way - this comment should just describe the obvious case in the positive "use the shorter encoding if no shifting is required" (paraphrased - those exact words are a bit too brief)

121

This looks like it should be an elseif - since the last line of the previous if block establishes a condition that can't possibly be true for this condition anyway, right?

lib/CodeGen/AsmPrinter/DwarfUnit.cpp

550

Same repetition again

[aprantl]

lib/CodeGen/AsmPrinter/DwarfDebug.cpp

1536–1544

Yes absolutely, I intentionally wrote it that way so I could factor out the (now) obvious similarities in an NFC follow-up commit.

lib/CodeGen/AsmPrinter/DwarfExpression.cpp

81

I'm pretty sure we would have heard that by now. Besides, if this was a general flag to disable DW_OP_piece, what condition should it be triggered on: a command line option?

106

Good point, renaming Size -> SubRegSize seems to carry the same information.

115

"Use the shorter DW_OP_piece to describe a subregister at offset 0."

121

Correct.

lib/CodeGen/AsmPrinter/DwarfUnit.cpp

550

I'd like to clean this up in a follow-up commit since this is orthogonal to this bugfix.

[aprantl]

Address remaining comments (sans the refactoring).

[hjl.tools]

Maybe it is specific to x32. When a register is used as frame register,
the upper 32 bits are guaranteed to zero by hardware. We don't need
DW_OP_piece to describe the lower 32 bits of a frame register.

[aprantl]

[Just noticed that I forgot to rename MayUsePieceForSubRegMask in DwarfCompileUnit.]

The problem is that the TargetRegisterInfo tells us that the frame register is ebp, for which there is no separate register number, so it must be constructed from rbp. The DWARF backend doesn't know about what is in the upper half of rbp so it must mask out the upper bits.

[hjl.tools]

In D8233#140148, @aprantl wrote:

[Just noticed that I forgot to rename MayUsePieceForSubRegMask in DwarfCompileUnit.]

The problem is that the TargetRegisterInfo tells us that the frame register is ebp, for which there is no separate register number, so it must be constructed from rbp. The DWARF backend doesn't know about what is in the upper half of rbp so it must mask out the upper bits.

Not if ebp is used as frame register. It is OK to use rbp's DWARF register
number to map ebp when ebp is used as frame register.

[aprantl]

I think I'm ok with generally disabling DW_OP_piece inside of DW_AT_frame_base, but I would like to avoid putting in a target-specific hack (emitting rbp instead of ebp inside of DW_AT_frame_base) to work around a bug in GDB.

include/llvm/CodeGen/AsmPrinter.h

public:
   /// Emit the 4-byte offset of Label from the start of its section.  This can
   /// be done with a special directive if the target supports it (e.g. cygwin)
   /// or by emitting it as an offset from a label at the start of the section.
   void emitSectionOffset(const MCSymbol *Label) const;
 
   /// Get the value for DW_AT_APPLE_isa. Zero if no isa encoding specified.
   virtual unsigned getISAEncoding(const Function *) { return 0; }
 
-  /// EmitDwarfRegOp - Emit a dwarf register operation.
-  virtual void EmitDwarfRegOp(ByteStreamer &BS,
-                              const MachineLocation &MLoc) const;
-
   //===------------------------------------------------------------------===//
   // Dwarf Lowering Routines
   //===------------------------------------------------------------------===//
 
   /// \brief Emit frame instruction to describe the layout of the frame.
   void emitCFIInstruction(const MCCFIInstruction &Inst) const;
 
   /// \brief Emit Dwarf abbreviation table.

lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp

if (MAI->doesDwarfUseRelocationsAcrossSections()) {
     OutStreamer.EmitSymbolValue(Label, 4);
     return;
   }
 
   // Otherwise, emit it as a label difference from the start of the section.
   EmitLabelDifference(Label, Label->getSection().getBeginSymbol(), 4);
 }
 
-/// EmitDwarfRegOp - Emit dwarf register operation.
-void AsmPrinter::EmitDwarfRegOp(ByteStreamer &Streamer,
-                                const MachineLocation &MLoc) const {
-  DebugLocDwarfExpression Expr(*MF->getSubtarget().getRegisterInfo(),
-                               getDwarfDebug()->getDwarfVersion(), Streamer);
-  const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo();
-  int Reg = MRI->getDwarfRegNum(MLoc.getReg(), false);
-  if (Reg < 0) {
-    // We assume that pointers are always in an addressable register.
-    if (MLoc.isIndirect())
-      // FIXME: We have no reasonable way of handling errors in here. The
-      // caller might be in the middle of a dwarf expression. We should
-      // probably assert that Reg >= 0 once debug info generation is more
-      // mature.
-      return Expr.EmitOp(dwarf::DW_OP_nop,
-                         "nop (could not find a dwarf register number)");
-
-    // Attempt to find a valid super- or sub-register.
-    if (!Expr.AddMachineRegPiece(MLoc.getReg()))
-      Expr.EmitOp(dwarf::DW_OP_nop,
-                  "nop (could not find a dwarf register number)");
-    return;
-  }
-
-  if (MLoc.isIndirect())
-    Expr.AddRegIndirect(Reg, MLoc.getOffset());
-  else
-    Expr.AddReg(Reg);
-}
-
 //===----------------------------------------------------------------------===//
 // Dwarf Lowering Routines
 //===----------------------------------------------------------------------===//
 
 void AsmPrinter::emitCFIInstruction(const MCCFIInstruction &Inst) const {
   switch (Inst.getOperation()) {
   default:
     llvm_unreachable("Unexpected instruction");

lib/CodeGen/AsmPrinter/DwarfCompileUnit.h

public:
   const StringMap<const DIE *> &getGlobalTypes() const { return GlobalTypes; }
 
   /// Add DW_AT_location attribute for a DbgVariable based on provided
   /// MachineLocation.
   void addVariableAddress(const DbgVariable &DV, DIE &Die,
                           MachineLocation Location);
   /// Add an address attribute to a die based on the location provided.
   void addAddress(DIE &Die, dwarf::Attribute Attribute,
-                  const MachineLocation &Location);
+                  const MachineLocation &Location,
+                  bool MayUsePieceForSubRegMask = false);
 
   /// Start with the address based on the location provided, and generate the
   /// DWARF information necessary to find the actual variable (navigating the
   /// extra location information encoded in the type) based on the starting
   /// location.  Add the DWARF information to the die.
   void addComplexAddress(const DbgVariable &DV, DIE &Die,
                          dwarf::Attribute Attribute,
                          const MachineLocation &Location);

lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp

 /// DbgVariable based on provided MachineLocation.
 void DwarfCompileUnit::addVariableAddress(const DbgVariable &DV, DIE &Die,
                                           MachineLocation Location) {
   if (DV.variableHasComplexAddress())
     addComplexAddress(DV, Die, dwarf::DW_AT_location, Location);
   else if (DV.isBlockByrefVariable())
     addBlockByrefAddress(DV, Die, dwarf::DW_AT_location, Location);
   else
-    addAddress(Die, dwarf::DW_AT_location, Location);
+    addAddress(Die, dwarf::DW_AT_location, Location,
+               /*MayUsePieceForSubRegMask*/ true);
 }
 
 /// Add an address attribute to a die based on the location provided.
 void DwarfCompileUnit::addAddress(DIE &Die, dwarf::Attribute Attribute,
-                                  const MachineLocation &Location) {
+                                  const MachineLocation &Location,
+                                  bool MayUsePieceForSubRegMask) {
   DIELoc *Loc = new (DIEValueAllocator) DIELoc();
 
-  bool validReg;
-  if (Location.isReg())
-    validReg = addRegisterOpPiece(*Loc, Location.getReg());
-  else
-    validReg = addRegisterOffset(*Loc, Location.getReg(), Location.getOffset());
+  DIEDwarfExpression DwarfExpr(*Asm, *this, *Loc);
+  bool ValidReg = Location.isIndirect()
+    ? DwarfExpr.AddMachineRegIndirect(Location.getReg(), Location.getOffset())
+    : DwarfExpr.AddMachineRegPiece(Location.getReg(), 0, 0,
+                                   MayUsePieceForSubRegMask);
 
-  if (!validReg)
+  if (!ValidReg)
     return;
 
   // Now attach the location information to the DIE.
   addBlock(Die, Attribute, Loc);
 }
 
 /// Start with the address based on the location provided, and generate the
 /// DWARF information necessary to find the actual variable given the extra

lib/CodeGen/AsmPrinter/DwarfDebug.cpp

if (Value.isInt()) {
     if (BTy.Verify() && (BTy.getEncoding() == dwarf::DW_ATE_signed ||
                          BTy.getEncoding() == dwarf::DW_ATE_signed_char))
       DwarfExpr.AddSignedConstant(Value.getInt());
     else
       DwarfExpr.AddUnsignedConstant(Value.getInt());
   } else if (Value.isLocation()) {
     MachineLocation Loc = Value.getLoc();
     DIExpression Expr = Value.getExpression();
-    if (!Expr || (Expr.getNumElements() == 0))
+    if (!Expr || (Expr.getNumElements() == 0)) {
       // Regular entry.
-      AP.EmitDwarfRegOp(Streamer, Loc);
-    else {
+      bool ValidReg = Loc.isIndirect()
+        ? DwarfExpr.AddMachineRegIndirect(Loc.getReg(), Loc.getOffset())
+        : DwarfExpr.AddMachineRegPiece(Loc.getReg(), 0, 0,
+                                       /*MayUsePieceForSubRegMask*/true);
+
+      if (!ValidReg)
+        DwarfExpr.EmitOp(dwarf::DW_OP_nop,
+                         "nop (could not find a dwarf register number)");
+    } else {
       // Complex address entry.
       if (Loc.getOffset()) {
         DwarfExpr.AddMachineRegIndirect(Loc.getReg(), Loc.getOffset());
         DwarfExpr.AddExpression(Expr.begin(), Expr.end(), PieceOffsetInBits);
       } else
         DwarfExpr.AddMachineRegExpression(Expr, Loc.getReg(),
                                           PieceOffsetInBits);
     }

lib/CodeGen/AsmPrinter/DwarfExpression.h

public:
   /// current function.
   virtual bool isFrameRegister(unsigned MachineReg) = 0;
 
   /// Emit a dwarf register operation.
   void AddReg(int DwarfReg, const char *Comment = nullptr);
   /// Emit an (double-)indirect dwarf register operation.
   void AddRegIndirect(int DwarfReg, int Offset, bool Deref = false);
 
-  /// Emit a dwarf register operation for describing
+  /// Emit a dwarf operation for describing
   /// - a small value occupying only part of a register or
   /// - a register representing only part of a value.
   void AddOpPiece(unsigned SizeInBits, unsigned OffsetInBits = 0);
-  /// Emit a shift-right dwarf expression.
-  void AddShr(unsigned ShiftBy);
 
   /// Emit an indirect dwarf register operation for the given machine register.
   /// \return false if no DWARF register exists for MachineReg.
   bool AddMachineRegIndirect(unsigned MachineReg, int Offset = 0);
 
   /// \brief Emit a partial DWARF register operation.
   /// \param MachineReg        the register
   /// \param PieceSizeInBits   size and
   /// \param PieceOffsetInBits offset of the piece in bits, if this is one
   ///                          piece of an aggregate value.
+  /// \param MayEmitOpPiece    Controls whether DW_OP_piece may be emitted to
+  ///                          construct super-registers or mask subregisters at
+  ///                          offet 0. If any of the previous two parameters
+  ///                          are nonzero, then this must be true.
   ///
   /// If size and offset is zero an operation for the entire
   /// register is emitted: Some targets do not provide a DWARF
   /// register number for every register.  If this is the case, this
   /// function will attempt to emit a DWARF register by emitting a
   /// piece of a super-register or by piecing together multiple
   /// subregisters that alias the register.
   ///
   /// \return false if no DWARF register exists for MachineReg.
   bool AddMachineRegPiece(unsigned MachineReg, unsigned PieceSizeInBits = 0,
-                          unsigned PieceOffsetInBits = 0);
+                          unsigned PieceOffsetInBits = 0,
+                          bool MayEmitOpPiece = false);
 
   /// Emit a signed constant.
   void AddSignedConstant(int Value);
   /// Emit an unsigned constant.
   void AddUnsignedConstant(unsigned Value);
 
   /// Emit an entire DIExpression on top of a machine register location.
   /// \param PieceOffsetInBits If this is one piece out of a fragmented

lib/CodeGen/AsmPrinter/DwarfExpression.cpp

if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
     EmitUnsigned(OffsetInBits);
   } else {
     EmitOp(dwarf::DW_OP_piece);
     unsigned ByteSize = SizeInBits / SizeOfByte;
     EmitUnsigned(ByteSize);
   }
 }
 
-void DwarfExpression::AddShr(unsigned ShiftBy) {
-  EmitOp(dwarf::DW_OP_constu);
-  EmitUnsigned(ShiftBy);
-  EmitOp(dwarf::DW_OP_shr);
-}
-
 bool DwarfExpression::AddMachineRegIndirect(unsigned MachineReg, int Offset) {
   if (isFrameRegister(MachineReg)) {
     // If variable offset is based in frame register then use fbreg.
     EmitOp(dwarf::DW_OP_fbreg);
     EmitSigned(Offset);
     return true;
   }
 
   int DwarfReg = TRI.getDwarfRegNum(MachineReg, false);
   if (DwarfReg < 0)
     return false;
 
   AddRegIndirect(DwarfReg, Offset);
   return true;
 }
 
 bool DwarfExpression::AddMachineRegPiece(unsigned MachineReg,
                                          unsigned PieceSizeInBits,
-                                         unsigned PieceOffsetInBits) {
+                                         unsigned PieceOffsetInBits,
+                                         bool MayEmitOpPiece) {
+  assert((PieceOffsetInBits || PieceSizeInBits) ? MayEmitOpPiece : true &&
+         "piece requested, but MayEmitOpPiece is false");
+
   if (!TRI.isPhysicalRegister(MachineReg))
     return false;
 
   int Reg = TRI.getDwarfRegNum(MachineReg, false);
 
   // If this is a valid register number, emit it.
   if (Reg >= 0) {
     AddReg(Reg);
     if (PieceSizeInBits)
       AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
     return true;
   }
 
   // Walk up the super-register chain until we find a valid number.
   // For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
   for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
     Reg = TRI.getDwarfRegNum(*SR, false);
     if (Reg >= 0) {
       unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
-      unsigned Size = TRI.getSubRegIdxSize(Idx);
-      unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
+      uint64_t SubRegSize = TRI.getSubRegIdxSize(Idx);
+      uint64_t SubRegOffset = TRI.getSubRegIdxOffset(Idx);
       AddReg(Reg, "super-register");
-      if (PieceOffsetInBits == RegOffset) {
-        AddOpPiece(Size, RegOffset);
-      } else {
-        // If this is part of a variable in a sub-register at a
-        // non-zero offset, we need to manually shift the value into
-        // place, since the DW_OP_piece describes the part of the
-        // variable, not the position of the subregister.
-        if (RegOffset)
-          AddShr(RegOffset);
-        AddOpPiece(Size, PieceOffsetInBits);
+      // If this is in a sub-register at a non-zero offset, we need to manually
+      // shift the value into place, since the DW_OP_piece describes the part of
+      // the variable, not the position of the subregister.
+      if (SubRegOffset > 0) {
+        EmitOp(dwarf::DW_OP_constu);
+        EmitUnsigned(SubRegOffset);
+        EmitOp(dwarf::DW_OP_shr);
+      }
+      if (MayEmitOpPiece && SubRegOffset == 0) {
+        // Use the shorter DW_OP_piece to describe a subregister at offset 0.
+        PieceSizeInBits = SubRegSize;
+      } else if (SubRegSize > PieceSizeInBits) {
+        // Mask out the uninteresting higher bits.
+        // Use a DW_OP_and with a constant for this, because the size of DWARF
+        // stack elements is not well defined.
+        assert(SubRegSize <= 64 && "cannot create a mask larger than 64 bits");
+        uint64_t Mask = ~uint64_t(0ULL) >> (64 - SubRegSize);
+        EmitOp(dwarf::DW_OP_constu);
+        EmitUnsigned(Mask);
+        EmitOp(dwarf::DW_OP_and);
       }
+      if (PieceSizeInBits)
+        AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
       return true;
     }
   }
 
+  if (!MayEmitOpPiece)
+    return false;
+
   // Otherwise, attempt to find a covering set of sub-register numbers.
   // For example, Q0 on ARM is a composition of D0+D1.
   //
   // Keep track of the current position so we can emit the more
   // efficient DW_OP_piece.
   unsigned CurPos = PieceOffsetInBits;
   // The size of the register in bits, assuming 8 bits per byte.
   unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8;
bool DwarfExpression::AddMachineRegExpression(DIExpression Expr,
   // first.
   bool ValidReg = false;
   switch (*I) {
   case dwarf::DW_OP_bit_piece: {
     unsigned OffsetInBits = I->getArg(1);
     unsigned SizeInBits   = I->getArg(2);
     // Piece always comes at the end of the expression.
     return AddMachineRegPiece(MachineReg, SizeInBits,
-               getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
+      getOffsetOrZero(OffsetInBits, PieceOffsetInBits), true);
   }
   case dwarf::DW_OP_plus: {
     // [DW_OP_reg,Offset,DW_OP_plus,DW_OP_deref] --> [DW_OP_breg,Offset].
     auto N = I->getNext();
     if ((N != E) && (*N == dwarf::DW_OP_deref)) {
       unsigned Offset = I->getArg(1);
       ValidReg = AddMachineRegIndirect(MachineReg, Offset);
       std::advance(I, 2);

lib/CodeGen/AsmPrinter/DwarfUnit.h

public:
   void addConstantFPValue(DIE &Die, const ConstantFP *CFP);
 
   /// \brief Add a linkage name, if it isn't empty.
   void addLinkageName(DIE &Die, StringRef LinkageName);
 
   /// addTemplateParams - Add template parameters in buffer.
   void addTemplateParams(DIE &Buffer, DIArray TParams);
 
-  /// \brief Add register operand.
-  /// \returns false if the register does not exist, e.g., because it was never
-  /// materialized.
-  bool addRegisterOpPiece(DIELoc &TheDie, unsigned Reg,
-                          unsigned SizeInBits = 0, unsigned OffsetInBits = 0);
-
-  /// \brief Add register offset.
-  /// \returns false if the register does not exist, e.g., because it was never
-  /// materialized.
-  bool addRegisterOffset(DIELoc &TheDie, unsigned Reg, int64_t Offset);
-
   // FIXME: Should be reformulated in terms of addComplexAddress.
   /// addBlockByrefAddress - Start with the address based on the location
   /// provided, and generate the DWARF information necessary to find the
   /// actual Block variable (navigating the Block struct) based on the
   /// starting location.  Add the DWARF information to the die.  Obsolete,
   /// please use addComplexAddress instead.
   void addBlockByrefAddress(const DbgVariable &DV, DIE &Die,
                             dwarf::Attribute Attribute,

lib/CodeGen/AsmPrinter/DwarfUnit.cpp

 /// addSourceLine - Add location information to specified debug information
 /// entry.
 void DwarfUnit::addSourceLine(DIE &Die, DINameSpace NS) {
   assert(NS.Verify());
 
   addSourceLine(Die, NS.getLineNumber(), NS.getFilename(), NS.getDirectory());
 }
 
-/// addRegisterOp - Add register operand.
-bool DwarfUnit::addRegisterOpPiece(DIELoc &TheDie, unsigned Reg,
-                                   unsigned SizeInBits, unsigned OffsetInBits) {
-  DIEDwarfExpression Expr(*Asm, *this, TheDie);
-  Expr.AddMachineRegPiece(Reg, SizeInBits, OffsetInBits);
-  return true;
-}
-
-/// addRegisterOffset - Add register offset.
-bool DwarfUnit::addRegisterOffset(DIELoc &TheDie, unsigned Reg,
-                                  int64_t Offset) {
-  DIEDwarfExpression Expr(*Asm, *this, TheDie);
-  return Expr.AddMachineRegIndirect(Reg, Offset);
-}
-
 /* Byref variables, in Blocks, are declared by the programmer as "SomeType
    VarName;", but the compiler creates a __Block_byref_x_VarName struct, and
    gives the variable VarName either the struct, or a pointer to the struct, as
    its type.  This is necessary for various behind-the-scenes things the
    compiler needs to do with by-reference variables in Blocks.
 
    However, as far as the original *programmer* is concerned, the variable
    should still have type 'SomeType', as originally declared.
void DwarfUnit::addBlockByrefAddress(const DbgVariable &DV, DIE &Die,
   // Get the offsets for the forwarding field and the variable field.
   unsigned forwardingFieldOffset = forwardingField.getOffsetInBits() >> 3;
   unsigned varFieldOffset = varField.getOffsetInBits() >> 2;
 
   // Decode the original location, and use that as the start of the byref
   // variable's location.
   DIELoc *Loc = new (DIEValueAllocator) DIELoc();
 
-  bool validReg;
-  if (Location.isReg())
-    validReg = addRegisterOpPiece(*Loc, Location.getReg());
-  else
-    validReg = addRegisterOffset(*Loc, Location.getReg(), Location.getOffset());
+  DIEDwarfExpression DwarfExpr(*Asm, *this, *Loc);
+  bool ValidReg = Location.isIndirect()
+    ? DwarfExpr.AddMachineRegIndirect(Location.getReg(), Location.getOffset())
+    : DwarfExpr.AddMachineRegPiece(Location.getReg(), 0, 0,
+                                   /*MayUsePieceForSubRegMask*/true);
 
-  if (!validReg)
+  if (!ValidReg)
     return;
 
   // If we started with a pointer to the __Block_byref... struct, then
   // the first thing we need to do is dereference the pointer (DW_OP_deref).
   if (isPointer)
     addUInt(*Loc, dwarf::DW_FORM_data1, dwarf::DW_OP_deref);
 
   // Next add the offset for the '__forwarding' field:

test/DebugInfo/X86/frame-register.ll

 ; RUN: llc %s -filetype=obj -o - | llvm-dwarfdump --debug-dump=info - | FileCheck %s
+; This should be a mask operation to extract the lower 32 bits and not a DW_OP_piece.
+; CHECK: DW_AT_frame_base [DW_FORM_exprloc]      (<0x8> 57 10 ff ff ff ff 0f 1a )
+
 ; CHECK: DW_TAG_variable
 ;                                                      DW_OP_fbreg
 ; CHECK-NEXT: DW_AT_location [DW_FORM_exprloc]      (<0x2> 91 00 )
-; CHECK-NEXT: DW_AT_name {{.*}}"i"
+; CHECK-NEXT: DW_AT_name {{.*}}i
 
 target datalayout = "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
-target triple = "x86_64-apple-darwin"
+target triple = "x86_64-pc-linux-gnux32"
 
 ; Function Attrs: nounwind uwtable
 declare i32 @foo(i32 %i) #0
 
 ; Function Attrs: nounwind readnone
 declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
 
 ; Function Attrs: nounwind uwtable