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Differential D7941

Change the fast-isel-abort option from bool to int to enable "levels"
ClosedPublic

Authored by mehdi_amini on Feb 27 2015, 8:38 AM.

Details

Reviewers
echristo
mehdi_amini
resistor
ributzka
Commits
rG945a660cbc92: Change the fast-isel-abort option from bool to int to enable "levels"
Summary

Currently fast-isel-abort will only abort for regular instructions,
and just warn for function calls, terminators, function arguments.
There is already fast-isel-abort-args but nothing for calls and
terminators.

This change turns the fast-isel-abort options into an integer option,
so that multiple levels of strictness can be defined.
This will help no being surprised when the "abort" option indeed does
not abort, and enables the possibility to write test that verifies
that no intrinsics are forgotten by fast-isel.

Diff Detail

Event Timeline

mehdi_amini updated this revision to Diff 20856.Feb 27 2015, 8:38 AM
mehdi_amini retitled this revision from to Change the fast-isel-abort option from bool to int to enable "levels".
mehdi_amini updated this object.
mehdi_amini edited the test plan for this revision. (Show Details)
mehdi_amini added a reviewer: resistor.
mehdi_amini added a subscriber: Unknown Object (MLST).
Herald added a subscriber: jfb. · View Herald TranscriptFeb 27 2015, 8:38 AM
mcrosier added reviewers: echristo, ributzka.Feb 27 2015, 9:16 AM
resistor added inline comments.Feb 27 2015, 9:48 AM
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
175

This usage string looks wrong. The effect of 2 is never defined.

echristo edited edge metadata.Feb 27 2015, 9:50 AM

Some inline comments.

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
171–177

Can we make this default to the current default behavior? It'll mean that you don't need to update testcases too :)

175

Did you mean 2 on this line? :)

418

> 0?

1255

Don't need quotes here. (Though should probably fix from where you copied it as well :)

mehdi_amini added inline comments.Feb 27 2015, 9:59 AM
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
171–177

The existing default value is "off". I believe it is gonna be the same here.
I had to update the tests because previously you would be able to just add -fast-isel-abort while now you need -fast-isel-abort=1
I don't know if there is a way to say that -fast-isel-abort with no argument will be like =1.
Even if it is possible, I'm not even sure it is desirable as reading a command line with -fast-isel-abort alone makes me expect to always abort.

175

Nicely spotted, it is indeed 2 on the second line.

mehdi_amini updated this revision to Diff 20860.Feb 27 2015, 10:01 AM
mehdi_amini edited edge metadata.

Update thanks to Eric Christopher's review.

echristo added a comment.Feb 27 2015, 10:16 AM

One reply inline and one small cosmetic comment. Otherwise LGTM.

-eric

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
171–177

Right. Was just trying to keep the command line from changing, but you've convinced me. :)

418

Probably want some nice whitespace, but that's cosmetic.

mehdi_amini accepted this revision.Feb 27 2015, 10:34 AM
mehdi_amini added a reviewer: mehdi_amini.
This revision is now accepted and ready to land.Feb 27 2015, 10:34 AM
mehdi_amini closed this revision.Feb 27 2015, 10:35 AM

r230775 (last cosmetic comment included)

Revision Contents

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Diff 20860

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Show First 20 Lines • Show All 162 Lines • ▼ Show 20 Lines
STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call"); STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call"); STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
#endif #endif
static cl::opt<bool> static cl::opt<bool>
EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
cl::desc("Enable verbose messages in the \"fast\" " cl::desc("Enable verbose messages in the \"fast\" "
"instruction selector")); "instruction selector"));
static cl::opt<bool> static cl::opt<int> EnableFastISelAbort(
EnableFastISelAbort("fast-isel-abort", cl::Hidden, "fast-isel-abort", cl::Hidden,
cl::desc("Enable abort calls when \"fast\" instruction selection "
"fails to lower an instruction"));
static cl::opt<bool>
EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
cl::desc("Enable abort calls when \"fast\" instruction selection " cl::desc("Enable abort calls when \"fast\" instruction selection "
"fails to lower a formal argument")); "fails to lower an instruction: 0 disable the abort, 1 will "
"abort but for args, calls and terminators, 2 will also "
echristoUnsubmitted
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Did you mean 2 on this line? :)

echristo: Did you mean 2 on this line? :)
resistorUnsubmitted
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This usage string looks wrong. The effect of 2 is never defined.

resistor: This usage string looks wrong. The effect of 2 is never defined.
mehdi_aminiAuthorUnsubmitted
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Nicely spotted, it is indeed 2 on the second line.

mehdi_amini: Nicely spotted, it is indeed 2 on the second line.
"abort for argument lowering, and 3 will never fallback "
"to SelectionDAG."));
echristoUnsubmitted
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Can we make this default to the current default behavior? It'll mean that you don't need to update testcases too :)

echristo: Can we make this default to the current default behavior? It'll mean that you don't need to…
mehdi_aminiAuthorUnsubmitted
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The existing default value is "off". I believe it is gonna be the same here.
I had to update the tests because previously you would be able to just add -fast-isel-abort while now you need -fast-isel-abort=1
I don't know if there is a way to say that -fast-isel-abort with no argument will be like =1.
Even if it is possible, I'm not even sure it is desirable as reading a command line with -fast-isel-abort alone makes me expect to always abort.

mehdi_amini: The existing default value is "off". I believe it is gonna be the same here. I had to update…
echristoUnsubmitted
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Right. Was just trying to keep the command line from changing, but you've convinced me. :)

echristo: Right. Was just trying to keep the command line from changing, but you've convinced me. :)
static cl::opt<bool> static cl::opt<bool>
UseMBPI("use-mbpi", UseMBPI("use-mbpi",
cl::desc("use Machine Branch Probability Info"), cl::desc("use Machine Branch Probability Info"),
cl::init(true), cl::Hidden); cl::init(true), cl::Hidden);
#ifndef NDEBUG #ifndef NDEBUG
static cl::opt<std::string> static cl::opt<std::string>
▲ Show 20 Lines • Show All 224 Lines • ▼ Show 20 Linesstatic void SplitCriticalSideEffectEdges(Function &Fn, AliasAnalysis *AA) {
} }
} }
bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
// Do some sanity-checking on the command-line options. // Do some sanity-checking on the command-line options.
assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
"-fast-isel-verbose requires -fast-isel"); "-fast-isel-verbose requires -fast-isel");
assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
"-fast-isel-abort requires -fast-isel"); "-fast-isel-abort>0 requires -fast-isel");
echristoUnsubmitted
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> 0?

echristo: > 0?
echristoUnsubmitted
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Probably want some nice whitespace, but that's cosmetic.

echristo: Probably want some nice whitespace, but that's cosmetic.
const Function &Fn = *mf.getFunction(); const Function &Fn = *mf.getFunction();
MF = &mf; MF = &mf;
// Reset the target options before resetting the optimization // Reset the target options before resetting the optimization
// level below. // level below.
// FIXME: This is a horrible hack and should be processed via // FIXME: This is a horrible hack and should be processed via
// codegen looking at the optimization level explicitly when // codegen looking at the optimization level explicitly when
▲ Show 20 Lines • Show All 749 Lines • ▼ Show 20 Lines if (FastIS) {
// beginning FastISel on the entry block. // beginning FastISel on the entry block.
if (LLVMBB == &Fn.getEntryBlock()) { if (LLVMBB == &Fn.getEntryBlock()) {
++NumEntryBlocks; ++NumEntryBlocks;
// Lower any arguments needed in this block if this is the entry block. // Lower any arguments needed in this block if this is the entry block.
if (!FastIS->lowerArguments()) { if (!FastIS->lowerArguments()) {
// Fast isel failed to lower these arguments // Fast isel failed to lower these arguments
++NumFastIselFailLowerArguments; ++NumFastIselFailLowerArguments;
if (EnableFastISelAbortArgs) if (EnableFastISelAbort > 1)
llvm_unreachable("FastISel didn't lower all arguments"); llvm_unreachable("FastISel didn't lower all arguments");
// Use SelectionDAG argument lowering // Use SelectionDAG argument lowering
LowerArguments(Fn); LowerArguments(Fn);
CurDAG->setRoot(SDB->getControlRoot()); CurDAG->setRoot(SDB->getControlRoot());
SDB->clear(); SDB->clear();
CodeGenAndEmitDAG(); CodeGenAndEmitDAG();
} }
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines#endif
// Then handle certain instructions as single-LLVM-Instruction blocks. // Then handle certain instructions as single-LLVM-Instruction blocks.
if (isa<CallInst>(Inst)) { if (isa<CallInst>(Inst)) {
if (EnableFastISelVerbose || EnableFastISelAbort) { if (EnableFastISelVerbose || EnableFastISelAbort) {
dbgs() << "FastISel missed call: "; dbgs() << "FastISel missed call: ";
Inst->dump(); Inst->dump();
} }
if (EnableFastISelAbort > 2)
// FastISel selector couldn't handle something and bailed.
echristoUnsubmitted
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Don't need quotes here. (Though should probably fix from where you copied it as well :)

echristo: Don't need quotes here. (Though should probably fix from where you copied it as well :)
// For the purpose of debugging, just abort.
llvm_unreachable("FastISel didn't select the entire block");
if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
unsigned &R = FuncInfo->ValueMap[Inst]; unsigned &R = FuncInfo->ValueMap[Inst];
if (!R) if (!R)
R = FuncInfo->CreateRegs(Inst->getType()); R = FuncInfo->CreateRegs(Inst->getType());
} }
bool HadTailCall = false; bool HadTailCall = false;
Show All 11 Lines#endif
// Recompute NumFastIselRemaining as Selection DAG instruction // Recompute NumFastIselRemaining as Selection DAG instruction
// selection may have handled the call, input args, etc. // selection may have handled the call, input args, etc.
unsigned RemainingNow = std::distance(Begin, BI); unsigned RemainingNow = std::distance(Begin, BI);
NumFastIselFailures += NumFastIselRemaining - RemainingNow; NumFastIselFailures += NumFastIselRemaining - RemainingNow;
NumFastIselRemaining = RemainingNow; NumFastIselRemaining = RemainingNow;
continue; continue;
} }
if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
// Don't abort, and use a different message for terminator misses.
NumFastIselFailures += NumFastIselRemaining;
if (EnableFastISelVerbose || EnableFastISelAbort) { if (EnableFastISelVerbose || EnableFastISelAbort) {
if (isa<TerminatorInst>(Inst)) {
// Use a different message for terminator misses.
dbgs() << "FastISel missed terminator: "; dbgs() << "FastISel missed terminator: ";
Inst->dump();
}
} else { } else {
NumFastIselFailures += NumFastIselRemaining;
if (EnableFastISelVerbose || EnableFastISelAbort) {
dbgs() << "FastISel miss: "; dbgs() << "FastISel miss: ";
}
Inst->dump(); Inst->dump();
} }
if (EnableFastISelAbort) if (EnableFastISelAbort > 2)
// The "fast" selector couldn't handle something and bailed. // FastISel selector couldn't handle something and bailed.
// For the purpose of debugging, just abort. // For the purpose of debugging, just abort.
llvm_unreachable("FastISel didn't select the entire block"); llvm_unreachable("FastISel didn't select the entire block");
}
NumFastIselFailures += NumFastIselRemaining;
break; break;
} }
FastIS->recomputeInsertPt(); FastIS->recomputeInsertPt();
} else { } else {
// Lower any arguments needed in this block if this is the entry block. // Lower any arguments needed in this block if this is the entry block.
if (LLVMBB == &Fn.getEntryBlock()) { if (LLVMBB == &Fn.getEntryBlock()) {
++NumEntryBlocks; ++NumEntryBlocks;
▲ Show 20 Lines • Show All 2,091 Lines • Show Last 20 Lines

test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll

; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
@sortlist = common global [5001 x i32] zeroinitializer, align 16 @sortlist = common global [5001 x i32] zeroinitializer, align 16
@sortlist2 = common global [5001 x i64] zeroinitializer, align 16 @sortlist2 = common global [5001 x i64] zeroinitializer, align 16
; Load an address with an offset larget then LDR imm can handle ; Load an address with an offset larget then LDR imm can handle
define i32 @foo() nounwind { define i32 @foo() nounwind {
entry: entry:
; CHECK: @foo ; CHECK: @foo
Show All 38 Lines

test/CodeGen/AArch64/arm64-fast-isel-alloca.ll

; This test should cause the TargetMaterializeAlloca to be invoked ; This test should cause the TargetMaterializeAlloca to be invoked
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
%struct.S1Ty = type { i64 } %struct.S1Ty = type { i64 }
%struct.S2Ty = type { %struct.S1Ty, %struct.S1Ty } %struct.S2Ty = type { %struct.S1Ty, %struct.S1Ty }
define void @takeS1(%struct.S1Ty* %V) nounwind { define void @takeS1(%struct.S1Ty* %V) nounwind {
entry: entry:
%V.addr = alloca %struct.S1Ty*, align 8 %V.addr = alloca %struct.S1Ty*, align 8
store %struct.S1Ty* %V, %struct.S1Ty** %V.addr, align 8 store %struct.S1Ty* %V, %struct.S1Ty** %V.addr, align 8
Show All 14 Lines

test/CodeGen/AArch64/arm64-fast-isel-br.ll

; RUN: llc -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -mcpu=cyclone -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -O0 -fast-isel-abort=1 -mtriple=arm64-apple-darwin -mcpu=cyclone -verify-machineinstrs < %s | FileCheck %s
define void @branch1() nounwind uwtable ssp { define void @branch1() nounwind uwtable ssp {
%x = alloca i32, align 4 %x = alloca i32, align 4
store i32 0, i32* %x, align 4 store i32 0, i32* %x, align 4
%1 = load i32* %x, align 4 %1 = load i32* %x, align 4
%2 = icmp ne i32 %1, 0 %2 = icmp ne i32 %1, 0
br i1 %2, label %3, label %4 br i1 %2, label %3, label %4
▲ Show 20 Lines • Show All 145 Lines • Show Last 20 Lines

test/CodeGen/AArch64/arm64-fast-isel-call.ll

; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=small -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ; RUN: llc -O0 -fast-isel-abort=2 -code-model=small -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=large -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s --check-prefix=LARGE ; RUN: llc -O0 -fast-isel-abort=2 -code-model=large -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s --check-prefix=LARGE
; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=small -verify-machineinstrs -mtriple=aarch64_be-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-BE ; RUN: llc -O0 -fast-isel-abort=2 -code-model=small -verify-machineinstrs -mtriple=aarch64_be-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-BE
define void @call0() nounwind { define void @call0() nounwind {
entry: entry:
ret void ret void
} }
define void @foo0() nounwind { define void @foo0() nounwind {
entry: entry:
▲ Show 20 Lines • Show All 258 Lines • Show Last 20 Lines

test/CodeGen/AArch64/arm64-fast-isel-conversion.ll

; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin -mcpu=cyclone < %s | FileCheck %s ; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin -mcpu=cyclone < %s | FileCheck %s
;; Test various conversions. ;; Test various conversions.
define zeroext i32 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp { define zeroext i32 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
entry: entry:
; CHECK-LABEL: trunc_ ; CHECK-LABEL: trunc_
; CHECK: sub sp, sp, #16 ; CHECK: sub sp, sp, #16
; CHECK: strb w0, [sp, #15] ; CHECK: strb w0, [sp, #15]
; CHECK: strh w1, [sp, #12] ; CHECK: strh w1, [sp, #12]
▲ Show 20 Lines • Show All 443 Lines • Show Last 20 Lines

test/CodeGen/AArch64/arm64-fast-isel-fcmp.ll

; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
define zeroext i1 @fcmp_float1(float %a) { define zeroext i1 @fcmp_float1(float %a) {
; CHECK-LABEL: fcmp_float1 ; CHECK-LABEL: fcmp_float1
; CHECK: fcmp s0, #0.0 ; CHECK: fcmp s0, #0.0
; CHECK-NEXT: cset {{w[0-9]+}}, ne ; CHECK-NEXT: cset {{w[0-9]+}}, ne
%1 = fcmp une float %a, 0.000000e+00 %1 = fcmp une float %a, 0.000000e+00
ret i1 %1 ret i1 %1
} }
▲ Show 20 Lines • Show All 153 Lines • Show Last 20 Lines

test/CodeGen/AArch64/arm64-fast-isel-gv.ll

; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
; Test load/store of global value from global offset table. ; Test load/store of global value from global offset table.
@seed = common global i64 0, align 8 @seed = common global i64 0, align 8
define void @Initrand() nounwind { define void @Initrand() nounwind {
entry: entry:
; CHECK: @Initrand ; CHECK: @Initrand
; CHECK: adrp [[REG:x[0-9]+]], _seed@GOTPAGE ; CHECK: adrp [[REG:x[0-9]+]], _seed@GOTPAGE
Show All 28 Lines

test/CodeGen/AArch64/arm64-fast-isel-icmp.ll

; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
define i32 @icmp_eq_imm(i32 %a) nounwind ssp { define i32 @icmp_eq_imm(i32 %a) nounwind ssp {
entry: entry:
; CHECK-LABEL: icmp_eq_imm ; CHECK-LABEL: icmp_eq_imm
; CHECK: cmp w0, #31 ; CHECK: cmp w0, #31
; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: cset w0, eq
%cmp = icmp eq i32 %a, 31 %cmp = icmp eq i32 %a, 31
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
▲ Show 20 Lines • Show All 232 Lines • Show Last 20 Lines

test/CodeGen/AArch64/arm64-fast-isel-indirectbr.ll

; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
@fn.table = internal global [2 x i8*] [i8* blockaddress(@fn, %ZERO), i8* blockaddress(@fn, %ONE)], align 8 @fn.table = internal global [2 x i8*] [i8* blockaddress(@fn, %ZERO), i8* blockaddress(@fn, %ONE)], align 8
define i32 @fn(i32 %target) nounwind { define i32 @fn(i32 %target) nounwind {
entry: entry:
; CHECK-LABEL: fn ; CHECK-LABEL: fn
%retval = alloca i32, align 4 %retval = alloca i32, align 4
%target.addr = alloca i32, align 4 %target.addr = alloca i32, align 4
Show All 27 Lines

test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll

; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=arm64-apple-ios < %s | FileCheck %s --check-prefix=ARM64 ; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=arm64-apple-ios < %s | FileCheck %s --check-prefix=ARM64
@message = global [80 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 16 @message = global [80 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 16
@temp = common global [80 x i8] zeroinitializer, align 16 @temp = common global [80 x i8] zeroinitializer, align 16
define void @t1() { define void @t1() {
; ARM64-LABEL: t1 ; ARM64-LABEL: t1
; ARM64: adrp x8, _message@PAGE ; ARM64: adrp x8, _message@PAGE
; ARM64: add x0, x8, _message@PAGEOFF ; ARM64: add x0, x8, _message@PAGEOFF
▲ Show 20 Lines • Show All 139 Lines • Show Last 20 Lines

test/CodeGen/AArch64/arm64-fast-isel-materialize.ll

; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
; Materialize using fmov ; Materialize using fmov
define float @fmov_float1() { define float @fmov_float1() {
; CHECK-LABEL: fmov_float1 ; CHECK-LABEL: fmov_float1
; CHECK: fmov s0, #1.25000000 ; CHECK: fmov s0, #1.25000000
ret float 1.250000e+00 ret float 1.250000e+00
} }
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test/CodeGen/AArch64/arm64-fast-isel-rem.ll

; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
; RUN: llc %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t ; RUN: llc %s -O0 -fast-isel-abort=1 -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t
; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA ; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA
; CHECK-SSA-LABEL: Machine code for function t1 ; CHECK-SSA-LABEL: Machine code for function t1
; CHECK-SSA: [[QUOTREG:%vreg[0-9]+]]<def> = SDIVWr ; CHECK-SSA: [[QUOTREG:%vreg[0-9]+]]<def> = SDIVWr
; CHECK-SSA-NOT: [[QUOTREG]]<def> = ; CHECK-SSA-NOT: [[QUOTREG]]<def> =
; CHECK-SSA: {{%vreg[0-9]+}}<def> = MSUBWrrr [[QUOTREG]] ; CHECK-SSA: {{%vreg[0-9]+}}<def> = MSUBWrrr [[QUOTREG]]
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test/CodeGen/AArch64/arm64-fast-isel-ret.ll

; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
;; Test returns. ;; Test returns.
define void @t0() nounwind ssp { define void @t0() nounwind ssp {
entry: entry:
; CHECK: t0 ; CHECK: t0
; CHECK: ret ; CHECK: ret
ret void ret void
} }
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test/CodeGen/AArch64/arm64-fast-isel-store.ll

; RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-unknown-unknown -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-unknown-unknown -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
define void @store_i8(i8* %a) { define void @store_i8(i8* %a) {
; CHECK-LABEL: store_i8 ; CHECK-LABEL: store_i8
; CHECK: strb wzr, [x0] ; CHECK: strb wzr, [x0]
store i8 0, i8* %a store i8 0, i8* %a
ret void ret void
} }
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test/CodeGen/AArch64/arm64-fast-isel.ll

; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
define void @t0(i32 %a) nounwind { define void @t0(i32 %a) nounwind {
entry: entry:
; CHECK: t0 ; CHECK: t0
; CHECK: str {{w[0-9]+}}, [sp, #12] ; CHECK: str {{w[0-9]+}}, [sp, #12]
; CHECK-NEXT: ldr [[REGISTER:w[0-9]+]], [sp, #12] ; CHECK-NEXT: ldr [[REGISTER:w[0-9]+]], [sp, #12]
; CHECK-NEXT: str [[REGISTER]], [sp, #12] ; CHECK-NEXT: str [[REGISTER]], [sp, #12]
; CHECK: ret ; CHECK: ret
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test/CodeGen/AArch64/arm64-patchpoint.ll

; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone < %s | FileCheck %s ; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone < %s | FileCheck %s
; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -fast-isel -fast-isel-abort < %s | FileCheck %s ; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -fast-isel -fast-isel-abort=1 < %s | FileCheck %s
; Trivial patchpoint codegen ; Trivial patchpoint codegen
; ;
define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry: entry:
; CHECK-LABEL: trivial_patchpoint_codegen: ; CHECK-LABEL: trivial_patchpoint_codegen:
; CHECK: movz x16, #0xdead, lsl #32 ; CHECK: movz x16, #0xdead, lsl #32
; CHECK-NEXT: movk x16, #0xbeef, lsl #16 ; CHECK-NEXT: movk x16, #0xbeef, lsl #16
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test/CodeGen/AArch64/arm64-stackmap.ll

; RUN: llc -mtriple=arm64-apple-darwin < %s | FileCheck %s ; RUN: llc -mtriple=arm64-apple-darwin < %s | FileCheck %s
; RUN: llc -mtriple=arm64-apple-darwin -fast-isel -fast-isel-abort < %s | FileCheck %s ; RUN: llc -mtriple=arm64-apple-darwin -fast-isel -fast-isel-abort=1 < %s | FileCheck %s
; ;
; Note: Print verbose stackmaps using -debug-only=stackmaps. ; Note: Print verbose stackmaps using -debug-only=stackmaps.
; We are not getting the correct stack alignment when cross compiling for arm64. ; We are not getting the correct stack alignment when cross compiling for arm64.
; So specify a datalayout here. ; So specify a datalayout here.
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
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test/CodeGen/AArch64/arm64-xaluo.ll

; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
; ;
; Get the actual value of the overflow bit. ; Get the actual value of the overflow bit.
; ;
define zeroext i1 @saddo1.i32(i32 %v1, i32 %v2, i32* %res) { define zeroext i1 @saddo1.i32(i32 %v1, i32 %v2, i32* %res) {
entry: entry:
; CHECK-LABEL: saddo1.i32 ; CHECK-LABEL: saddo1.i32
; CHECK: adds {{w[0-9]+}}, w0, w1 ; CHECK: adds {{w[0-9]+}}, w0, w1
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test/CodeGen/AArch64/fast-isel-addressing-modes.ll

; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG ; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
; Load / Store Base Register only ; Load / Store Base Register only
define zeroext i1 @load_breg_i1(i1* %a) { define zeroext i1 @load_breg_i1(i1* %a) {
; CHECK-LABEL: load_breg_i1 ; CHECK-LABEL: load_breg_i1
; CHECK: ldrb {{w[0-9]+}}, [x0] ; CHECK: ldrb {{w[0-9]+}}, [x0]
%1 = load i1* %a %1 = load i1* %a
ret i1 %1 ret i1 %1
} }
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test/CodeGen/AArch64/fast-isel-branch-cond-split.ll

; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
; CHECK-label: test_or ; CHECK-label: test_or
; CHECK: cbnz w0, {{LBB[0-9]+_2}} ; CHECK: cbnz w0, {{LBB[0-9]+_2}}
; CHECK: cbz w1, {{LBB[0-9]+_1}} ; CHECK: cbz w1, {{LBB[0-9]+_1}}
define i64 @test_or(i32 %a, i32 %b) { define i64 @test_or(i32 %a, i32 %b) {
bb1: bb1:
%0 = icmp eq i32 %a, 0 %0 = icmp eq i32 %a, 0
%1 = icmp eq i32 %b, 0 %1 = icmp eq i32 %b, 0
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test/CodeGen/AArch64/fast-isel-branch_weights.ll

; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
; Test if the BBs are reordred according to their branch weights. ; Test if the BBs are reordred according to their branch weights.
define i64 @branch_weights_test(i64 %a, i64 %b) { define i64 @branch_weights_test(i64 %a, i64 %b) {
; CHECK-LABEL: branch_weights_test ; CHECK-LABEL: branch_weights_test
; CHECK-LABEL: success ; CHECK-LABEL: success
; CHECK-LABEL: fail ; CHECK-LABEL: fail
%1 = icmp ult i64 %a, %b %1 = icmp ult i64 %a, %b
br i1 %1, label %fail, label %success, !prof !0 br i1 %1, label %fail, label %success, !prof !0
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test/CodeGen/AArch64/fast-isel-call-return.ll

; RUN: llc -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-linux-gnu" target triple = "aarch64-linux-gnu"
define i8* @test_call_return_type(i64 %size) { define i8* @test_call_return_type(i64 %size) {
entry: entry:
; CHECK: bl xmalloc ; CHECK: bl xmalloc
%0 = call noalias i8* @xmalloc(i64 undef) %0 = call noalias i8* @xmalloc(i64 undef)
ret i8* %0 ret i8* %0
} }
declare noalias i8* @xmalloc(i64) declare noalias i8* @xmalloc(i64)

test/CodeGen/AArch64/fast-isel-cbz.ll

; RUN: llc -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s ; RUN: llc -fast-isel -fast-isel-abort=1 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s
define i32 @icmp_eq_i1(i1 %a) { define i32 @icmp_eq_i1(i1 %a) {
; CHECK-LABEL: icmp_eq_i1 ; CHECK-LABEL: icmp_eq_i1
; CHECK: tbz w0, #0, {{LBB.+_2}} ; CHECK: tbz w0, #0, {{LBB.+_2}}
%1 = icmp eq i1 %a, 0 %1 = icmp eq i1 %a, 0
br i1 %1, label %bb1, label %bb2 br i1 %1, label %bb1, label %bb2
bb2: bb2:
ret i32 1 ret i32 1
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test/CodeGen/AArch64/fast-isel-cmp-branch.ll

; RUN: llc -aarch64-atomic-cfg-tidy=0 -mtriple=aarch64-apple-darwin < %s | FileCheck %s ; RUN: llc -aarch64-atomic-cfg-tidy=0 -mtriple=aarch64-apple-darwin < %s | FileCheck %s
; RUN: llc -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=0 -mtriple=aarch64-apple-darwin < %s | FileCheck %s ; RUN: llc -fast-isel -fast-isel-abort=1 -aarch64-atomic-cfg-tidy=0 -mtriple=aarch64-apple-darwin < %s | FileCheck %s
define i32 @fcmp_oeq(float %x, float %y) { define i32 @fcmp_oeq(float %x, float %y) {
; CHECK-LABEL: fcmp_oeq ; CHECK-LABEL: fcmp_oeq
; CHECK: fcmp s0, s1 ; CHECK: fcmp s0, s1
; CHECK-NEXT: b.ne {{LBB.+_2}} ; CHECK-NEXT: b.ne {{LBB.+_2}}
%1 = fcmp oeq float %x, %y %1 = fcmp oeq float %x, %y
br i1 %1, label %bb1, label %bb2 br i1 %1, label %bb1, label %bb2
bb2: bb2:
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test/CodeGen/AArch64/fast-isel-folding.ll

; RUN: llc -mtriple=aarch64-apple-darwin -O0 -fast-isel-abort -verify-machineinstrs < %s ; RUN: llc -mtriple=aarch64-apple-darwin -O0 -fast-isel-abort=1 -verify-machineinstrs < %s
; Test that we don't fold the shift. ; Test that we don't fold the shift.
define i64 @fold_shift_test(i64 %a, i1 %c) { define i64 @fold_shift_test(i64 %a, i1 %c) {
%1 = sub i64 %a, 8 %1 = sub i64 %a, 8
%2 = ashr i64 %1, 3 %2 = ashr i64 %1, 3
br i1 %c, label %bb1, label %bb2 br i1 %c, label %bb1, label %bb2
bb1: bb1:
%3 = icmp ult i64 0, %2 %3 = icmp ult i64 0, %2
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test/CodeGen/AArch64/fast-isel-gep.ll

; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
%struct.foo = type { i32, i64, float, double } %struct.foo = type { i32, i64, float, double }
define double* @test_struct(%struct.foo* %f) { define double* @test_struct(%struct.foo* %f) {
; CHECK-LABEL: test_struct ; CHECK-LABEL: test_struct
; CHECK: add x0, x0, #24 ; CHECK: add x0, x0, #24
%1 = getelementptr inbounds %struct.foo* %f, i64 0, i32 3 %1 = getelementptr inbounds %struct.foo* %f, i64 0, i32 3
ret double* %1 ret double* %1
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test/CodeGen/AArch64/fast-isel-int-ext.ll

; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
; ;
; Test that we only use the sign/zero extend in the address calculation when ; Test that we only use the sign/zero extend in the address calculation when
; necessary. ; necessary.
; ;
; SHIFT ; SHIFT
; ;
define i64 @load_addr_shift_zext1(i32 %a, i64 %b) { define i64 @load_addr_shift_zext1(i32 %a, i64 %b) {
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test/CodeGen/AArch64/fast-isel-int-ext2.ll

; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=false -disable-cgp-branch-opts -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -aarch64-atomic-cfg-tidy=false -disable-cgp-branch-opts -verify-machineinstrs < %s | FileCheck %s
; ;
; Test folding of the sign-/zero-extend into the load instruction. ; Test folding of the sign-/zero-extend into the load instruction.
; ;
; Unscaled ; Unscaled
define i32 @load_unscaled_zext_i8_to_i32(i64 %a) { define i32 @load_unscaled_zext_i8_to_i32(i64 %a) {
; CHECK-LABEL: load_unscaled_zext_i8_to_i32 ; CHECK-LABEL: load_unscaled_zext_i8_to_i32
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test/CodeGen/AArch64/fast-isel-int-ext4.ll

; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
define i32 @kill_flag(i16 signext %a) { define i32 @kill_flag(i16 signext %a) {
; CHECK-LABEL: kill_flag ; CHECK-LABEL: kill_flag
entry: entry:
%0 = sext i16 %a to i32 %0 = sext i16 %a to i32
br label %bb1 br label %bb1
bb1: bb1:
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test/CodeGen/AArch64/fast-isel-logic-op.ll

; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
; AND ; AND
define zeroext i1 @and_rr_i1(i1 signext %a, i1 signext %b) { define zeroext i1 @and_rr_i1(i1 signext %a, i1 signext %b) {
; CHECK-LABEL: and_rr_i1 ; CHECK-LABEL: and_rr_i1
; CHECK: and [[REG:w[0-9]+]], w0, w1 ; CHECK: and [[REG:w[0-9]+]], w0, w1
%1 = and i1 %a, %b %1 = and i1 %a, %b
ret i1 %1 ret i1 %1
} }
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test/CodeGen/AArch64/fast-isel-memcpy.ll

; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
; Test that we don't segfault. ; Test that we don't segfault.
; CHECK-LABEL: test ; CHECK-LABEL: test
; CHECK: ldr [[REG1:x[0-9]+]], [x1] ; CHECK: ldr [[REG1:x[0-9]+]], [x1]
; CHECK-NEXT: and [[REG2:x[0-9]+]], x0, #0x7fffffffffffffff ; CHECK-NEXT: and [[REG2:x[0-9]+]], x0, #0x7fffffffffffffff
; CHECK-NEXT: str [[REG1]], {{\[}}[[REG2]]{{\]}} ; CHECK-NEXT: str [[REG1]], {{\[}}[[REG2]]{{\]}}
define void @test(i64 %a, i8* %b) { define void @test(i64 %a, i8* %b) {
%1 = and i64 %a, 9223372036854775807 %1 = and i64 %a, 9223372036854775807
%2 = inttoptr i64 %1 to i8* %2 = inttoptr i64 %1 to i8*
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %b, i64 8, i32 8, i1 false) call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %b, i64 8, i32 8, i1 false)
ret void ret void
} }
declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1) declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1)

test/CodeGen/AArch64/fast-isel-mul.ll

; RUN: llc -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s ; RUN: llc -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s
define zeroext i8 @test_mul8(i8 %lhs, i8 %rhs) { define zeroext i8 @test_mul8(i8 %lhs, i8 %rhs) {
; CHECK-LABEL: test_mul8: ; CHECK-LABEL: test_mul8:
; CHECK: mul {{w[0-9]+}}, w0, w1 ; CHECK: mul {{w[0-9]+}}, w0, w1
%1 = mul i8 %lhs, %rhs %1 = mul i8 %lhs, %rhs
ret i8 %1 ret i8 %1
} }
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test/CodeGen/AArch64/fast-isel-runtime-libcall.ll

; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -code-model=small -verify-machineinstrs < %s | FileCheck %s --check-prefix=SMALL ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -code-model=small -verify-machineinstrs < %s | FileCheck %s --check-prefix=SMALL
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -code-model=large -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -code-model=large -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE
define float @frem_f32(float %a, float %b) { define float @frem_f32(float %a, float %b) {
; SMALL-LABEL: frem_f32 ; SMALL-LABEL: frem_f32
; SMALL: bl _fmodf ; SMALL: bl _fmodf
; LARGE-LABEL: frem_f32 ; LARGE-LABEL: frem_f32
; LARGE: adrp [[REG:x[0-9]+]], _fmodf@GOTPAGE ; LARGE: adrp [[REG:x[0-9]+]], _fmodf@GOTPAGE
; LARGE: ldr [[REG]], {{\[}}[[REG]], _fmodf@GOTPAGEOFF{{\]}} ; LARGE: ldr [[REG]], {{\[}}[[REG]], _fmodf@GOTPAGEOFF{{\]}}
; LARGE-NEXT: blr [[REG]] ; LARGE-NEXT: blr [[REG]]
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test/CodeGen/AArch64/fast-isel-sdiv.ll

; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
define i32 @sdiv_i32_exact(i32 %a) { define i32 @sdiv_i32_exact(i32 %a) {
; CHECK-LABEL: sdiv_i32_exact ; CHECK-LABEL: sdiv_i32_exact
; CHECK: asr {{w[0-9]+}}, w0, #3 ; CHECK: asr {{w[0-9]+}}, w0, #3
%1 = sdiv exact i32 %a, 8 %1 = sdiv exact i32 %a, 8
ret i32 %1 ret i32 %1
} }
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test/CodeGen/AArch64/fast-isel-select.ll

; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
; First test the different supported value types for select. ; First test the different supported value types for select.
define zeroext i1 @select_i1(i1 zeroext %c, i1 zeroext %a, i1 zeroext %b) { define zeroext i1 @select_i1(i1 zeroext %c, i1 zeroext %a, i1 zeroext %b) {
; CHECK-LABEL: select_i1 ; CHECK-LABEL: select_i1
; CHECK: {{cmp w0, #0|tst w0, #0x1}} ; CHECK: {{cmp w0, #0|tst w0, #0x1}}
; CHECK-NEXT: csel {{w[0-9]+}}, w1, w2, ne ; CHECK-NEXT: csel {{w[0-9]+}}, w1, w2, ne
%1 = select i1 %c, i1 %a, i1 %b %1 = select i1 %c, i1 %a, i1 %b
ret i1 %1 ret i1 %1
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test/CodeGen/AArch64/fast-isel-shift.ll

; RUN: llc -fast-isel -fast-isel-abort -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -fast-isel -fast-isel-abort=1 -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: asr_zext_i1_i16 ; CHECK-LABEL: asr_zext_i1_i16
; CHECK: uxth {{w[0-9]*}}, wzr ; CHECK: uxth {{w[0-9]*}}, wzr
define zeroext i16 @asr_zext_i1_i16(i1 %b) { define zeroext i16 @asr_zext_i1_i16(i1 %b) {
%1 = zext i1 %b to i16 %1 = zext i1 %b to i16
%2 = ashr i16 %1, 1 %2 = ashr i16 %1, 1
ret i16 %2 ret i16 %2
} }
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test/CodeGen/AArch64/fast-isel-sqrt.ll

; RUN: llc -mtriple=arm64-apple-darwin -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=arm64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=arm64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=arm64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
define float @test_sqrt_f32(float %a) { define float @test_sqrt_f32(float %a) {
; CHECK-LABEL: test_sqrt_f32 ; CHECK-LABEL: test_sqrt_f32
; CHECK: fsqrt s0, s0 ; CHECK: fsqrt s0, s0
%res = call float @llvm.sqrt.f32(float %a) %res = call float @llvm.sqrt.f32(float %a)
ret float %res ret float %res
} }
declare float @llvm.sqrt.f32(float) nounwind readnone declare float @llvm.sqrt.f32(float) nounwind readnone
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test/CodeGen/AArch64/fast-isel-tbz.ll

; RUN: llc -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK %s ; RUN: llc -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK %s
; RUN: llc -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK --check-prefix=FAST %s ; RUN: llc -fast-isel -fast-isel-abort=1 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK --check-prefix=FAST %s
define i32 @icmp_eq_i8(i8 zeroext %a) { define i32 @icmp_eq_i8(i8 zeroext %a) {
; CHECK-LABEL: icmp_eq_i8 ; CHECK-LABEL: icmp_eq_i8
; CHECK: tbz {{w[0-9]+}}, #0, {{LBB.+_2}} ; CHECK: tbz {{w[0-9]+}}, #0, {{LBB.+_2}}
%1 = and i8 %a, 1 %1 = and i8 %a, 1
%2 = icmp eq i8 %1, 0 %2 = icmp eq i8 %1, 0
br i1 %2, label %bb1, label %bb2, !prof !0 br i1 %2, label %bb1, label %bb2, !prof !0
bb1: bb1:
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test/CodeGen/AArch64/fast-isel-trunc.ll

; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s
; Test that %1 doesn't get the kill flag set before its last use. ; Test that %1 doesn't get the kill flag set before its last use.
define i32 @test_trunc(i32 %a) { define i32 @test_trunc(i32 %a) {
%1 = add i32 %a, 1 %1 = add i32 %a, 1
%2 = trunc i32 %1 to i16 %2 = trunc i32 %1 to i16
%3 = icmp ult i16 1, %2 %3 = icmp ult i16 1, %2
%4 = add i32 %1, 1 %4 = add i32 %1, 1
%5 = sext i1 %3 to i32 %5 = sext i1 %3 to i32
%6 = and i32 %4, %5 %6 = and i32 %4, %5
ret i32 %6 ret i32 %6
} }

test/CodeGen/AArch64/fast-isel-vector-arithmetic.ll

; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -fast-isel-abort-args -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=2 -verify-machineinstrs < %s | FileCheck %s
; Vector Integer Add ; Vector Integer Add
define <8 x i8> @add_v8i8_rr(<8 x i8> %a, <8 x i8> %b) { define <8 x i8> @add_v8i8_rr(<8 x i8> %a, <8 x i8> %b) {
; CHECK: add_v8i8_rr ; CHECK: add_v8i8_rr
; CHECK: add.8b v0, v0, v1 ; CHECK: add.8b v0, v0, v1
%1 = add <8 x i8> %a, %b %1 = add <8 x i8> %a, %b
ret <8 x i8> %1 ret <8 x i8> %1
} }
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test/CodeGen/AArch64/fast-isel-vret.ll

; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
; Test that we don't abort fast-isle for ret ; Test that we don't abort fast-isle for ret
define <8 x i8> @ret_v8i8(<8 x i8> %a, <8 x i8> %b) { define <8 x i8> @ret_v8i8(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: ret_v8i8 ; CHECK-LABEL: ret_v8i8
; CHECK: add.8b v0, v0, v1 ; CHECK: add.8b v0, v0, v1
%1 = add <8 x i8> %a, %b %1 = add <8 x i8> %a, %b
ret <8 x i8> %1 ret <8 x i8> %1
} }

test/CodeGen/AArch64/fpimm.ll

; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE ; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE
; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE ; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE
@varf32 = global float 0.0 @varf32 = global float 0.0
@varf64 = global double 0.0 @varf64 = global double 0.0
define void @check_float() { define void @check_float() {
; CHECK-LABEL: check_float: ; CHECK-LABEL: check_float:
%val = load float* @varf32 %val = load float* @varf32
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test/CodeGen/AArch64/frameaddr.ll

; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
define i8* @test_frameaddress0() nounwind { define i8* @test_frameaddress0() nounwind {
entry: entry:
; CHECK-LABEL: test_frameaddress0: ; CHECK-LABEL: test_frameaddress0:
; CHECK: stp x29, x30, [sp, #-16]! ; CHECK: stp x29, x30, [sp, #-16]!
; CHECK: mov x29, sp ; CHECK: mov x29, sp
; CHECK: mov x0, x29 ; CHECK: mov x0, x29
; CHECK: ldp x29, x30, [sp], #16 ; CHECK: ldp x29, x30, [sp], #16
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test/CodeGen/ARM/fast-isel-GEP-coalesce.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
%struct.A = type { i32, [2 x [2 x i32]], i8, [3 x [3 x [3 x i32]]] } %struct.A = type { i32, [2 x [2 x i32]], i8, [3 x [3 x [3 x i32]]] }
%struct.B = type { i32, [2 x [2 x [2 x %struct.A]]] } %struct.B = type { i32, [2 x [2 x [2 x %struct.A]]] }
@arr = common global [2 x [2 x [2 x [2 x [2 x i32]]]]] zeroinitializer, align 4 @arr = common global [2 x [2 x [2 x [2 x [2 x i32]]]]] zeroinitializer, align 4
@A = common global [3 x [3 x %struct.A]] zeroinitializer, align 4 @A = common global [3 x [3 x %struct.A]] zeroinitializer, align 4
@B = common global [2 x [2 x [2 x %struct.B]]] zeroinitializer, align 4 @B = common global [2 x [2 x [2 x %struct.B]]] zeroinitializer, align 4
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test/CodeGen/ARM/fast-isel-align.ll

; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN ; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN ; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN ; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN ; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN ; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN ; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN ; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
; Check unaligned stores ; Check unaligned stores
%struct.anon = type <{ float }> %struct.anon = type <{ float }>
@a = common global %struct.anon* null, align 4 @a = common global %struct.anon* null, align 4
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test/CodeGen/ARM/fast-isel-binary.ll

; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
; Test add with non-legal types ; Test add with non-legal types
define void @add_i1(i1 %a, i1 %b) nounwind ssp { define void @add_i1(i1 %a, i1 %b) nounwind ssp {
entry: entry:
; ARM: add_i1 ; ARM: add_i1
; THUMB: add_i1 ; THUMB: add_i1
%a.addr = alloca i1, align 4 %a.addr = alloca i1, align 4
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test/CodeGen/ARM/fast-isel-br-const.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp { define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp {
entry: entry:
; THUMB-LABEL: t1: ; THUMB-LABEL: t1:
; ARM-LABEL: t1: ; ARM-LABEL: t1:
%x = add i32 %a, %b %x = add i32 %a, %b
br i1 1, label %if.then, label %if.else br i1 1, label %if.then, label %if.else
; THUMB-NOT: b {{\.?}}LBB0_1 ; THUMB-NOT: b {{\.?}}LBB0_1
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test/CodeGen/ARM/fast-isel-br-phi.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios
; This test ensures HandlePHINodesInSuccessorBlocks() is able to promote basic ; This test ensures HandlePHINodesInSuccessorBlocks() is able to promote basic
; non-legal integer types (i.e., i1, i8, i16). ; non-legal integer types (i.e., i1, i8, i16).
declare void @fooi8(i8) declare void @fooi8(i8)
declare void @fooi16(i16) declare void @fooi16(i16)
define void @foo(i1 %cmp) nounwind ssp { define void @foo(i1 %cmp) nounwind ssp {
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test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
; Fast-isel can't handle non-double multi-reg retvals. ; Fast-isel can't handle non-double multi-reg retvals.
; This test just check to make sure we don't hit the assert in FinishCall. ; This test just check to make sure we don't hit the assert in FinishCall.
define <16 x i8> @foo() nounwind ssp { define <16 x i8> @foo() nounwind ssp {
entry: entry:
ret <16 x i8> zeroinitializer ret <16 x i8> zeroinitializer
} }
define void @t1() nounwind ssp { define void @t1() nounwind ssp {
entry: entry:
; ARM: @t1 ; ARM: @t1
; THUMB: @t1 ; THUMB: @t1
%call = call <16 x i8> @foo() %call = call <16 x i8> @foo()
ret void ret void
} }

test/CodeGen/ARM/fast-isel-call.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=THUMB-LONG ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=THUMB-LONG
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=THUMB-NOVFP ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=THUMB-NOVFP
; Note that some of these tests assume that relocations are either ; Note that some of these tests assume that relocations are either
; movw/movt or constant pool loads. Different platforms will select ; movw/movt or constant pool loads. Different platforms will select
; different approaches. ; different approaches.
define i32 @t0(i1 zeroext %a) nounwind { define i32 @t0(i1 zeroext %a) nounwind {
%1 = zext i1 %a to i32 %1 = zext i1 %a to i32
ret i32 %1 ret i32 %1
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test/CodeGen/ARM/fast-isel-cmp-imm.ll

; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
define void @t1a(float %a) uwtable ssp { define void @t1a(float %a) uwtable ssp {
entry: entry:
; ARM: t1a ; ARM: t1a
; THUMB: t1a ; THUMB: t1a
%cmp = fcmp oeq float %a, 0.000000e+00 %cmp = fcmp oeq float %a, 0.000000e+00
; ARM: vcmpe.f32 s{{[0-9]+}}, #0 ; ARM: vcmpe.f32 s{{[0-9]+}}, #0
; THUMB: vcmpe.f32 s{{[0-9]+}}, #0 ; THUMB: vcmpe.f32 s{{[0-9]+}}, #0
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test/CodeGen/ARM/fast-isel-conversion.ll

; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
; Test sitofp ; Test sitofp
define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp { define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp {
entry: entry:
; ARM: sitofp_single_i32 ; ARM: sitofp_single_i32
; ARM: vmov s0, r0 ; ARM: vmov s0, r0
; ARM: vcvt.f32.s32 s0, s0 ; ARM: vcvt.f32.s32 s0, s0
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test/CodeGen/ARM/fast-isel-crash.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-apple-darwin ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=thumbv7-apple-darwin
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-linux-gnueabi ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=thumbv7-linux-gnueabi
%union.anon = type { <16 x i32> } %union.anon = type { <16 x i32> }
@__md0 = external global [137 x i8] @__md0 = external global [137 x i8]
define internal void @stretch(<4 x i8> addrspace(1)* %src, <4 x i8> addrspace(1)* %dst, i32 %width, i32 %height, i32 %iLS, i32 %oLS, <2 x float> %c, <4 x float> %param) nounwind { define internal void @stretch(<4 x i8> addrspace(1)* %src, <4 x i8> addrspace(1)* %dst, i32 %width, i32 %height, i32 %iLS, i32 %oLS, <2 x float> %c, <4 x float> %param) nounwind {
entry: entry:
ret void ret void
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test/CodeGen/ARM/fast-isel-deadcode.ll

; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
; Target-specific selector can't properly handle the double because it isn't ; Target-specific selector can't properly handle the double because it isn't
; being passed via a register, so the materialized arguments become dead code. ; being passed via a register, so the materialized arguments become dead code.
define i32 @main(i32 %argc, i8** %argv) nounwind { define i32 @main(i32 %argc, i8** %argv) nounwind {
entry: entry:
; THUMB: main ; THUMB: main
call void @printArgsNoRet(i32 1, float 0x4000CCCCC0000000, i8 signext 99, double 4.100000e+00) call void @printArgsNoRet(i32 1, float 0x4000CCCCC0000000, i8 signext 99, double 4.100000e+00)
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test/CodeGen/ARM/fast-isel-ext.ll

; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7 ; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=v7 ; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=v7
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6 ; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv4t-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6 ; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv4t-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6 ; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv5-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6 ; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv5-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7 ; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports ; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports
; Thumb2. The ARMFastISel::ARMEmitIntExt code should work for Thumb by always ; Thumb2. The ARMFastISel::ARMEmitIntExt code should work for Thumb by always
; using two shifts. ; using two shifts.
; Note that lsl, asr and lsr in Thumb are all encoded as 16-bit instructions ; Note that lsl, asr and lsr in Thumb are all encoded as 16-bit instructions
; and therefore must set flags. {{s?}} below denotes this, instead of ; and therefore must set flags. {{s?}} below denotes this, instead of
; duplicating tests. ; duplicating tests.
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test/CodeGen/ARM/fast-isel-fold.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
@a = global i8 1, align 1 @a = global i8 1, align 1
@b = global i16 2, align 2 @b = global i16 2, align 2
define void @t1() nounwind uwtable ssp { define void @t1() nounwind uwtable ssp {
; ARM: t1 ; ARM: t1
; ARM: ldrb ; ARM: ldrb
; ARM-NOT: uxtb ; ARM-NOT: uxtb
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test/CodeGen/ARM/fast-isel-frameaddr.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=DARWIN-ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=DARWIN-ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=LINUX-ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=LINUX-ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=DARWIN-THUMB2 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=DARWIN-THUMB2
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-linux-gnueabi | FileCheck %s --check-prefix=LINUX-THUMB2 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=thumbv7-linux-gnueabi | FileCheck %s --check-prefix=LINUX-THUMB2
define i8* @frameaddr_index0() nounwind { define i8* @frameaddr_index0() nounwind {
entry: entry:
; DARWIN-ARM-LABEL: frameaddr_index0: ; DARWIN-ARM-LABEL: frameaddr_index0:
; DARWIN-ARM: push {r7} ; DARWIN-ARM: push {r7}
; DARWIN-ARM: mov r7, sp ; DARWIN-ARM: mov r7, sp
; DARWIN-ARM: mov r0, r7 ; DARWIN-ARM: mov r0, r7
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test/CodeGen/ARM/fast-isel-icmp.ll

; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
define i32 @icmp_i16_signed(i16 %a, i16 %b) nounwind { define i32 @icmp_i16_signed(i16 %a, i16 %b) nounwind {
entry: entry:
; ARM: icmp_i16_signed ; ARM: icmp_i16_signed
; ARM: sxth r0, r0 ; ARM: sxth r0, r0
; ARM: sxth r1, r1 ; ARM: sxth r1, r1
; ARM: cmp r0, r1 ; ARM: cmp r0, r1
; THUMB: icmp_i16_signed ; THUMB: icmp_i16_signed
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test/CodeGen/ARM/fast-isel-indirectbr.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
define void @t1(i8* %x) { define void @t1(i8* %x) {
entry: entry:
; ARM: t1 ; ARM: t1
; THUMB: t1 ; THUMB: t1
br label %L0 br label %L0
L0: L0:
br label %L1 br label %L1
L1: L1:
indirectbr i8* %x, [ label %L0, label %L1 ] indirectbr i8* %x, [ label %L0, label %L1 ]
; ARM: bx r0 ; ARM: bx r0
; THUMB: mov pc, r0 ; THUMB: mov pc, r0
} }

test/CodeGen/ARM/fast-isel-intrinsic.ll

; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-LONG ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-LONG
; Note that some of these tests assume that relocations are either ; Note that some of these tests assume that relocations are either
; movw/movt or constant pool loads. Different platforms will select ; movw/movt or constant pool loads. Different platforms will select
; different approaches. ; different approaches.
@message1 = global [60 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 1 @message1 = global [60 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 1
@temp = common global [60 x i8] zeroinitializer, align 1 @temp = common global [60 x i8] zeroinitializer, align 1
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test/CodeGen/ARM/fast-isel-ldr-str-arm.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=ARM
define i32 @t1(i32* nocapture %ptr) nounwind readonly { define i32 @t1(i32* nocapture %ptr) nounwind readonly {
entry: entry:
; ARM: t1 ; ARM: t1
%add.ptr = getelementptr inbounds i32* %ptr, i32 1 %add.ptr = getelementptr inbounds i32* %ptr, i32 1
%0 = load i32* %add.ptr, align 4 %0 = load i32* %add.ptr, align 4
; ARM: ldr r{{[0-9]}}, [r0, #4] ; ARM: ldr r{{[0-9]}}, [r0, #4]
ret i32 %0 ret i32 %0
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test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll

; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
define i32 @t1(i32* nocapture %ptr) nounwind readonly { define i32 @t1(i32* nocapture %ptr) nounwind readonly {
entry: entry:
; THUMB: t1 ; THUMB: t1
%add.ptr = getelementptr inbounds i32* %ptr, i32 -1 %add.ptr = getelementptr inbounds i32* %ptr, i32 -1
%0 = load i32* %add.ptr, align 4 %0 = load i32* %add.ptr, align 4
; THUMB: ldr r{{[0-9]}}, [r0, #-4] ; THUMB: ldr r{{[0-9]}}, [r0, #-4]
ret i32 %0 ret i32 %0
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test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
; rdar://10418009 ; rdar://10418009
define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp { define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp {
entry: entry:
; ARM: t1 ; ARM: t1
%add.ptr = getelementptr inbounds i16* %a, i64 -8 %add.ptr = getelementptr inbounds i16* %a, i64 -8
%0 = load i16* %add.ptr, align 2 %0 = load i16* %add.ptr, align 2
; ARM: ldrh r0, [r0, #-16] ; ARM: ldrh r0, [r0, #-16]
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test/CodeGen/ARM/fast-isel-load-store-verify.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ALL ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ALL
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ALL ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ALL
; FIXME Add tests for thumbv7, they currently fail MI verification because ; FIXME Add tests for thumbv7, they currently fail MI verification because
; of a mismatch in register classes in uses. ; of a mismatch in register classes in uses.
; This test verifies that load/store instructions are properly generated, ; This test verifies that load/store instructions are properly generated,
; and that they pass MI verification (wasn't the case until 2013-06-08). ; and that they pass MI verification (wasn't the case until 2013-06-08).
@a = global i8 1, align 1 @a = global i8 1, align 1
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test/CodeGen/ARM/fast-isel-mvn.ll

; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=armv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM ; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=armv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=armv7-linux-gnueabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM ; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=armv7-linux-gnueabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=thumbv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM ; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=thumbv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -arm-use-movt=true -mtriple=thumbv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB ; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=true -mtriple=thumbv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB
; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -arm-use-movt=true -mtriple=armv7-apple-ios < %s | FileCheck %s --check-prefix=MOVT ; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=true -mtriple=armv7-apple-ios < %s | FileCheck %s --check-prefix=MOVT
; rdar://10412592 ; rdar://10412592
define void @t1() nounwind { define void @t1() nounwind {
entry: entry:
; CHECK-LABEL: t1 ; CHECK-LABEL: t1
; CHECK: mvn r0, #0 ; CHECK: mvn r0, #0
call void @foo(i32 -1) call void @foo(i32 -1)
ret void ret void
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test/CodeGen/ARM/fast-isel-pic.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF
@g = global i32 0, align 4 @g = global i32 0, align 4
define i32 @LoadGV() { define i32 @LoadGV() {
entry: entry:
; THUMB: LoadGV ; THUMB: LoadGV
; THUMB: movw [[reg0:r[0-9]+]], ; THUMB: movw [[reg0:r[0-9]+]],
; THUMB: movt [[reg0]], ; THUMB: movt [[reg0]],
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test/CodeGen/ARM/fast-isel-redefinition.ll

; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -optimize-regalloc -regalloc=basic < %s ; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -optimize-regalloc -regalloc=basic < %s
; This isn't exactly a useful set of command-line options, but check that it ; This isn't exactly a useful set of command-line options, but check that it
; doesn't crash. (It was crashing because a register was getting redefined.) ; doesn't crash. (It was crashing because a register was getting redefined.)
target triple = "thumbv7-apple-macosx10.6.7" target triple = "thumbv7-apple-macosx10.6.7"
define i32 @f(i32* %x) nounwind ssp { define i32 @f(i32* %x) nounwind ssp {
%y = getelementptr inbounds i32* %x, i32 5000 %y = getelementptr inbounds i32* %x, i32 5000
%tmp103 = load i32* %y, align 4 %tmp103 = load i32* %y, align 4
ret i32 %tmp103 ret i32 %tmp103
} }

test/CodeGen/ARM/fast-isel-ret.ll

; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s
; Sign-extend of i1 currently not supported by fast-isel ; Sign-extend of i1 currently not supported by fast-isel
;define signext i1 @ret0(i1 signext %a) nounwind uwtable ssp { ;define signext i1 @ret0(i1 signext %a) nounwind uwtable ssp {
;entry: ;entry:
; ret i1 %a ; ret i1 %a
;} ;}
define zeroext i1 @ret1(i1 signext %a) nounwind uwtable ssp { define zeroext i1 @ret1(i1 signext %a) nounwind uwtable ssp {
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test/CodeGen/ARM/fast-isel-select.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv8-apple-ios | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv8-apple-ios | FileCheck %s --check-prefix=THUMB
define i32 @t1(i1 %c) nounwind readnone { define i32 @t1(i1 %c) nounwind readnone {
entry: entry:
; ARM: t1 ; ARM: t1
; ARM: movw r{{[1-9]}}, #10 ; ARM: movw r{{[1-9]}}, #10
; ARM: cmp r0, #0 ; ARM: cmp r0, #0
; ARM: moveq r{{[1-9]}}, #20 ; ARM: moveq r{{[1-9]}}, #20
; ARM: mov r0, r{{[1-9]}} ; ARM: mov r0, r{{[1-9]}}
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test/CodeGen/ARM/fast-isel-shifter.ll

; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
define i32 @shl() nounwind ssp { define i32 @shl() nounwind ssp {
entry: entry:
; ARM: shl ; ARM: shl
; ARM: lsl r0, r0, #2 ; ARM: lsl r0, r0, #2
%shl = shl i32 -1, 2 %shl = shl i32 -1, 2
ret i32 %shl ret i32 %shl
} }
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test/CodeGen/ARM/fast-isel-static.ll

; RUN: llc < %s -mtriple=thumbv7-apple-ios -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=CHECK-LONG %s ; RUN: llc < %s -mtriple=thumbv7-apple-ios -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static -arm-long-calls | FileCheck -check-prefix=CHECK-LONG %s
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=CHECK-LONG %s ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static -arm-long-calls | FileCheck -check-prefix=CHECK-LONG %s
; RUN: llc < %s -mtriple=thumbv7-apple-ios -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s ; RUN: llc < %s -mtriple=thumbv7-apple-ios -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s
define void @myadd(float* %sum, float* %addend) nounwind { define void @myadd(float* %sum, float* %addend) nounwind {
entry: entry:
%sum.addr = alloca float*, align 4 %sum.addr = alloca float*, align 4
%addend.addr = alloca float*, align 4 %addend.addr = alloca float*, align 4
store float* %sum, float** %sum.addr, align 4 store float* %sum, float** %sum.addr, align 4
store float* %addend, float** %addend.addr, align 4 store float* %addend, float** %addend.addr, align 4
%tmp = load float** %sum.addr, align 4 %tmp = load float** %sum.addr, align 4
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test/CodeGen/ARM/fast-isel-vararg.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
define i32 @VarArg() nounwind { define i32 @VarArg() nounwind {
entry: entry:
%i = alloca i32, align 4 %i = alloca i32, align 4
%j = alloca i32, align 4 %j = alloca i32, align 4
%k = alloca i32, align 4 %k = alloca i32, align 4
%m = alloca i32, align 4 %m = alloca i32, align 4
%n = alloca i32, align 4 %n = alloca i32, align 4
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test/CodeGen/ARM/fast-isel.ll

; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
; Very basic fast-isel functionality. ; Very basic fast-isel functionality.
define i32 @test0(i32 %a, i32 %b) nounwind { define i32 @test0(i32 %a, i32 %b) nounwind {
entry: entry:
%a.addr = alloca i32, align 4 %a.addr = alloca i32, align 4
%b.addr = alloca i32, align 4 %b.addr = alloca i32, align 4
store i32 %a, i32* %a.addr store i32 %a, i32* %a.addr
store i32 %b, i32* %b.addr store i32 %b, i32* %b.addr
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test/CodeGen/Mips/Fast-ISel/br1.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@b = global i32 1, align 4 @b = global i32 1, align 4
@i = global i32 0, align 4 @i = global i32 0, align 4
@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br() #0 { define void @br() #0 {
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test/CodeGen/Mips/Fast-ISel/callabi.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s -check-prefix=mips32r2 ; RUN: < %s | FileCheck %s -check-prefix=mips32r2
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s -check-prefix=mips32 ; RUN: < %s | FileCheck %s -check-prefix=mips32
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s -check-prefix=CHECK2 ; RUN: < %s | FileCheck %s -check-prefix=CHECK2
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s -check-prefix=CHECK2 ; RUN: < %s | FileCheck %s -check-prefix=CHECK2
@c1 = global i8 -45, align 1 @c1 = global i8 -45, align 1
@uc1 = global i8 27, align 1 @uc1 = global i8 27, align 1
@s1 = global i16 -1789, align 2 @s1 = global i16 -1789, align 2
@us1 = global i16 1256, align 2 @us1 = global i16 1256, align 2
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test/CodeGen/Mips/Fast-ISel/fpcmpa.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@f1 = common global float 0.000000e+00, align 4 @f1 = common global float 0.000000e+00, align 4
@f2 = common global float 0.000000e+00, align 4 @f2 = common global float 0.000000e+00, align 4
@b1 = common global i32 0, align 4 @b1 = common global i32 0, align 4
@d1 = common global double 0.000000e+00, align 8 @d1 = common global double 0.000000e+00, align 8
@d2 = common global double 0.000000e+00, align 8 @d2 = common global double 0.000000e+00, align 8
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test/CodeGen/Mips/Fast-ISel/fpext.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@f = global float 0x40147E6B80000000, align 4 @f = global float 0x40147E6B80000000, align 4
@d_f = common global double 0.000000e+00, align 8 @d_f = common global double 0.000000e+00, align 8
@.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1 @.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @dv() #0 { define void @dv() #0 {
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test/CodeGen/Mips/Fast-ISel/fpintconv.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@f = global float 0x40D6E83280000000, align 4 @f = global float 0x40D6E83280000000, align 4
@d = global double 0x4132D68780000000, align 8 @d = global double 0x4132D68780000000, align 8
@i_f = common global i32 0, align 4 @i_f = common global i32 0, align 4
@i_d = common global i32 0, align 4 @i_d = common global i32 0, align 4
@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
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test/CodeGen/Mips/Fast-ISel/fptrunc.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@d = global double 0x40147E6B74DF0446, align 8 @d = global double 0x40147E6B74DF0446, align 8
@f = common global float 0.000000e+00, align 4 @f = common global float 0.000000e+00, align 4
@.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1 @.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @fv() #0 { define void @fv() #0 {
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test/CodeGen/Mips/Fast-ISel/icmpa.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@c = global i32 4, align 4 @c = global i32 4, align 4
@d = global i32 9, align 4 @d = global i32 9, align 4
@uc = global i32 4, align 4 @uc = global i32 4, align 4
@ud = global i32 9, align 4 @ud = global i32 9, align 4
@b1 = common global i32 0, align 4 @b1 = common global i32 0, align 4
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test/CodeGen/Mips/Fast-ISel/loadstore2.ll

; ModuleID = 'loadstore2.c' ; ModuleID = 'loadstore2.c'
target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64" target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
target triple = "mips--linux-gnu" target triple = "mips--linux-gnu"
@c2 = common global i8 0, align 1 @c2 = common global i8 0, align 1
@c1 = common global i8 0, align 1 @c1 = common global i8 0, align 1
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@s2 = common global i16 0, align 2 @s2 = common global i16 0, align 2
@s1 = common global i16 0, align 2 @s1 = common global i16 0, align 2
@i2 = common global i32 0, align 4 @i2 = common global i32 0, align 4
@i1 = common global i32 0, align 4 @i1 = common global i32 0, align 4
@f2 = common global float 0.000000e+00, align 4 @f2 = common global float 0.000000e+00, align 4
@f1 = common global float 0.000000e+00, align 4 @f1 = common global float 0.000000e+00, align 4
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test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s -check-prefix=mips32r2 ; RUN: < %s | FileCheck %s -check-prefix=mips32r2
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s -check-prefix=mips32 ; RUN: < %s | FileCheck %s -check-prefix=mips32
@b2 = global i8 0, align 1 @b2 = global i8 0, align 1
@b1 = global i8 1, align 1 @b1 = global i8 1, align 1
@uc1 = global i8 0, align 1 @uc1 = global i8 0, align 1
@uc2 = global i8 -1, align 1 @uc2 = global i8 -1, align 1
@sc1 = global i8 -128, align 1 @sc1 = global i8 -128, align 1
@sc2 = global i8 127, align 1 @sc2 = global i8 127, align 1
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test/CodeGen/Mips/Fast-ISel/loadstrconst.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1
@s = common global i8* null, align 4 @s = common global i8* null, align 4
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @foo() #0 { define void @foo() #0 {
entry: entry:
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test/CodeGen/Mips/Fast-ISel/nullvoid.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @foo() { define void @foo() {
entry: entry:
ret void ret void
; CHECK: jr $ra ; CHECK: jr $ra
} }

test/CodeGen/Mips/Fast-ISel/overflt.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@x = common global [128000 x float] zeroinitializer, align 4 @x = common global [128000 x float] zeroinitializer, align 4
@y = global float* getelementptr inbounds ([128000 x float]* @x, i32 0, i32 0), align 4 @y = global float* getelementptr inbounds ([128000 x float]* @x, i32 0, i32 0), align 4
@result = common global float 0.000000e+00, align 4 @result = common global float 0.000000e+00, align 4
@.str = private unnamed_addr constant [5 x i8] c"%f \0A\00", align 1 @.str = private unnamed_addr constant [5 x i8] c"%f \0A\00", align 1
; Function Attrs: nounwind ; Function Attrs: nounwind
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test/CodeGen/Mips/Fast-ISel/retabi.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@i = global i32 75, align 4 @i = global i32 75, align 4
@s = global i16 -345, align 2 @s = global i16 -345, align 2
@c = global i8 118, align 1 @c = global i8 118, align 1
@f = global float 0x40BE623360000000, align 4 @f = global float 0x40BE623360000000, align 4
@d = global double 1.298330e+03, align 8 @d = global double 1.298330e+03, align 8
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test/CodeGen/Mips/Fast-ISel/simplestore.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@abcd = external global i32 @abcd = external global i32
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @foo() { define void @foo() {
entry: entry:
store i32 12345, i32* @abcd, align 4 store i32 12345, i32* @abcd, align 4
; CHECK: addiu $[[REG1:[0-9]+]], $zero, 12345 ; CHECK: addiu $[[REG1:[0-9]+]], $zero, 12345
; CHECK: lw $[[REG2:[0-9]+]], %got(abcd)(${{[0-9]+}}) ; CHECK: lw $[[REG2:[0-9]+]], %got(abcd)(${{[0-9]+}})
; CHECK: sw $[[REG1]], 0($[[REG2]]) ; CHECK: sw $[[REG1]], 0($[[REG2]])
ret void ret void
} }

test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s -check-prefix=mips32r2 ; RUN: < %s | FileCheck %s -check-prefix=mips32r2
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s -check-prefix=mips32 ; RUN: < %s | FileCheck %s -check-prefix=mips32
@f = common global float 0.000000e+00, align 4 @f = common global float 0.000000e+00, align 4
@de = common global double 0.000000e+00, align 8 @de = common global double 0.000000e+00, align 8
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f1() #0 { define void @f1() #0 {
entry: entry:
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test/CodeGen/Mips/Fast-ISel/simplestorei.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@ijk = external global i32 @ijk = external global i32
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @si2_1() #0 { define void @si2_1() #0 {
entry: entry:
store i32 32767, i32* @ijk, align 4 store i32 32767, i32* @ijk, align 4
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test/CodeGen/PowerPC/fast-isel-GEP-coalesce.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
%struct.A = type { i32, [2 x [2 x i32]], i8, [3 x [3 x [3 x i32]]] } %struct.A = type { i32, [2 x [2 x i32]], i8, [3 x [3 x [3 x i32]]] }
%struct.B = type { i32, [2 x [2 x [2 x %struct.A]]] } %struct.B = type { i32, [2 x [2 x [2 x %struct.A]]] }
@arr = common global [2 x [2 x [2 x [2 x [2 x i32]]]]] zeroinitializer, align 4 @arr = common global [2 x [2 x [2 x [2 x [2 x i32]]]]] zeroinitializer, align 4
@A = common global [3 x [3 x %struct.A]] zeroinitializer, align 4 @A = common global [3 x [3 x %struct.A]] zeroinitializer, align 4
@B = common global [2 x [2 x [2 x %struct.B]]] zeroinitializer, align 4 @B = common global [2 x [2 x [2 x %struct.B]]] zeroinitializer, align 4
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test/CodeGen/PowerPC/fast-isel-binary.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
; Test add with non-legal types ; Test add with non-legal types
define void @add_i8(i8 %a, i8 %b) nounwind ssp { define void @add_i8(i8 %a, i8 %b) nounwind ssp {
entry: entry:
; ELF64: add_i8 ; ELF64: add_i8
%a.addr = alloca i8, align 4 %a.addr = alloca i8, align 4
%0 = add i8 %a, %b %0 = add i8 %a, %b
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test/CodeGen/PowerPC/fast-isel-br-const.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp { define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp {
entry: entry:
; ELF64: t1 ; ELF64: t1
%x = add i32 %a, %b %x = add i32 %a, %b
br i1 1, label %if.then, label %if.else br i1 1, label %if.then, label %if.else
; ELF64-NOT: b {{\.?}}LBB0_1 ; ELF64-NOT: b {{\.?}}LBB0_1
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test/CodeGen/PowerPC/fast-isel-call.ll

; FIXME: FastISel currently returns false if it hits code that uses VSX ; FIXME: FastISel currently returns false if it hits code that uses VSX
; registers and with -fast-isel-abort turned on the test case will then fail. ; registers and with -fast-isel-abort=1 turned on the test case will then fail.
; When fastisel better supports VSX fix up this test case. ; When fastisel better supports VSX fix up this test case.
; ;
; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
define i32 @t1(i8 signext %a) nounwind { define i32 @t1(i8 signext %a) nounwind {
%1 = sext i8 %a to i32 %1 = sext i8 %a to i32
ret i32 %1 ret i32 %1
} }
define i32 @t2(i8 zeroext %a) nounwind { define i32 @t2(i8 zeroext %a) nounwind {
%1 = zext i8 %a to i32 %1 = zext i8 %a to i32
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test/CodeGen/PowerPC/fast-isel-cmp-imm.ll

; FIXME: FastISel currently returns false if it hits code that uses VSX ; FIXME: FastISel currently returns false if it hits code that uses VSX
; registers and with -fast-isel-abort turned on the test case will then fail. ; registers and with -fast-isel-abort=1 turned on the test case will then fail.
; When fastisel better supports VSX fix up this test case. ; When fastisel better supports VSX fix up this test case.
; ;
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
define void @t1a(float %a) uwtable ssp { define void @t1a(float %a) uwtable ssp {
entry: entry:
; ELF64: t1a ; ELF64: t1a
%cmp = fcmp oeq float %a, 0.000000e+00 %cmp = fcmp oeq float %a, 0.000000e+00
; ELF64: addis ; ELF64: addis
; ELF64: lfs ; ELF64: lfs
; ELF64: fcmpu ; ELF64: fcmpu
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
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test/CodeGen/PowerPC/fast-isel-const.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
define zeroext i1 @testi1(i8 %in) nounwind uwtable ssp { define zeroext i1 @testi1(i8 %in) nounwind uwtable ssp {
entry: entry:
%c = icmp eq i8 %in, 5 %c = icmp eq i8 %in, 5
br i1 %c, label %true, label %false br i1 %c, label %true, label %false
; ELF64-LABEL: @testi1 ; ELF64-LABEL: @testi1
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test/CodeGen/PowerPC/fast-isel-conversion-p5.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr5 | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr5 | FileCheck %s --check-prefix=ELF64
; Test sitofp ; Test sitofp
define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp { define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp {
entry: entry:
; ELF64: sitofp_double_i32 ; ELF64: sitofp_double_i32
%b.addr = alloca double, align 8 %b.addr = alloca double, align 8
%conv = sitofp i32 %a to double %conv = sitofp i32 %a to double
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test/CodeGen/PowerPC/fast-isel-conversion.ll

; FIXME: FastISel currently returns false if it hits code that uses VSX ; FIXME: FastISel currently returns false if it hits code that uses VSX
; registers and with -fast-isel-abort turned on the test case will then fail. ; registers and with -fast-isel-abort=1 turned on the test case will then fail.
; When fastisel better supports VSX fix up this test case. ; When fastisel better supports VSX fix up this test case.
; ;
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s --check-prefix=ELF64LE ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s --check-prefix=ELF64LE
; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970 ; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970
;; Tests for 970 don't use -fast-isel-abort because we intentionally punt ;; Tests for 970 don't use -fast-isel-abort=1 because we intentionally punt
;; to SelectionDAG in some cases. ;; to SelectionDAG in some cases.
; Test sitofp ; Test sitofp
define void @sitofp_single_i64(i64 %a, float %b) nounwind ssp { define void @sitofp_single_i64(i64 %a, float %b) nounwind ssp {
entry: entry:
; ELF64: sitofp_single_i64 ; ELF64: sitofp_single_i64
; ELF64LE: sitofp_single_i64 ; ELF64LE: sitofp_single_i64
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test/CodeGen/PowerPC/fast-isel-crash.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7
; Ensure this doesn't crash. ; Ensure this doesn't crash.
%union.anon = type { <16 x i32> } %union.anon = type { <16 x i32> }
@__md0 = external global [137 x i8] @__md0 = external global [137 x i8]
define internal void @stretch(<4 x i8> addrspace(1)* %src, <4 x i8> addrspace(1)* %dst, i32 %width, i32 %height, i32 %iLS, i32 %oLS, <2 x float> %c, <4 x float> %param) nounwind { define internal void @stretch(<4 x i8> addrspace(1)* %src, <4 x i8> addrspace(1)* %dst, i32 %width, i32 %height, i32 %iLS, i32 %oLS, <2 x float> %c, <4 x float> %param) nounwind {
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test/CodeGen/PowerPC/fast-isel-ext.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
; zext ; zext
define i32 @zext_8_32(i8 %a) nounwind ssp { define i32 @zext_8_32(i8 %a) nounwind ssp {
; ELF64: zext_8_32 ; ELF64: zext_8_32
%r = zext i8 %a to i32 %r = zext i8 %a to i32
; ELF64: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31 ; ELF64: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31
ret i32 %r ret i32 %r
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test/CodeGen/PowerPC/fast-isel-fold.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
@a = global i8 1, align 1 @a = global i8 1, align 1
@b = global i16 2, align 2 @b = global i16 2, align 2
@c = global i32 4, align 4 @c = global i32 4, align 4
define void @t1() nounwind uwtable ssp { define void @t1() nounwind uwtable ssp {
; ELF64: t1 ; ELF64: t1
%1 = load i8* @a, align 1 %1 = load i8* @a, align 1
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test/CodeGen/PowerPC/fast-isel-indirectbr.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
define void @t1(i8* %x) { define void @t1(i8* %x) {
entry: entry:
; ELF64: t1 ; ELF64: t1
br label %L0 br label %L0
L0: L0:
br label %L1 br label %L1
L1: L1:
indirectbr i8* %x, [ label %L0, label %L1 ] indirectbr i8* %x, [ label %L0, label %L1 ]
; ELF64: mtctr 3 ; ELF64: mtctr 3
; ELF64: bctr ; ELF64: bctr
} }

test/CodeGen/PowerPC/fast-isel-load-store.ll

; FIXME: FastISel currently returns false if it hits code that uses VSX ; FIXME: FastISel currently returns false if it hits code that uses VSX
; registers and with -fast-isel-abort turned on the test case will then fail. ; registers and with -fast-isel-abort=1 turned on the test case will then fail.
; When fastisel better supports VSX fix up this test case. ; When fastisel better supports VSX fix up this test case.
; ;
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel -fast-isel-abort -mattr=-vsx -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel -fast-isel-abort=1 -mattr=-vsx -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
; This test verifies that load/store instructions are properly generated, ; This test verifies that load/store instructions are properly generated,
; and that they pass MI verification. ; and that they pass MI verification.
@a = global i8 1, align 1 @a = global i8 1, align 1
@b = global i16 2, align 2 @b = global i16 2, align 2
@c = global i32 4, align 4 @c = global i32 4, align 4
@d = global i64 8, align 8 @d = global i64 8, align 8
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test/CodeGen/PowerPC/fast-isel-redefinition.ll

; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -optimize-regalloc -regalloc=basic -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s ; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -optimize-regalloc -regalloc=basic -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
; This isn't exactly a useful set of command-line options, but check that it ; This isn't exactly a useful set of command-line options, but check that it
; doesn't crash. (It crashed formerly on ARM, and proved useful in ; doesn't crash. (It crashed formerly on ARM, and proved useful in
; discovering a bug on PowerPC as well.) ; discovering a bug on PowerPC as well.)
define i32 @f(i32* %x) nounwind ssp { define i32 @f(i32* %x) nounwind ssp {
%y = getelementptr inbounds i32* %x, i32 5000 %y = getelementptr inbounds i32* %x, i32 5000
%tmp103 = load i32* %y, align 4 %tmp103 = load i32* %y, align 4
ret i32 %tmp103 ret i32 %tmp103
} }

test/CodeGen/PowerPC/fast-isel-ret.ll

; FIXME: FastISel currently returns false if it hits code that uses VSX ; FIXME: FastISel currently returns false if it hits code that uses VSX
; registers and with -fast-isel-abort turned on the test case will then fail. ; registers and with -fast-isel-abort=1 turned on the test case will then fail.
; When fastisel better supports VSX fix up this test case. ; When fastisel better supports VSX fix up this test case.
; ;
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
define zeroext i1 @rettrue() nounwind uwtable ssp { define zeroext i1 @rettrue() nounwind uwtable ssp {
entry: entry:
; ELF64-LABEL: rettrue ; ELF64-LABEL: rettrue
; ELF64: li 3, 1 ; ELF64: li 3, 1
; ELF64: blr ; ELF64: blr
ret i1 true ret i1 true
} }
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test/CodeGen/PowerPC/fast-isel-shifter.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
define i32 @shl() nounwind ssp { define i32 @shl() nounwind ssp {
entry: entry:
; ELF64: shl ; ELF64: shl
; ELF64: slw ; ELF64: slw
%shl = shl i32 -1, 2 %shl = shl i32 -1, 2
ret i32 %shl ret i32 %shl
} }
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test/CodeGen/PowerPC/ppc64-fastcc-fast-isel.ll

; RUN: llc -mcpu=pwr7 -mattr=-vsx -fast-isel -fast-isel-abort < %s | FileCheck %s ; RUN: llc -mcpu=pwr7 -mattr=-vsx -fast-isel -fast-isel-abort=1 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define fastcc i64 @g1(i64 %g1, double %f1, i64 %g2, double %f2, i64 %g3, double %f3, i64 %g4, double %f4) #0 { define fastcc i64 @g1(i64 %g1, double %f1, i64 %g2, double %f2, i64 %g3, double %f3, i64 %g4, double %f4) #0 {
ret i64 %g1 ret i64 %g1
; CHECK-LABEL: @g1 ; CHECK-LABEL: @g1
; CHECK-NOT: mr 3, ; CHECK-NOT: mr 3,
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test/CodeGen/PowerPC/ppc64-patchpoint.ll

; RUN: llc < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE ; RUN: llc < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
; RUN: llc -fast-isel -fast-isel-abort < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE ; RUN: llc -fast-isel -fast-isel-abort=1 < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -fast-isel -fast-isel-abort < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -fast-isel -fast-isel-abort=1 < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Trivial patchpoint codegen ; Trivial patchpoint codegen
; ;
define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry: entry:
; CHECK-LABEL: trivial_patchpoint_codegen: ; CHECK-LABEL: trivial_patchpoint_codegen:
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test/CodeGen/Thumb2/large-call.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mcpu=cortex-a8 | FileCheck %s ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mcpu=cortex-a8 | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
target triple = "thumbv7-apple-ios0.0.0" target triple = "thumbv7-apple-ios0.0.0"
; This test case would clobber the outgoing call arguments by writing to the ; This test case would clobber the outgoing call arguments by writing to the
; emergency spill slots at [sp, #4] or [sp, #8] without adjusting the stack ; emergency spill slots at [sp, #4] or [sp, #8] without adjusting the stack
; pointer first. ; pointer first.
; CHECK: main ; CHECK: main
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test/CodeGen/X86/fast-isel-args-fail2.ll

; RUN: not --crash llc < %s -fast-isel -fast-isel-abort-args -mtriple=x86_64-apple-darwin10 ; RUN: not --crash llc < %s -fast-isel -fast-isel-abort=2 -mtriple=x86_64-apple-darwin10
; REQUIRES: asserts ; REQUIRES: asserts
%struct.s0 = type { x86_fp80, x86_fp80 } %struct.s0 = type { x86_fp80, x86_fp80 }
; FastISel cannot handle this case yet. Make sure that we abort. ; FastISel cannot handle this case yet. Make sure that we abort.
define i8* @args_fail(%struct.s0* byval nocapture readonly align 16 %y) { define i8* @args_fail(%struct.s0* byval nocapture readonly align 16 %y) {
%1 = bitcast %struct.s0* %y to i8* %1 = bitcast %struct.s0* %y to i8*
ret i8* %1 ret i8* %1
} }

test/CodeGen/X86/fast-isel-args.ll

; RUN: llc < %s -fast-isel -fast-isel-abort -fast-isel-abort-args -verify-machineinstrs -mtriple=x86_64-apple-darwin10 ; RUN: llc < %s -fast-isel -fast-isel-abort=2 -verify-machineinstrs -mtriple=x86_64-apple-darwin10
; Just make sure these don't abort when lowering the arguments. ; Just make sure these don't abort when lowering the arguments.
define i32 @t1(i32 %a, i32 %b, i32 %c) { define i32 @t1(i32 %a, i32 %b, i32 %c) {
entry: entry:
%add = add nsw i32 %b, %a %add = add nsw i32 %b, %a
%add1 = add nsw i32 %add, %c %add1 = add nsw i32 %add, %c
ret i32 %add1 ret i32 %add1
} }
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test/CodeGen/X86/fast-isel-branch_weights.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10 | FileCheck %s ; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 | FileCheck %s
; Test if the BBs are reordred according to their branch weights. ; Test if the BBs are reordred according to their branch weights.
define i64 @branch_weights_test(i64 %a, i64 %b) { define i64 @branch_weights_test(i64 %a, i64 %b) {
; CHECK-LABEL: branch_weights_test ; CHECK-LABEL: branch_weights_test
; CHECK-LABEL: success ; CHECK-LABEL: success
; CHECK-LABEL: fail ; CHECK-LABEL: fail
%1 = icmp ult i64 %a, %b %1 = icmp ult i64 %a, %b
br i1 %1, label %fail, label %success, !prof !0 br i1 %1, label %fail, label %success, !prof !0
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test/CodeGen/X86/fast-isel-call.ll

; RUN: llc < %s -O0 -fast-isel-abort -march=x86 | FileCheck %s ; RUN: llc < %s -O0 -fast-isel-abort=1 -march=x86 | FileCheck %s
%struct.s = type {i32, i32, i32} %struct.s = type {i32, i32, i32}
define i32 @test1() nounwind { define i32 @test1() nounwind {
tak: tak:
%tmp = call i1 @foo() %tmp = call i1 @foo()
br i1 %tmp, label %BB1, label %BB2 br i1 %tmp, label %BB1, label %BB2
BB1: BB1:
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test/CodeGen/X86/fast-isel-cmp-branch2.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10 | FileCheck %s ; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 | FileCheck %s
define i32 @fcmp_oeq(float %x, float %y) { define i32 @fcmp_oeq(float %x, float %y) {
; CHECK-LABEL: fcmp_oeq ; CHECK-LABEL: fcmp_oeq
; CHECK: ucomiss %xmm1, %xmm0 ; CHECK: ucomiss %xmm1, %xmm0
; CHECK-NEXT: jne {{LBB.+_1}} ; CHECK-NEXT: jne {{LBB.+_1}}
; CHECK-NEXT: jnp {{LBB.+_2}} ; CHECK-NEXT: jnp {{LBB.+_2}}
%1 = fcmp oeq float %x, %y %1 = fcmp oeq float %x, %y
br i1 %1, label %bb1, label %bb2 br i1 %1, label %bb1, label %bb2
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test/CodeGen/X86/fast-isel-cmp-branch3.ll

; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10 | FileCheck %s ; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 | FileCheck %s
define i32 @fcmp_oeq1(float %x) { define i32 @fcmp_oeq1(float %x) {
; CHECK-LABEL: fcmp_oeq1 ; CHECK-LABEL: fcmp_oeq1
; CHECK: ucomiss %xmm0, %xmm0 ; CHECK: ucomiss %xmm0, %xmm0
; CHECK-NEXT: jp {{LBB.+_1}} ; CHECK-NEXT: jp {{LBB.+_1}}
%1 = fcmp oeq float %x, %x %1 = fcmp oeq float %x, %x
br i1 %1, label %bb1, label %bb2 br i1 %1, label %bb1, label %bb2
bb2: bb2:
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test/CodeGen/X86/fast-isel-cmp.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s --check-prefix=SDAG ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s --check-prefix=SDAG
; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10 | FileCheck %s --check-prefix=FAST ; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 | FileCheck %s --check-prefix=FAST
define zeroext i1 @fcmp_oeq(float %x, float %y) { define zeroext i1 @fcmp_oeq(float %x, float %y) {
; SDAG-LABEL: fcmp_oeq ; SDAG-LABEL: fcmp_oeq
; SDAG: cmpeqss %xmm1, %xmm0 ; SDAG: cmpeqss %xmm1, %xmm0
; SDAG-NEXT: movd %xmm0, %eax ; SDAG-NEXT: movd %xmm0, %eax
; SDAG-NEXT: andl $1, %eax ; SDAG-NEXT: andl $1, %eax
; FAST-LABEL: fcmp_oeq ; FAST-LABEL: fcmp_oeq
; FAST: ucomiss %xmm1, %xmm0 ; FAST: ucomiss %xmm1, %xmm0
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test/CodeGen/X86/fast-isel-divrem-x86-64.ll

; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
define i64 @test_sdiv64(i64 %dividend, i64 %divisor) nounwind { define i64 @test_sdiv64(i64 %dividend, i64 %divisor) nounwind {
entry: entry:
%result = sdiv i64 %dividend, %divisor %result = sdiv i64 %dividend, %divisor
ret i64 %result ret i64 %result
} }
; CHECK-LABEL: test_sdiv64: ; CHECK-LABEL: test_sdiv64:
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test/CodeGen/X86/fast-isel-divrem.ll

; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
define i8 @test_sdiv8(i8 %dividend, i8 %divisor) nounwind { define i8 @test_sdiv8(i8 %dividend, i8 %divisor) nounwind {
entry: entry:
%result = sdiv i8 %dividend, %divisor %result = sdiv i8 %dividend, %divisor
ret i8 %result ret i8 %result
} }
; CHECK-LABEL: test_sdiv8: ; CHECK-LABEL: test_sdiv8:
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test/CodeGen/X86/fast-isel-double-half-convertion.ll

; RUN: llc -fast-isel -fast-isel-abort -mtriple=x86_64-unknown-unknown -mattr=+f16c < %s ; RUN: llc -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+f16c < %s
; XFAIL: * ; XFAIL: *
; In the future, we might want to teach fast-isel how to expand a double-to-half ; In the future, we might want to teach fast-isel how to expand a double-to-half
; conversion into a double-to-float conversion immediately followed by a ; conversion into a double-to-float conversion immediately followed by a
; float-to-half conversion. For now, fast-isel is expected to fail. ; float-to-half conversion. For now, fast-isel is expected to fail.
define double @test_fp16_to_fp64(i32 %a) { define double @test_fp16_to_fp64(i32 %a) {
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test/CodeGen/X86/fast-isel-extract.ll

; RUN: llc < %s -mtriple x86_64-apple-darwin11 -O0 -fast-isel-abort | FileCheck %s ; RUN: llc < %s -mtriple x86_64-apple-darwin11 -O0 -fast-isel-abort=1 | FileCheck %s
%struct.x = type { i64, i64 } %struct.x = type { i64, i64 }
%addovf = type { i32, i1 } %addovf = type { i32, i1 }
declare %struct.x @f() declare %struct.x @f()
define void @test1(i64*) nounwind ssp { define void @test1(i64*) nounwind ssp {
%2 = tail call %struct.x @f() nounwind %2 = tail call %struct.x @f() nounwind
%3 = extractvalue %struct.x %2, 0 %3 = extractvalue %struct.x %2, 0
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test/CodeGen/X86/fast-isel-float-half-convertion.ll

; RUN: llc -fast-isel -fast-isel-abort -asm-verbose=false -mtriple=x86_64-unknown-unknown -mattr=+f16c < %s | FileCheck %s ; RUN: llc -fast-isel -fast-isel-abort=1 -asm-verbose=false -mtriple=x86_64-unknown-unknown -mattr=+f16c < %s | FileCheck %s
; Verify that fast-isel correctly expands float-half conversions. ; Verify that fast-isel correctly expands float-half conversions.
define i16 @test_fp32_to_fp16(float %a) { define i16 @test_fp32_to_fp16(float %a) {
; CHECK-LABEL: test_fp32_to_fp16: ; CHECK-LABEL: test_fp32_to_fp16:
; CHECK: vcvtps2ph $0, %xmm0, %xmm0 ; CHECK: vcvtps2ph $0, %xmm0, %xmm0
; CHECK-NEXT: vmovd %xmm0, %eax ; CHECK-NEXT: vmovd %xmm0, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
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test/CodeGen/X86/fast-isel-fneg.ll

; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10 | FileCheck %s ; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 | FileCheck %s
; RUN: llc < %s -fast-isel -march=x86 -mattr=+sse2 | FileCheck --check-prefix=SSE2 %s ; RUN: llc < %s -fast-isel -march=x86 -mattr=+sse2 | FileCheck --check-prefix=SSE2 %s
; SSE2: xor ; SSE2: xor
; SSE2: xor ; SSE2: xor
; SSE2-NOT: xor ; SSE2-NOT: xor
; CHECK-LABEL: doo: ; CHECK-LABEL: doo:
; CHECK: xor ; CHECK: xor
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test/CodeGen/X86/fast-isel-fold-mem.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin | FileCheck %s ; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin | FileCheck %s
define i64 @fold_load(i64* %a, i64 %b) { define i64 @fold_load(i64* %a, i64 %b) {
; CHECK-LABEL: fold_load ; CHECK-LABEL: fold_load
; CHECK: addq (%rdi), %rsi ; CHECK: addq (%rdi), %rsi
; CHECK-NEXT: movq %rsi, %rax ; CHECK-NEXT: movq %rsi, %rax
%1 = load i64* %a, align 8 %1 = load i64* %a, align 8
%2 = add i64 %1, %b %2 = add i64 %1, %b
ret i64 %2 ret i64 %2
} }

test/CodeGen/X86/fast-isel-fptrunc-fpext.ll

; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=ALL --check-prefix=SSE ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=ALL --check-prefix=AVX ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=ALL --check-prefix=AVX
; ;
; Verify that fast-isel doesn't select legacy SSE instructions on targets that ; Verify that fast-isel doesn't select legacy SSE instructions on targets that
; feature AVX. ; feature AVX.
; ;
; Test cases are obtained from the following code snippet: ; Test cases are obtained from the following code snippet:
; /// ; ///
; double single_to_double_rr(float x) { ; double single_to_double_rr(float x) {
; return (double)x; ; return (double)x;
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test/CodeGen/X86/fast-isel-i1.ll

; RUN: llc < %s -mtriple=i686-apple-darwin10 -fast-isel -fast-isel-abort | FileCheck %s ; RUN: llc < %s -mtriple=i686-apple-darwin10 -fast-isel -fast-isel-abort=1 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 | FileCheck %s
declare i32 @test1a(i32) declare i32 @test1a(i32)
define i32 @test1(i32 %x) nounwind { define i32 @test1(i32 %x) nounwind {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: andb $1, % ; CHECK: andb $1, %
%y = add i32 %x, -3 %y = add i32 %x, -3
%t = call i32 @test1a(i32 %y) %t = call i32 @test1a(i32 %y)
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test/CodeGen/X86/fast-isel-int-float-conversion.ll

; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+sse2 -O0 --fast-isel-abort < %s | FileCheck %s --check-prefix=ALL --check-prefix=SSE2 ; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+sse2 -O0 --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=ALL --check-prefix=SSE2
; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx -O0 --fast-isel-abort < %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX ; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx -O0 --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX
define double @int_to_double_rr(i32 %a) { define double @int_to_double_rr(i32 %a) {
; ALL-LABEL: int_to_double_rr: ; ALL-LABEL: int_to_double_rr:
; SSE2: cvtsi2sdl %edi, %xmm0 ; SSE2: cvtsi2sdl %edi, %xmm0
; AVX: vcvtsi2sdl %edi, %xmm0, %xmm0 ; AVX: vcvtsi2sdl %edi, %xmm0, %xmm0
; ALL-NEXT: ret ; ALL-NEXT: ret
entry: entry:
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test/CodeGen/X86/fast-isel-ret-ext.ll

; RUN: llc < %s -O0 -fast-isel-abort -mtriple i686-apple-darwin10 | FileCheck %s ; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple i686-apple-darwin10 | FileCheck %s
; RUN: llc < %s -O0 -fast-isel-abort -mtriple x86_64-apple-darwin10 | FileCheck %s ; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple x86_64-apple-darwin10 | FileCheck %s
define zeroext i8 @test1(i32 %y) nounwind { define zeroext i8 @test1(i32 %y) nounwind {
%conv = trunc i32 %y to i8 %conv = trunc i32 %y to i8
ret i8 %conv ret i8 %conv
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: movzbl {{.*}}, %eax ; CHECK: movzbl {{.*}}, %eax
} }
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test/CodeGen/X86/fast-isel-select-cmov.ll

; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10 | FileCheck %s ; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 | FileCheck %s
; Test conditional move for the supported types (i16, i32, and i32) and ; Test conditional move for the supported types (i16, i32, and i32) and
; conditon input (argument or cmp). Currently i8 is not supported. ; conditon input (argument or cmp). Currently i8 is not supported.
define zeroext i16 @select_cmov_i16(i1 zeroext %cond, i16 zeroext %a, i16 zeroext %b) { define zeroext i16 @select_cmov_i16(i1 zeroext %cond, i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: select_cmov_i16 ; CHECK-LABEL: select_cmov_i16
; CHECK: testb $1, %dil ; CHECK: testb $1, %dil
; CHECK-NEXT: cmovew %dx, %si ; CHECK-NEXT: cmovew %dx, %si
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test/CodeGen/X86/fast-isel-select-cmov2.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 | FileCheck %s
; Test all the cmp predicates that can feed an integer conditional move. ; Test all the cmp predicates that can feed an integer conditional move.
define i64 @select_fcmp_false_cmov(double %a, double %b, i64 %c, i64 %d) { define i64 @select_fcmp_false_cmov(double %a, double %b, i64 %c, i64 %d) {
; CHECK-LABEL: select_fcmp_false_cmov ; CHECK-LABEL: select_fcmp_false_cmov
; CHECK: movq %rsi, %rax ; CHECK: movq %rsi, %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%1 = fcmp false double %a, %b %1 = fcmp false double %a, %b
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test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mcpu=corei7-avx | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mcpu=corei7-avx | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort -mcpu=corei7-avx | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 -mcpu=corei7-avx | FileCheck %s
define float @select_fcmp_one_f32(float %a, float %b, float %c, float %d) { define float @select_fcmp_one_f32(float %a, float %b, float %c, float %d) {
; CHECK-LABEL: select_fcmp_one_f32 ; CHECK-LABEL: select_fcmp_one_f32
; CHECK: ucomiss %xmm1, %xmm0 ; CHECK: ucomiss %xmm1, %xmm0
; CHECK-NEXT: jne [[BB:LBB[0-9]+_2]] ; CHECK-NEXT: jne [[BB:LBB[0-9]+_2]]
; CHECK: [[BB]] ; CHECK: [[BB]]
; CHECK-NEXT: movaps %xmm2, %xmm0 ; CHECK-NEXT: movaps %xmm2, %xmm0
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test/CodeGen/X86/fast-isel-select-sse.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mcpu=corei7-avx | FileCheck %s --check-prefix=AVX ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mcpu=corei7-avx | FileCheck %s --check-prefix=AVX
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort -mcpu=corei7-avx | FileCheck %s --check-prefix=AVX ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 -mcpu=corei7-avx | FileCheck %s --check-prefix=AVX
; Test all cmp predicates that can be used with SSE. ; Test all cmp predicates that can be used with SSE.
define float @select_fcmp_oeq_f32(float %a, float %b, float %c, float %d) { define float @select_fcmp_oeq_f32(float %a, float %b, float %c, float %d) {
; CHECK-LABEL: select_fcmp_oeq_f32 ; CHECK-LABEL: select_fcmp_oeq_f32
; CHECK: cmpeqss %xmm1, %xmm0 ; CHECK: cmpeqss %xmm1, %xmm0
; CHECK-NEXT: andps %xmm0, %xmm2 ; CHECK-NEXT: andps %xmm0, %xmm2
; CHECK-NEXT: andnps %xmm3, %xmm0 ; CHECK-NEXT: andnps %xmm3, %xmm0
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test/CodeGen/X86/fast-isel-sse12-fptoint.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=SSE ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx2,+avx -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=AVX ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx2,+avx -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=AVX
define i32 @cvt_test1(float %a) { define i32 @cvt_test1(float %a) {
; SSE-LABEL: cvt_test1 ; SSE-LABEL: cvt_test1
; SSE: cvttss2si %xmm0, %eax ; SSE: cvttss2si %xmm0, %eax
; AVX-LABEL: cvt_test1 ; AVX-LABEL: cvt_test1
; AVX: vcvttss2si %xmm0, %eax ; AVX: vcvttss2si %xmm0, %eax
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 0.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 0.000000e+00, i32 1
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test/CodeGen/X86/fast-isel-store.ll

; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort -mattr=+sse2 < %s | FileCheck %s ; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort=1 -mattr=+sse2 < %s | FileCheck %s
; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort -mattr=+sse2 < %s | FileCheck %s ; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort=1 -mattr=+sse2 < %s | FileCheck %s
define i32 @test_store_32(i32* nocapture %addr, i32 %value) { define i32 @test_store_32(i32* nocapture %addr, i32 %value) {
entry: entry:
store i32 %value, i32* %addr, align 1 store i32 %value, i32* %addr, align 1
ret i32 %value ret i32 %value
} }
; CHECK: ret ; CHECK: ret
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test/CodeGen/X86/fast-isel-x32.ll

; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -fast-isel -fast-isel-abort | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -fast-isel -fast-isel-abort=1 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-nacl -fast-isel -fast-isel-abort | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-nacl -fast-isel -fast-isel-abort=1 | FileCheck %s
; Test that alloca addresses are materialized with the right size instruction. ; Test that alloca addresses are materialized with the right size instruction.
declare void @bar(i32* %arg) declare void @bar(i32* %arg)
; CHECK-LABEL: @foo ; CHECK-LABEL: @foo
define void @foo() { define void @foo() {
%a = alloca i32 %a = alloca i32
; CHECK: leal {{.*}}, %edi ; CHECK: leal {{.*}}, %edi
call void @bar(i32* %a) call void @bar(i32* %a)
ret void ret void
} }

test/CodeGen/X86/fast-isel-x86-64.ll

; RUN: llc < %s -mattr=-avx -fast-isel -mcpu=core2 -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort | FileCheck %s ; RUN: llc < %s -mattr=-avx -fast-isel -mcpu=core2 -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort=1 | FileCheck %s
; RUN: llc < %s -mattr=+avx -fast-isel -mcpu=core2 -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort | FileCheck %s --check-prefix=AVX ; RUN: llc < %s -mattr=+avx -fast-isel -mcpu=core2 -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort=1 | FileCheck %s --check-prefix=AVX
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin10.0.0" target triple = "x86_64-apple-darwin10.0.0"
; Make sure that fast-isel folds the immediate into the binop even though it ; Make sure that fast-isel folds the immediate into the binop even though it
; is non-canonical. ; is non-canonical.
define i32 @test1(i32 %i) nounwind ssp { define i32 @test1(i32 %i) nounwind ssp {
%and = and i32 8, %i %and = and i32 8, %i
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test/CodeGen/X86/fast-isel.ll

; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -march=x86 -mattr=sse2 -no-integrated-as ; RUN: llc < %s -fast-isel -fast-isel-abort=1 -verify-machineinstrs -march=x86 -mattr=sse2 -no-integrated-as
; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=x86_64-apple-darwin10 -no-integrated-as ; RUN: llc < %s -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=x86_64-apple-darwin10 -no-integrated-as
; This tests very minimal fast-isel functionality. ; This tests very minimal fast-isel functionality.
define i32* @foo(i32* %p, i32* %q, i32** %z) nounwind { define i32* @foo(i32* %p, i32* %q, i32** %z) nounwind {
entry: entry:
%r = load i32* %p %r = load i32* %p
%s = load i32* %q %s = load i32* %q
%y = load i32** %z %y = load i32** %z
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test/CodeGen/X86/frameaddr.ll

; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=CHECK-32 ; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=CHECK-32
; RUN: llc < %s -march=x86 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-32 ; RUN: llc < %s -march=x86 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-32
; RUN: llc < %s -mtriple=x86_64-pc-win32 -fast-isel | FileCheck %s --check-prefix=CHECK-W64 ; RUN: llc < %s -mtriple=x86_64-pc-win32 -fast-isel | FileCheck %s --check-prefix=CHECK-W64
; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=CHECK-64 ; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=CHECK-64
; RUN: llc < %s -mtriple=x86_64-unknown -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-64 ; RUN: llc < %s -mtriple=x86_64-unknown -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-64
; RUN: llc < %s -mtriple=x86_64-gnux32 | FileCheck %s --check-prefix=CHECK-X32ABI ; RUN: llc < %s -mtriple=x86_64-gnux32 | FileCheck %s --check-prefix=CHECK-X32ABI
; RUN: llc < %s -mtriple=x86_64-gnux32 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-X32ABI ; RUN: llc < %s -mtriple=x86_64-gnux32 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-X32ABI
; RUN: llc < %s -mtriple=x86_64-nacl | FileCheck %s --check-prefix=CHECK-NACL64 ; RUN: llc < %s -mtriple=x86_64-nacl | FileCheck %s --check-prefix=CHECK-NACL64
; RUN: llc < %s -mtriple=x86_64-nacl -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-NACL64 ; RUN: llc < %s -mtriple=x86_64-nacl -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-NACL64
define i8* @test1() nounwind { define i8* @test1() nounwind {
entry: entry:
; CHECK-32-LABEL: test1 ; CHECK-32-LABEL: test1
; CHECK-32: push ; CHECK-32: push
; CHECK-32-NEXT: movl %esp, %ebp ; CHECK-32-NEXT: movl %esp, %ebp
; CHECK-32-NEXT: movl %ebp, %eax ; CHECK-32-NEXT: movl %ebp, %eax
; CHECK-32-NEXT: pop ; CHECK-32-NEXT: pop
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test/CodeGen/X86/patchpoint-webkit_jscc.ll

; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 < %s | FileCheck %s ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort < %s | FileCheck %s --check-prefix=FAST ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort=1 < %s | FileCheck %s --check-prefix=FAST
; Test the webkit_jscc calling convention. ; Test the webkit_jscc calling convention.
; One argument will be passed in register, the other will be pushed on the stack. ; One argument will be passed in register, the other will be pushed on the stack.
; Return value in $rax. ; Return value in $rax.
define void @jscall_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { define void @jscall_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry: entry:
; CHECK-LABEL: jscall_patchpoint_codegen: ; CHECK-LABEL: jscall_patchpoint_codegen:
; CHECK: Ltmp ; CHECK: Ltmp
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test/CodeGen/X86/patchpoint.ll

; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 < %s | FileCheck %s ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort < %s | FileCheck %s ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort=1 < %s | FileCheck %s
; Trivial patchpoint codegen ; Trivial patchpoint codegen
; ;
define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry: entry:
; CHECK-LABEL: trivial_patchpoint_codegen: ; CHECK-LABEL: trivial_patchpoint_codegen:
; CHECK: movabsq $-559038736, %r11 ; CHECK: movabsq $-559038736, %r11
; CHECK-NEXT: callq *%r11 ; CHECK-NEXT: callq *%r11
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test/CodeGen/X86/sqrt.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 | FileCheck %s --check-prefix=SSE2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 | FileCheck %s --check-prefix=SSE2
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=SSE2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=SSE2
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx2,+avx | FileCheck %s --check-prefix=AVX ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx2,+avx | FileCheck %s --check-prefix=AVX
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx2,+avx -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=AVX ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx2,+avx -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=AVX
define float @test_sqrt_f32(float %a) { define float @test_sqrt_f32(float %a) {
; SSE2-LABEL: test_sqrt_f32 ; SSE2-LABEL: test_sqrt_f32
; SSE2: sqrtss %xmm0, %xmm0 ; SSE2: sqrtss %xmm0, %xmm0
; AVX-LABEL: test_sqrt_f32 ; AVX-LABEL: test_sqrt_f32
; AVX: vsqrtss %xmm0, %xmm0 ; AVX: vsqrtss %xmm0, %xmm0
%res = call float @llvm.sqrt.f32(float %a) %res = call float @llvm.sqrt.f32(float %a)
ret float %res ret float %res
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test/CodeGen/X86/stackmap-fast-isel.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort=1 | FileCheck %s
; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
; CHECK-NEXT: __LLVM_StackMaps: ; CHECK-NEXT: __LLVM_StackMaps:
; Header ; Header
; CHECK-NEXT: .byte 1 ; CHECK-NEXT: .byte 1
; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .byte 0
; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0
; Num Functions ; Num Functions
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test/CodeGen/X86/tailcall-fastisel.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin -tailcallopt -fast-isel -fast-isel-abort | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin -tailcallopt -fast-isel -fast-isel-abort=1 | FileCheck %s
%0 = type { i64, i32, i8* } %0 = type { i64, i32, i8* }
define fastcc i8* @"visit_array_aux<`Reference>"(%0 %arg, i32 %arg1) nounwind { define fastcc i8* @"visit_array_aux<`Reference>"(%0 %arg, i32 %arg1) nounwind {
fail: ; preds = %entry fail: ; preds = %entry
%tmp20 = tail call fastcc i8* @"visit_array_aux<`Reference>"(%0 %arg, i32 undef) ; <i8*> [#uses=1] %tmp20 = tail call fastcc i8* @"visit_array_aux<`Reference>"(%0 %arg, i32 undef) ; <i8*> [#uses=1]
; CHECK: jmp "_visit_array_aux<`Reference>" ## TAILCALL ; CHECK: jmp "_visit_array_aux<`Reference>" ## TAILCALL
ret i8* %tmp20 ret i8* %tmp20
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test/CodeGen/X86/xaluo.ll

; RUN: llc -mtriple=x86_64-darwin-unknown < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG ; RUN: llc -mtriple=x86_64-darwin-unknown < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
; RUN: llc -mtriple=x86_64-darwin-unknown -fast-isel -fast-isel-abort < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST ; RUN: llc -mtriple=x86_64-darwin-unknown -fast-isel -fast-isel-abort=1 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
; ;
; Get the actual value of the overflow bit. ; Get the actual value of the overflow bit.
; ;
; SADDO reg, reg ; SADDO reg, reg
define zeroext i1 @saddo.i8(i8 signext %v1, i8 signext %v2, i8* %res) { define zeroext i1 @saddo.i8(i8 signext %v1, i8 signext %v2, i8* %res) {
entry: entry:
; CHECK-LABEL: saddo.i8 ; CHECK-LABEL: saddo.i8
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test/MC/ARM/data-in-code.ll

;; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort \ ;; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 \
;; RUN: -mtriple=armv7-linux-gnueabi -filetype=obj %s -o - | \ ;; RUN: -mtriple=armv7-linux-gnueabi -filetype=obj %s -o - | \
;; RUN: llvm-readobj -t | FileCheck -check-prefix=ARM %s ;; RUN: llvm-readobj -t | FileCheck -check-prefix=ARM %s
;; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort \ ;; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 \
;; RUN: -mtriple=thumbv7-linux-gnueabi -filetype=obj %s -o - | \ ;; RUN: -mtriple=thumbv7-linux-gnueabi -filetype=obj %s -o - | \
;; RUN: llvm-readobj -t | FileCheck -check-prefix=TMB %s ;; RUN: llvm-readobj -t | FileCheck -check-prefix=TMB %s
;; Ensure that if a jump table is generated that it has Mapping Symbols ;; Ensure that if a jump table is generated that it has Mapping Symbols
;; marking the data-in-code region. ;; marking the data-in-code region.
define void @foo(i32* %ptr) nounwind ssp { define void @foo(i32* %ptr) nounwind ssp {
%tmp = load i32* %ptr, align 4 %tmp = load i32* %ptr, align 4
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