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[AMDGPU] Add 192-bit register classes
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Authored by foad on Apr 16 2020, 10:56 AM.

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foad created this revision.Apr 16 2020, 10:56 AM
arsenm added inline comments.Apr 16 2020, 11:14 AM
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
1371

Should also AReg_192

1546

Trailing comma

foad updated this revision to Diff 258257.Apr 17 2020, 1:46 AM
foad marked an inline comment as done.

Update AMDGPURegisterBanks.td.
Add AReg_192 register class.
Remove trailing comma.

foad marked 2 inline comments as done.
foad updated this revision to Diff 258314.Apr 17 2020, 7:03 AM

Rebase.

arsenm accepted this revision.Apr 17 2020, 7:05 AM
This revision is now accepted and ready to land.Apr 17 2020, 7:05 AM

Same notes about missing places as in D78348.

llvm/lib/Target/AMDGPU/SIRegisterInfo.td
771

This renumbering becomes troublesome. Maybe we need a policy like AllocationPriority = Size/32.

rampitec added inline comments.Apr 17 2020, 12:48 PM
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
760

I wander if we should just use for loop to define all the classes at once.

AMDGPUGenRegisterBankInfo.def probably should be updated as well.

foad updated this revision to Diff 258950.Apr 21 2020, 3:18 AM

Rebase.
Update AMDGPUAsmPrinter, AMDGPUISelDAGToDAG, AMDGPUAsmParser,
SIMCCodeEmitter and SITargetLowering::getRegForInlineAsmConstraint.

foad added a comment.Apr 21 2020, 3:20 AM

AMDGPUGenRegisterBankInfo.def probably should be updated as well.

Probably, but it is already missing 160-bit classes. Can we leave it for a separate patch?

AMDGPUGenRegisterBankInfo.def probably should be updated as well.

Probably, but it is already missing 160-bit classes. Can we leave it for a separate patch?

Sounds good.

This revision was automatically updated to reflect the committed changes.
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir