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Differential D75510

[X86][llvm-exegesis] Exploring vector insert/extract
AbandonedPublic

Authored by lebedev.ri on Mar 3 2020, 2:26 AM.

Details

Reviewers
gchatelet
courbet
RKSimon
Summary

This is proof-of-concept, i'm not sure if we want this
so i didn't spend much time on this. If we do i can improve this.

It's not very useful without something like D60000,
but even now i'm seeing somewhat confusing results:

---
mode:            latency
key:
  instructions:
    - 'PEXTRDrr R9D XMM6 i_0x0'
    - 'MOV64toPQIrr XMM6 R9'
  config:          ''
  register_initial_values:
    - 'XMM6=0x0'
    - 'R9=0x0'
cpu_name:        bdver2
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:
  - { key: latency, value: 10.0292, per_snippet_value: 20.0584 }
error:           ''
info:            Repeating two instructions
assembled_snippet: 4883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F34244883C41049B9000000000000000066410F3A16F10066490F6EF166410F3A16F10066490F6EF166410F3A16F10066490F6EF166410F3A16F10066490F6EF166410F3A16F10066490F6EF166410F3A16F10066490F6EF166410F3A16F10066490F6EF166410F3A16F10066490F6EF1C3
...
---
mode:            latency
key:
  instructions:
    - 'PEXTRDrr EBP XMM8 i_0x0'
    - 'VMOV64toPQIrr XMM8 RBP'
  config:          ''
  register_initial_values:
    - 'XMM8=0x0'
    - 'RBP=0x0'
cpu_name:        bdver2
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:
  - { key: latency, value: 10.0344, per_snippet_value: 20.0688 }
error:           ''
info:            Repeating two instructions
assembled_snippet: 554883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C57A6F04244883C41048BD000000000000000066440F3A16C500C461F96EC566440F3A16C500C461F96EC566440F3A16C500C461F96EC566440F3A16C500C461F96EC566440F3A16C500C461F96EC566440F3A16C500C461F96EC566440F3A16C500C461F96EC566440F3A16C500C461F96EC55DC3
...
---
mode:            latency
key:
  instructions:
    - 'EXTRACTPSrr EDI XMM2 i_0x0'
    - 'VPINSRWrr XMM2 XMM7 EDI i_0x1'
  config:          ''
  register_initial_values:
    - 'XMM2=0x0'
    - 'XMM7=0x0'
cpu_name:        bdver2
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:
  - { key: latency, value: 11.0299, per_snippet_value: 22.0598 }
error:           ''
info:            Repeating two instructions
assembled_snippet: 4883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F14244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F3C244883C410660F3A17D700C5C1C4D701660F3A17D700C5C1C4D701660F3A17D700C5C1C4D701660F3A17D700C5C1C4D701660F3A17D700C5C1C4D701660F3A17D700C5C1C4D701660F3A17D700C5C1C4D701660F3A17D700C5C1C4D701C3
...
---
mode:            latency
key:
  instructions:
    - 'EXTRACTPSrr ESI XMM6 i_0x0'
    - 'PINSRDrr XMM6 XMM6 ESI i_0x1'
  config:          ''
  register_initial_values:
    - 'XMM6=0x0'
cpu_name:        bdver2
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:
  - { key: latency, value: 11.0328, per_snippet_value: 22.0656 }
error:           ''
info:            Repeating two instructions
assembled_snippet: 4883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F34244883C410660F3A17F600660F3A22F601660F3A17F600660F3A22F601660F3A17F600660F3A22F601660F3A17F600660F3A22F601660F3A17F600660F3A22F601660F3A17F600660F3A22F601660F3A17F600660F3A22F601660F3A17F600660F3A22F601C3
...

So extraction from 0'th lane isn't actually any faster?

Diff Detail

Event Timeline

lebedev.ri created this revision.Mar 3 2020, 2:26 AM
Herald added subscribers: mstojanovic, tschuett. · View Herald TranscriptMar 3 2020, 2:26 AM
Harbormaster completed remote builds in B47886: Diff 247831.Mar 3 2020, 3:04 AM
RKSimon added inline comments.Mar 3 2020, 10:18 AM
llvm/tools/llvm-exegesis/lib/X86/Target.cpp
789

The VPINSR*Z* variants still work on 128-bit vectors, they just use EVEX encoding (supporting predicate masks etc.)

lebedev.ri updated this revision to Diff 247980.Mar 3 2020, 11:37 AM
lebedev.ri marked 2 inline comments as done.

Addressed review note - only AVX512 instructions work on 256-bit subvectors.
Also, tentatively add AVX512 instructions.

llvm/tools/llvm-exegesis/lib/X86/Target.cpp
789

Hm, and same for VINSERTPSZ, as far as i can tell.
Must be copypaste gone wrong.

Harbormaster completed remote builds in B47948: Diff 247980.Mar 3 2020, 12:37 PM
lebedev.ri abandoned this revision.Aug 12 2020, 2:23 PM

Revision Contents

PathSize
llvm/
tools/
llvm-exegesis/
lib/
X86/
250 lines

Diff 247980

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

Show First 20 Lines • Show All 756 Lines • ▼ Show 20 Linesstd::vector<InstructionTemplate> ExegesisX86Target::generateInstructionVariants(
SmallVector<SmallVector<MCOperand, 1>, 4> VariableChoices; SmallVector<SmallVector<MCOperand, 1>, 4> VariableChoices;
VariableChoices.resize(Instr.Variables.size()); VariableChoices.resize(Instr.Variables.size());
for (auto I : llvm::zip(Instr.Variables, VariableChoices)) { for (auto I : llvm::zip(Instr.Variables, VariableChoices)) {
const Variable &Var = std::get<0>(I); const Variable &Var = std::get<0>(I);
SmallVectorImpl<MCOperand> &Choices = std::get<1>(I); SmallVectorImpl<MCOperand> &Choices = std::get<1>(I);
switch (Instr.getPrimaryOperand(Var).getExplicitOperandInfo().OperandType) { switch (Instr.getPrimaryOperand(Var).getExplicitOperandInfo().OperandType) {
default: default:
// We don't wish to explicitly explore this variable. break;
Choices.emplace_back(); // But add invalid MCOperand to simplify logic. case MCOI::OperandType::OPERAND_IMMEDIATE: {
continue; int NumElts = 0;
switch (Instr.Description.getOpcode()) {
default:
break;
// Extract Byte from XMM
case X86::PEXTRBmr:
case X86::PEXTRBrr:
case X86::VPEXTRBZmr:
case X86::VPEXTRBZrr:
case X86::VPEXTRBmr:
case X86::VPEXTRBrr:
// Insert Byte into XMM
case X86::PINSRBrm:
case X86::PINSRBrr:
case X86::VPINSRBZrm:
case X86::VPINSRBZrr:
case X86::VPINSRBrm:
case X86::VPINSRBrr:
NumElts = 128 / 8;
break;
// Extract Word from XMM
case X86::PEXTRWmr:
RKSimonUnsubmitted
Done
ReplyInline Actions

The VPINSR*Z* variants still work on 128-bit vectors, they just use EVEX encoding (supporting predicate masks etc.)

RKSimon: The VPINSR*Z* variants still work on 128-bit vectors, they just use EVEX encoding (supporting…
lebedev.riAuthorUnsubmitted
Done
ReplyInline Actions

Hm, and same for VINSERTPSZ, as far as i can tell.
Must be copypaste gone wrong.

lebedev.ri: Hm, and same for `VINSERTPSZ`, as far as i can tell. Must be copypaste gone wrong.
case X86::PEXTRWrr:
case X86::VPEXTRWZmr:
case X86::VPEXTRWZrr:
case X86::VPEXTRWmr:
case X86::VPEXTRWrr:
// Insert Word into XMM
case X86::PINSRWrm:
case X86::PINSRWrr:
case X86::VPINSRWZrm:
case X86::VPINSRWZrr:
case X86::VPINSRWrm:
case X86::VPINSRWrr:
NumElts = 128 / 16;
break;
// Extract Double-Word from XMM
case X86::PEXTRDmr:
case X86::PEXTRDrr:
case X86::VPEXTRDZmr:
case X86::VPEXTRDZrr:
case X86::VPEXTRDmr:
case X86::VPEXTRDrr:
// Insert Double-Word into XMM
case X86::PINSRDrm:
case X86::PINSRDrr:
case X86::VPINSRDZrm:
case X86::VPINSRDZrr:
case X86::VPINSRDrm:
case X86::VPINSRDrr:
NumElts = 128 / 32;
break;
// Extract Quad-Word from XMM
case X86::PEXTRQmr:
case X86::PEXTRQrr:
case X86::VPEXTRQZmr:
case X86::VPEXTRQZrr:
case X86::VPEXTRQmr:
case X86::VPEXTRQrr:
// Insert Quad-Word into XMM
case X86::PINSRQrm:
case X86::PINSRQrr:
case X86::VPINSRQZrm:
case X86::VPINSRQZrr:
case X86::VPINSRQrm:
case X86::VPINSRQrr:
NumElts = 128 / 64;
break;
// Extract Scalar Single-Precision Floating-Point Value from XMM
case X86::EXTRACTPSmr:
case X86::EXTRACTPSrr:
case X86::VEXTRACTPSZmr:
case X86::VEXTRACTPSZrr:
case X86::VEXTRACTPSmr:
case X86::VEXTRACTPSrr:
// Insert Scalar Single-Precision Floating-Point Value into XMM
case X86::INSERTPSrm:
case X86::INSERTPSrr:
case X86::VINSERTPSZrm:
case X86::VINSERTPSZrr:
case X86::VINSERTPSrm:
case X86::VINSERTPSrr:
NumElts = 128 / 32;
break;
// Extract XMM from YMM
case X86::VEXTRACTF128mr:
case X86::VEXTRACTF128rr:
case X86::VEXTRACTF32x4Z256mr:
case X86::VEXTRACTF32x4Z256mrk:
case X86::VEXTRACTF32x4Z256rr:
case X86::VEXTRACTF32x4Z256rrk:
case X86::VEXTRACTF32x4Z256rrkz:
case X86::VEXTRACTF64x2Z256mr:
case X86::VEXTRACTF64x2Z256mrk:
case X86::VEXTRACTF64x2Z256rr:
case X86::VEXTRACTF64x2Z256rrk:
case X86::VEXTRACTF64x2Z256rrkz:
case X86::VEXTRACTI128mr:
case X86::VEXTRACTI128rr:
case X86::VEXTRACTI32x4Z256mr:
case X86::VEXTRACTI32x4Z256mrk:
case X86::VEXTRACTI32x4Z256rr:
case X86::VEXTRACTI32x4Z256rrk:
case X86::VEXTRACTI32x4Z256rrkz:
case X86::VEXTRACTI64x2Z256mr:
case X86::VEXTRACTI64x2Z256mrk:
case X86::VEXTRACTI64x2Z256rr:
case X86::VEXTRACTI64x2Z256rrk:
case X86::VEXTRACTI64x2Z256rrkz:
// Insert XMM into YMM
case X86::VINSERTF128rm:
case X86::VINSERTF128rr:
case X86::VINSERTF32x4Z256rm:
case X86::VINSERTF32x4Z256rmk:
case X86::VINSERTF32x4Z256rr:
case X86::VINSERTF32x4Z256rrk:
case X86::VINSERTF32x4Z256rrkz:
case X86::VINSERTF64x2Z256rm:
case X86::VINSERTF64x2Z256rmk:
case X86::VINSERTF64x2Z256rr:
case X86::VINSERTF64x2Z256rrk:
case X86::VINSERTF64x2Z256rrkz:
case X86::VINSERTI128rm:
case X86::VINSERTI128rr:
case X86::VINSERTI32x4Z256rm:
case X86::VINSERTI32x4Z256rmk:
case X86::VINSERTI32x4Z256rr:
case X86::VINSERTI32x4Z256rrk:
case X86::VINSERTI32x4Z256rrkz:
case X86::VINSERTI64x2Z256rm:
case X86::VINSERTI64x2Z256rmk:
case X86::VINSERTI64x2Z256rr:
case X86::VINSERTI64x2Z256rrk:
case X86::VINSERTI64x2Z256rrkz:
NumElts = 256 / 128;
break;
// Extract XMM from ZMM
case X86::VEXTRACTF32x4Zmr:
case X86::VEXTRACTF32x4Zmrk:
case X86::VEXTRACTF32x4Zrr:
case X86::VEXTRACTF32x4Zrrk:
case X86::VEXTRACTF32x4Zrrkz:
case X86::VEXTRACTF64x2Zmr:
case X86::VEXTRACTF64x2Zmrk:
case X86::VEXTRACTF64x2Zrr:
case X86::VEXTRACTF64x2Zrrk:
case X86::VEXTRACTF64x2Zrrkz:
case X86::VEXTRACTI32x4Zmr:
case X86::VEXTRACTI32x4Zmrk:
case X86::VEXTRACTI32x4Zrr:
case X86::VEXTRACTI32x4Zrrk:
case X86::VEXTRACTI32x4Zrrkz:
case X86::VEXTRACTI64x2Zmr:
case X86::VEXTRACTI64x2Zmrk:
case X86::VEXTRACTI64x2Zrr:
case X86::VEXTRACTI64x2Zrrk:
case X86::VEXTRACTI64x2Zrrkz:
// Insert XMM into ZMM
case X86::VINSERTF32x4Zrm:
case X86::VINSERTF32x4Zrmk:
case X86::VINSERTF32x4Zrr:
case X86::VINSERTF32x4Zrrk:
case X86::VINSERTF32x4Zrrkz:
case X86::VINSERTF64x2Zrm:
case X86::VINSERTF64x2Zrmk:
case X86::VINSERTF64x2Zrr:
case X86::VINSERTF64x2Zrrk:
case X86::VINSERTF64x2Zrrkz:
case X86::VINSERTI32x4Zrm:
case X86::VINSERTI32x4Zrmk:
case X86::VINSERTI32x4Zrr:
case X86::VINSERTI32x4Zrrk:
case X86::VINSERTI32x4Zrrkz:
case X86::VINSERTI64x2Zrm:
case X86::VINSERTI64x2Zrmk:
case X86::VINSERTI64x2Zrr:
case X86::VINSERTI64x2Zrrk:
case X86::VINSERTI64x2Zrrkz:
NumElts = 512 / 128;
break;
// Extract YMM from ZMM
case X86::VEXTRACTF32x8Zmr:
case X86::VEXTRACTF32x8Zmrk:
case X86::VEXTRACTF32x8Zrr:
case X86::VEXTRACTF32x8Zrrk:
case X86::VEXTRACTF32x8Zrrkz:
case X86::VEXTRACTF64x4Zmr:
case X86::VEXTRACTF64x4Zmrk:
case X86::VEXTRACTF64x4Zrr:
case X86::VEXTRACTF64x4Zrrk:
case X86::VEXTRACTF64x4Zrrkz:
case X86::VEXTRACTI32x8Zmr:
case X86::VEXTRACTI32x8Zmrk:
case X86::VEXTRACTI32x8Zrr:
case X86::VEXTRACTI32x8Zrrk:
case X86::VEXTRACTI32x8Zrrkz:
case X86::VEXTRACTI64x4Zmr:
case X86::VEXTRACTI64x4Zmrk:
case X86::VEXTRACTI64x4Zrr:
case X86::VEXTRACTI64x4Zrrk:
case X86::VEXTRACTI64x4Zrrkz:
// Insert YMM into ZMM
case X86::VINSERTF32x8Zrm:
case X86::VINSERTF32x8Zrr:
case X86::VINSERTF32x8Zrmk:
case X86::VINSERTF32x8Zrrk:
case X86::VINSERTF32x8Zrrkz:
case X86::VINSERTF64x4Zrm:
case X86::VINSERTF64x4Zrr:
case X86::VINSERTF64x4Zrmk:
case X86::VINSERTF64x4Zrrk:
case X86::VINSERTF64x4Zrrkz:
case X86::VINSERTI32x8Zrm:
case X86::VINSERTI32x8Zrr:
case X86::VINSERTI32x8Zrmk:
case X86::VINSERTI32x8Zrrk:
case X86::VINSERTI32x8Zrrkz:
case X86::VINSERTI64x4Zrm:
case X86::VINSERTI64x4Zrr:
case X86::VINSERTI64x4Zrmk:
case X86::VINSERTI64x4Zrrk:
case X86::VINSERTI64x4Zrrkz:
NumElts = 512 / 256;
break;
}
auto Indexes = seq(0, NumElts);
Choices.reserve(std::distance(Indexes.begin(), Indexes.end()));
for (int CondCode : Indexes)
Choices.emplace_back(MCOperand::createImm(CondCode));
break;
}
case X86::OperandType::OPERAND_COND_CODE: { case X86::OperandType::OPERAND_COND_CODE: {
Exploration = true;
auto CondCodes = seq((int)X86::CondCode::COND_O, auto CondCodes = seq((int)X86::CondCode::COND_O,
1 + (int)X86::CondCode::LAST_VALID_COND); 1 + (int)X86::CondCode::LAST_VALID_COND);
Choices.reserve(std::distance(CondCodes.begin(), CondCodes.end())); Choices.reserve(std::distance(CondCodes.begin(), CondCodes.end()));
for (int CondCode : CondCodes) for (int CondCode : CondCodes)
Choices.emplace_back(MCOperand::createImm(CondCode)); Choices.emplace_back(MCOperand::createImm(CondCode));
break; break;
} }
} }
// We don't wish to explicitly explore this variable.
if (Choices.empty())
Choices.emplace_back(); // But add invalid MCOperand to simplify logic.
else
Exploration = true;
} }
// If we don't wish to explore any variables, defer to the baseline method. // If we don't wish to explore any variables, defer to the baseline method.
if (!Exploration) if (!Exploration)
return ExegesisTarget::generateInstructionVariants(Instr, return ExegesisTarget::generateInstructionVariants(Instr,
MaxConfigsPerOpcode); MaxConfigsPerOpcode);
std::vector<InstructionTemplate> Variants; std::vector<InstructionTemplate> Variants;
Show All 32 Lines