[SVE][AArch64] Adding pattern matching for some SVE instructions.

[mgudim]

Summary

This is a follow-up with https://reviews.llvm.org/D68098.

We added straight-forward patten matching for two SVE intrinsics: frecps and frsqrts. We also added patterns for fsub and fmul - these SDNodes directly correspond to machine instructions.

[mgudim]

llvm/include/llvm/IR/IntrinsicsAArch64.td

805

I will fix this before committing or in the next revision.

[amehsan]

This looks straighforward. So LGTM. Since this is @mgudim's first patch, I will commit it for him. But I will wait a bit more (before committing) just in case @huntergr has any comments.

[huntergr]

Hi, thanks for waiting a bit. LGTM.

[amehsan]

In D68476#1717715, @huntergr wrote:

Hi, thanks for waiting a bit. LGTM.

Thanks @huntergr and Sorry for my delay. I will merge this very soon and get to the other patches. Thanks again.

[huntergr]

llvm/include/llvm/IR/IntrinsicsAArch64.td

856

One minor change I'd like to request is to do with the naming convention we have for these...

int_aarch64_sve_frecps_x and int_aarch64_sve_frsqrts_x would be the preferred names. Adding f to the start will match the instruction name, and the _x suffix is to indicate an unpredicated intrinsic.

[mgudim]

Renamed the inrinsics according to the convention.

[huntergr]

In D68476#1725466, @mgudim wrote:

Renamed the inrinsics according to the convention.

Thanks :)

[amehsan]

Committed in https://reviews.llvm.org/rG1e9de0215f04