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huntergr (Graham Hunter)
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User Since
Sep 5 2014, 5:55 AM (316 w, 5 d)

Recent Activity

Mar 4 2020

huntergr added a comment to D75594: [AArch64] Add support for Fujitsu A64FX.

Looks good, I agree with @dmgreen that a clang driver test would be nice.

Mar 4 2020, 7:19 AM · Restricted Project, Restricted Project

Mar 2 2020

huntergr committed rGad497658d25a: [OpenMP] Allow const parameters in declare simd linear clause (authored by huntergr).
[OpenMP] Allow const parameters in declare simd linear clause
Mar 2 2020, 6:57 AM
huntergr closed D75350: [OpenMP] Allow const parameters in declare simd linear clause.
Mar 2 2020, 6:57 AM · Restricted Project
huntergr updated the diff for D75350: [OpenMP] Allow const parameters in declare simd linear clause.
  • Removed the ) my editor helpfully added to the CHECK line
  • Added a test to declare_simd_aarch64.c
Mar 2 2020, 6:16 AM · Restricted Project

Feb 28 2020

huntergr updated the diff for D75350: [OpenMP] Allow const parameters in declare simd linear clause.
  • Added a function body to the test so that it would generate symbols
  • Added check lines to ensure the mangled name is present
  • Reformatted the params of Sema::CheckOpenMPLinearDecl to comply with coding style.
Feb 28 2020, 9:37 AM · Restricted Project
huntergr added inline comments to D75350: [OpenMP] Allow const parameters in declare simd linear clause.
Feb 28 2020, 7:17 AM · Restricted Project
huntergr created D75350: [OpenMP] Allow const parameters in declare simd linear clause.
Feb 28 2020, 6:39 AM · Restricted Project

Jan 23 2020

huntergr abandoned D47779: [AArch64][SVE] Implement copying for Z registers.

Superseded by D66302

Jan 23 2020, 6:57 AM
huntergr abandoned D47771: [AArch64][SVE] Scalable arguments and returns passed in Z regs.

Superseded by D65448

Jan 23 2020, 6:48 AM
huntergr abandoned D47773: [AArch64][SVE] Add VScale Intrinsic.

Superseded by D68203

Jan 23 2020, 6:48 AM

Nov 26 2019

huntergr added inline comments to D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics..
Nov 26 2019, 3:39 AM · Restricted Project

Nov 18 2019

huntergr committed rG3f08ad611aa2: [SVE][CodeGen] Scalable vector MVT size queries (authored by huntergr).
[SVE][CodeGen] Scalable vector MVT size queries
Nov 18 2019, 4:35 AM
huntergr closed D66871: [SVE] MVT scalable size queries.
Nov 18 2019, 4:35 AM · Restricted Project

Nov 14 2019

huntergr updated the diff for D66871: [SVE] MVT scalable size queries.
  • Removed const qualifier from queries
  • Swapped to std::make_tuple for the comparisons in CodeGenDAGPatterns.cpp
Nov 14 2019, 5:20 AM · Restricted Project

Nov 13 2019

huntergr added inline comments to D66871: [SVE] MVT scalable size queries.
Nov 13 2019, 5:02 AM · Restricted Project

Nov 12 2019

huntergr added inline comments to D66871: [SVE] MVT scalable size queries.
Nov 12 2019, 4:04 AM · Restricted Project
huntergr added a comment to D66871: [SVE] MVT scalable size queries.

I also changed the SelectionDAGBuilder code for masked loads/stores/gathers/scatters to use the known min size when creating a MachineMemoryOperand, since MMO isn't aware of scalable types yet. I've left TODOs as reminders.

Nov 12 2019, 4:04 AM · Restricted Project
huntergr updated the diff for D66871: [SVE] MVT scalable size queries.
  • Switched the lambdas in CodeGenDAGPatterns to use std::tie for ordering. This needed the TypeSize objects to be constant (I get a "non-const lvalue reference" error otherwise), so I changed all query methods to return const objects.
  • Changed stack offset to deliberately use a TypeSize. This hit another problem with implicit promotion and signed v. unsigned casting, so I've added explicit casts.
Nov 12 2019, 3:41 AM · Restricted Project

Nov 5 2019

huntergr added inline comments to D66871: [SVE] MVT scalable size queries.
Nov 5 2019, 9:42 AM · Restricted Project

Oct 30 2019

huntergr added a comment to D68476: [SVE][AArch64] Adding pattern matching for some SVE instructions..

Renamed the inrinsics according to the convention.

Oct 30 2019, 3:27 AM · Restricted Project
huntergr added inline comments to D69128: [AArch64][SVE] Add patterns for some integer vector instructions.
Oct 30 2019, 3:17 AM · Restricted Project

Oct 29 2019

huntergr added inline comments to D69128: [AArch64][SVE] Add patterns for some integer vector instructions.
Oct 29 2019, 5:01 AM · Restricted Project
huntergr added inline comments to D68476: [SVE][AArch64] Adding pattern matching for some SVE instructions..
Oct 29 2019, 3:37 AM · Restricted Project

Oct 25 2019

huntergr updated the diff for D66871: [SVE] MVT scalable size queries.
  • Refactored to match the same approach used in D53137 -- TypeSize returned for all size queries instead of introducing separate interfaces and relying on implicit conversion to be (mostly) compatible with existing code.
  • Added 'isByteSized()' interface to TypeSize.
  • Minor bugfix to DAGCombiner::ForwardStoreValueToDirectLoad, where implicit conversions allowed an unsigned number to wrap and then be converted to a larger signed integer; with TypeSize using uint64_t instead, this showed up during a make check-all run with ubsan active. Can't write a test for that one since the transform bailed out when Offset was non-zero.
Oct 25 2019, 4:55 AM · Restricted Project

Oct 23 2019

huntergr added a comment to D68877: [AArch64][SVE] Implement masked load intrinsics.

I was also expecting something that says "setOperationAction(ISD::MLOAD, VT, Legal)" somewhere, but I guess that's already the default?

Oct 23 2019, 6:26 AM · Restricted Project

Oct 22 2019

huntergr accepted D68476: [SVE][AArch64] Adding pattern matching for some SVE instructions..

Hi, thanks for waiting a bit. LGTM.

Oct 22 2019, 2:30 AM · Restricted Project

Oct 18 2019

huntergr committed rG84da2596f96d: [AArch64][SVE] Add SPLAT_VECTOR ISD Node (authored by huntergr).
[AArch64][SVE] Add SPLAT_VECTOR ISD Node
Oct 18 2019, 4:48 AM
huntergr closed D47775: [AArch64][SVE] Add SPLAT_VECTOR ISD Node.
Oct 18 2019, 4:47 AM · Restricted Project
huntergr committed rL375222: [AArch64][SVE] Add SPLAT_VECTOR ISD Node.
[AArch64][SVE] Add SPLAT_VECTOR ISD Node
Oct 18 2019, 4:47 AM
huntergr committed rL375216: Request commit access for huntergr.
Request commit access for huntergr
Oct 18 2019, 3:27 AM

Oct 17 2019

huntergr updated the diff for D47775: [AArch64][SVE] Add SPLAT_VECTOR ISD Node.
  • Fixed legalization action code, which was trying to use widening for all integer scalable vector types after the new MVT ranges were added
  • Added unit tests for legalizing the result via promotion
  • Minor cleanups, additional comments as requested
Oct 17 2019, 6:21 AM · Restricted Project

Oct 16 2019

huntergr committed rGf998fa2924c7: [SVE][IR] Small TypeSize improvements left out of initial commit (authored by huntergr).
[SVE][IR] Small TypeSize improvements left out of initial commit
Oct 16 2019, 9:32 AM
huntergr committed rL375013: [SVE][IR] Small TypeSize improvements left out of initial commit.
[SVE][IR] Small TypeSize improvements left out of initial commit
Oct 16 2019, 9:32 AM
huntergr added a comment to D47775: [AArch64][SVE] Add SPLAT_VECTOR ISD Node.

Ping.

Oct 16 2019, 6:41 AM · Restricted Project

Oct 8 2019

huntergr added a comment to D53137: Scalable vector core instruction support + size queries.

Hmm, forgot to add the last round of minor fixes before committing. Sorry about that, will push them as well.

Oct 8 2019, 7:01 AM · Restricted Project, Restricted Project
huntergr committed rGb302561b763a: [SVE][IR] Scalable Vector size queries and IR instruction support (authored by huntergr).
[SVE][IR] Scalable Vector size queries and IR instruction support
Oct 8 2019, 5:56 AM
huntergr committed rL374042: [SVE][IR] Scalable Vector size queries and IR instruction support.
[SVE][IR] Scalable Vector size queries and IR instruction support
Oct 8 2019, 5:56 AM
huntergr closed D53137: Scalable vector core instruction support + size queries.
Oct 8 2019, 5:56 AM · Restricted Project, Restricted Project

Oct 3 2019

huntergr updated the diff for D47775: [AArch64][SVE] Add SPLAT_VECTOR ISD Node.
  • Added DAG combine to canonicalize a build_vector splat into a splat_vector if the target supports the splat_vector operation (by overriding the default Expand legalization action)
Oct 3 2019, 6:55 AM · Restricted Project
huntergr updated subscribers of D47775: [AArch64][SVE] Add SPLAT_VECTOR ISD Node.

Hi James,

Oct 3 2019, 6:52 AM · Restricted Project

Oct 2 2019

huntergr added inline comments to D47775: [AArch64][SVE] Add SPLAT_VECTOR ISD Node.
Oct 2 2019, 2:39 AM · Restricted Project

Oct 1 2019

huntergr updated the diff for D53137: Scalable vector core instruction support + size queries.
  • Renamed ScalableSize to TypeSize, including header name.
  • added alignTo function that takes and returns a TypeSize. I wasn't sure if this should be added to MathExtras.h where the other variants live, so just kept it in TypeSize.h for now
Oct 1 2019, 5:16 AM · Restricted Project, Restricted Project
huntergr added inline comments to D53137: Scalable vector core instruction support + size queries.
Oct 1 2019, 5:14 AM · Restricted Project, Restricted Project

Sep 30 2019

huntergr updated subscribers of D47775: [AArch64][SVE] Add SPLAT_VECTOR ISD Node.
Sep 30 2019, 8:08 AM · Restricted Project
huntergr added inline comments to D47775: [AArch64][SVE] Add SPLAT_VECTOR ISD Node.
Sep 30 2019, 5:28 AM · Restricted Project
huntergr updated the diff for D47775: [AArch64][SVE] Add SPLAT_VECTOR ISD Node.
Sep 30 2019, 4:06 AM · Restricted Project
huntergr accepted D68098: [AArch64][SVE] Adding patterns for floating point SVE add instructions..

You can add the extra multiclass for ftsmul if you wish, but it's not needed until someone implements a matching pattern for that instruction. We only match it against an ACLE intrinsic downstream, not common SDag nodes.

Sep 30 2019, 2:52 AM · Restricted Project

Sep 27 2019

huntergr added a comment to D68098: [AArch64][SVE] Adding patterns for floating point SVE add instructions..

Thanks for taking an interest in SVE codegen. The tests look fine, but we had a different approach in mind for generating many of the patterns. In this case instead of making separate def : Pat< lines for each type, we add an SDPatternOperator and pattern to the multiclass for that instruction type.

Sep 27 2019, 4:53 AM · Restricted Project

Sep 23 2019

huntergr updated the diff for D53137: Scalable vector core instruction support + size queries.
  • Changed existing interface to return ScalableSize objects and added a (mostly) transparent conversion, as per Sander's suggestion.
  • Removed new interfaces for DataLayout and Type.
  • Fixed cases where the transparent conversion doesn't quite work (e.g. std::max/min, where the types must be the same)
Sep 23 2019, 4:25 AM · Restricted Project, Restricted Project

Sep 17 2019

huntergr committed rG1a9195d817d3: [SVE][MVT] Fixed-length vector MVT ranges (authored by huntergr).
[SVE][MVT] Fixed-length vector MVT ranges
Sep 17 2019, 3:20 AM
huntergr committed rL372099: [SVE][MVT] Fixed-length vector MVT ranges.
[SVE][MVT] Fixed-length vector MVT ranges
Sep 17 2019, 3:18 AM
huntergr closed D66339: [SVE] Fixed-length vector MVT ranges.
Sep 17 2019, 3:17 AM · Restricted Project

Aug 29 2019

huntergr added a comment to D66871: [SVE] MVT scalable size queries.

LGTM

Aug 29 2019, 6:34 AM · Restricted Project
huntergr added a comment to D53137: Scalable vector core instruction support + size queries.

Does anyone like Sander's suggestion to make ScalableSize (or whatever we end up naming it) the return value for all size queries and provide an overloaded cast operator to transparently work with existing code comparing against unsigned values? Or is it preferable to keep the current split?

Aug 29 2019, 5:52 AM · Restricted Project, Restricted Project

Aug 28 2019

huntergr created D66871: [SVE] MVT scalable size queries.
Aug 28 2019, 4:16 AM · Restricted Project

Aug 27 2019

huntergr updated the diff for D53137: Scalable vector core instruction support + size queries.
  • Split out backend code into separate patches
  • Renamed 'Min' to 'KnownMin' in method names.
  • Added a few more comments.
Aug 27 2019, 3:42 AM · Restricted Project, Restricted Project

Aug 21 2019

huntergr updated the diff for D66339: [SVE] Fixed-length vector MVT ranges.
  • Reordered MVTs to group fixed-length types together (and the same for scalable).
  • Replaced existing range accessors to remove explicit isScalableVector checks on MVTs in various backends.
Aug 21 2019, 9:02 AM · Restricted Project

Aug 16 2019

huntergr added a comment to D66339: [SVE] Fixed-length vector MVT ranges.

Split out from D53137.

Aug 16 2019, 4:14 AM · Restricted Project
huntergr added a comment to D53137: Scalable vector core instruction support + size queries.

Created D66339 to split out the code to skip scalable vector types in other backends.

Aug 16 2019, 4:14 AM · Restricted Project, Restricted Project
huntergr created D66339: [SVE] Fixed-length vector MVT ranges.
Aug 16 2019, 4:04 AM · Restricted Project

Aug 9 2019

huntergr added a comment to D53137: Scalable vector core instruction support + size queries.

Thanks @huntergr for working on this!

This patch can probably be split into two separate patches, which make them easier to review;

  • One that fixes the Targets to ignore scalable types (see comment)
  • Another one that adds the interface for scalable size queries.
Aug 9 2019, 3:34 AM · Restricted Project, Restricted Project
huntergr added inline comments to D53137: Scalable vector core instruction support + size queries.
Aug 9 2019, 3:16 AM · Restricted Project, Restricted Project

Aug 6 2019

huntergr updated the diff for D53137: Scalable vector core instruction support + size queries.
  • Added comments explaining the new methods
  • Added tests for the MVT/EVT/DataLayout interfaces
  • Refactored ScalableSize class operators to build on '==' and '<'
  • Added checks in various backends that don't support scalable vectors to prevent legalizing operations involving scalable MVTs
Aug 6 2019, 5:55 AM · Restricted Project, Restricted Project

Aug 5 2019

huntergr committed rG208d63ea9018: [MVT][SVE] Map between scalable vector IR Type and VTs (authored by huntergr).
[MVT][SVE] Map between scalable vector IR Type and VTs
Aug 5 2019, 4:19 AM
huntergr committed rL367832: [MVT][SVE] Map between scalable vector IR Type and VTs.
[MVT][SVE] Map between scalable vector IR Type and VTs
Aug 5 2019, 4:18 AM
huntergr closed D47770: [MVT][SVE] Add EVT strings and Type mapping.
Aug 5 2019, 4:18 AM · Restricted Project

Aug 2 2019

huntergr updated the diff for D47770: [MVT][SVE] Add EVT strings and Type mapping.
  • Added inline comments to clarify boolean parameter meaning.
Aug 2 2019, 3:29 AM · Restricted Project

Aug 1 2019

huntergr added a comment to D53137: Scalable vector core instruction support + size queries.

Thanks for the reviews; I left a couple of inline comments, and will make the requested changes.

Aug 1 2019, 6:22 AM · Restricted Project, Restricted Project
huntergr added a reviewer for D47770: [MVT][SVE] Add EVT strings and Type mapping: rovka.
Aug 1 2019, 5:09 AM · Restricted Project
huntergr updated the diff for D47770: [MVT][SVE] Add EVT strings and Type mapping.
  • Updated to head
  • Removed MVT-specific ElementCount in favour of using the common struct
  • Added unit tests.
Aug 1 2019, 4:44 AM · Restricted Project

Jul 31 2019

huntergr updated the diff for D53137: Scalable vector core instruction support + size queries.
  • Removed most of the changes in favour of reintroducing them in separate patches later with appropriate tests.
  • Added tests for core IR instructions to make sure they don't drop the scalable flag.
  • Fixed up a couple places which broke the new tests.
Jul 31 2019, 4:04 AM · Restricted Project, Restricted Project

Jul 23 2019

huntergr added a comment to D53137: Scalable vector core instruction support + size queries.

Hi Diana,

Jul 23 2019, 3:30 AM · Restricted Project, Restricted Project

Jul 16 2019

huntergr updated the diff for D53137: Scalable vector core instruction support + size queries.

Updated based on where scalable size queries were required when running with an SVE-capable loop vectorizer on several codebases (all of LNT, various flavours of SpecCPU, lots of HPC and embedded benchmarks).

Jul 16 2019, 6:59 AM · Restricted Project, Restricted Project

Jul 5 2019

huntergr committed rG957c40db6aeb: Scalable Vector IR Type with further LTO fixes (authored by huntergr).
Scalable Vector IR Type with further LTO fixes
Jul 5 2019, 5:49 AM
huntergr committed rL365203: Scalable Vector IR Type with further LTO fixes.
Scalable Vector IR Type with further LTO fixes
Jul 5 2019, 5:49 AM
huntergr closed D64079: Scalable Vector IR Type (Try 3).
Jul 5 2019, 5:48 AM · Restricted Project

Jul 2 2019

huntergr created D64079: Scalable Vector IR Type (Try 3).
Jul 2 2019, 7:11 AM · Restricted Project

Jun 18 2019

huntergr committed rG43854e3ccc7f: [SVE][IR] Scalable Vector IR Type with pr42210 fix (authored by huntergr).
[SVE][IR] Scalable Vector IR Type with pr42210 fix
Jun 18 2019, 3:11 AM
huntergr committed rL363658: [SVE][IR] Scalable Vector IR Type with pr42210 fix.
[SVE][IR] Scalable Vector IR Type with pr42210 fix
Jun 18 2019, 3:10 AM
huntergr closed D63321: [SVE][IR] Scalable Vector IR Type with pr42210 fix.
Jun 18 2019, 3:10 AM · Restricted Project

Jun 17 2019

huntergr added inline comments to D63321: [SVE][IR] Scalable Vector IR Type with pr42210 fix.
Jun 17 2019, 3:17 AM · Restricted Project

Jun 14 2019

huntergr created D63321: [SVE][IR] Scalable Vector IR Type with pr42210 fix.
Jun 14 2019, 12:58 AM · Restricted Project

Jun 10 2019

huntergr added a comment to D32530: [SVE][IR] Scalable Vector IR Type.

@huntergr do you have an account on bugzilla? I couldn't CC you on that bug.

Jun 10 2019, 2:29 AM · Restricted Project
huntergr added a comment to D32530: [SVE][IR] Scalable Vector IR Type.

Hi, this slowed down thinlto links 3-4x, and other things probably too. PR42210 has details. I've reverted this for now in r362913.

Jun 10 2019, 2:19 AM · Restricted Project

May 29 2019

huntergr committed rGf4fc01f8dd3a: [SVE][IR] Scalable Vector IR Type (authored by huntergr).
[SVE][IR] Scalable Vector IR Type
May 29 2019, 5:25 AM
huntergr committed rL361953: [SVE][IR] Scalable Vector IR Type.
[SVE][IR] Scalable Vector IR Type
May 29 2019, 5:20 AM
huntergr closed D32530: [SVE][IR] Scalable Vector IR Type.
May 29 2019, 5:20 AM · Restricted Project

May 28 2019

huntergr committed rG19e91253c0a5: [NFC] Test commit, delete trailing whitespace (authored by huntergr).
[NFC] Test commit, delete trailing whitespace
May 28 2019, 5:34 AM
huntergr committed rL361813: [NFC] Test commit, delete trailing whitespace.
[NFC] Test commit, delete trailing whitespace
May 28 2019, 5:34 AM

May 23 2019

huntergr updated the diff for D32530: [SVE][IR] Scalable Vector IR Type.
  • Simplified wording for extract/insertelement semantics
May 23 2019, 5:09 AM · Restricted Project

May 22 2019

huntergr updated the diff for D32530: [SVE][IR] Scalable Vector IR Type.
  • Changed textual IR format to <vscale x n x <ty>>
May 22 2019, 7:03 AM · Restricted Project

May 20 2019

huntergr added a comment to D32530: [SVE][IR] Scalable Vector IR Type.

It seems like there's enough support for changing to <vscale x as the prefix, so I'll revise the patch.

May 20 2019, 1:43 AM · Restricted Project

May 10 2019

huntergr updated the diff for D32530: [SVE][IR] Scalable Vector IR Type.
  • Changed (extract|insert)element semantics to return poison values at runtime if the index exceeds hardware vector length.
  • Changed shufflevector semantics to note that only zeroinitializer and undef can be used as mask values for scalable vectors for now.
May 10 2019, 12:05 AM · Restricted Project

May 2 2019

huntergr added a comment to D32530: [SVE][IR] Scalable Vector IR Type.

If you know the exact size of your vectors at compile time, then I believe fixed length vector types should be used, at least at the IR level.

Ah, ok. So let's say we're targeting SVE and I know my vector length is 512b. I was imagining building a vector like this:

%r1 = insertelement <scalable 2 x double> undef, double %x, i32 0  
%r2 = insertelement <scalable 2 x double > %r1, double %x1, i32 1
%r3 = insertelement <scalable 2 x double > %r2, double %x2, i32 2
%r4 = insertelement <scalable 2 x double > %r3, double %x3, i32 3
%r5 = insertelement <scalable 2 x double > %r4, double %x4, i32 4
%r6 = insertelement <scalable 2 x double > %r5, double %x5, i32 5
%r7 = insertelement <scalable 2 x double > %r6, double %x6, i32 6
%r8 = insertelement <scalable 2 x double > %r7, double %x7, i32 7
May 2 2019, 9:35 AM · Restricted Project
huntergr added a comment to D32530: [SVE][IR] Scalable Vector IR Type.

Sorry to be late to the party, but I have a quick question:

Ok, so do we have agreement that constant literal indices should be limited to 0..n-1 for now, but non-constant indices can potentially exceed n so that expressions featuring vscale can be used?

What if we know the width is fixed on our target machine? Let's say it's fixed at 512b. So a full width scalable double vector would be:

<vscale x 2 x double>

Since our width is fixed, we know that vscale=4 here and there are 8 elements in this vector.

I'd like to be able to do a really fast insert at say index 3. I.e. insert_element(<vscale x 2 x double> res, double elt, int 3). Would that insert be as fast with the vscale method as it would be for an index < n-1?

May 2 2019, 8:10 AM · Restricted Project

May 1 2019

huntergr added a comment to D32530: [SVE][IR] Scalable Vector IR Type.

Why implementation defined and not UB for the case where the index exceeds the runtime length? How do you intend to define this for SVE?

SVE uses a predicate for indexed inserts and extracts. We generate that predicate by comparing a splat of the index against a stepvector (0,1,2,3...); if the index is out of range then the predicate will be all false.

For a mov (insert), that results in an unmodified vector.

For a lastb (extract), that extracts the last lane in the vector if no predicate bits are true.

I don't know if RVV or SX-Aurora have similarly defined semantics. If the preference is to make it UB, that's fine.

I think this should be UB, or at least return poison. However, making it UB has the unfortunate side effect of making it illegal to hoist these operations out of conditionals (which currently isn't the case), so maybe poison is better.

For me the main reason for making is UB (aside from generally being conservative) is that element insert/extract can be usefully legalized by putting the vector into a stack slot and accessing the affected element with scalar loads/stores -- in fact, that's the default legalization strategy in trunk. But in that setting an out-of-bounds lane index would become a wild read/write (= clear-cut UB), unless the legalization code jumps through extra hoops to add a bounds check or clamp the lane index into range. This wouldn't affect SVE or RVV since they would implement custom lowering anyway, but for other targets (especially if we eventually generalize insert/extract to accept variable lane positions and do so for all vector types for consistency) it could become an unnecessary headache. Though if we make insertelement with out-of-range lane index return poison instead of being UB, then at minimum clamping in insertelement is necessary to avoid the wild write.

Aside: your proposed semantics for SVE would break the property extractelt(insertelt(vec, i, elt), i) = elt which instcombine (and others) most likely assumes. If we make the insertelt return poison (or even just undef, FWIW), that issue goes away.

I think that making the return be a poison value is best.

May 1 2019, 6:45 AM · Restricted Project
huntergr added a comment to D32530: [SVE][IR] Scalable Vector IR Type.

Noted the change in semantics for extractelement and insertelement in the langref.

Why implementation defined and not UB for the case where the index exceeds the runtime length? How do you intend to define this for SVE?

May 1 2019, 2:25 AM · Restricted Project

Apr 30 2019

huntergr updated the diff for D32530: [SVE][IR] Scalable Vector IR Type.

Noted the change in semantics for extractelement and insertelement in the langref.

Apr 30 2019, 5:11 AM · Restricted Project

Apr 25 2019

huntergr added a comment to D32530: [SVE][IR] Scalable Vector IR Type.

Exactly. Non-constant values can become constant. Constant values can be guarded by vscale-dependent runtime guards (both hand-written and compiler generated). My preference is to leave this not restricted to vscale == 1 values, but rather allow all values that can be supported at runtime, and have it be UB if, at runtime, the relevant index is not available.

+1

That means a need for a warning to general developers: If there is a check for constant_index >= n to see if the result is a poison value, that code has to be changed so that it applies to non-scalable vector only. Hopefully not too many instances of that. I'm fine with this as long as the communication to the rest of LLVM community is clear about it.

Apr 25 2019, 6:14 AM · Restricted Project

Apr 23 2019

huntergr added a comment to D32530: [SVE][IR] Scalable Vector IR Type.

I am not sure how it could be anything but n. If you don't know how long the vector is, you can't correctly generate an index beyond n.

But you know at runtime... there has to be a way to determine, at runtime, vscale. And the index doesn't need to be a constant. I'm not sure that we need to restrict non-constant n to only values valid for vscale == 1.

Good point. 100% agree. I was only considering the constant case.

Apr 23 2019, 5:50 AM · Restricted Project