[ARM] Add missing Tag_DIV_use tests.

[• chatur01]

Summary

Some of the CPUs tested in test/CodeGen/ARM/build-attributes.ll were missing tests for this attribute.

This patch adds the missing tests.

[• chatur01]

Gentle ping.

[rengolin]

Could you add a test for A15 or A7 and add a check for that attribute (among others)? Just to make sure we cover all cases.

Otherwise, LGTM.

[• chatur01]

Hi Renato, happy new year!

In D6721#105733, @rengolin wrote:

Could you add a test for A15 or A7 and add a check for that attribute (among others)? Just to make sure we cover all cases.

The A15 and A7 have existing tests for this tag. This patch adds some missing tests for other CPUs.

This test file isn't exhaustive over the cross product of ARM CPUs / architecture variants / command line options and their effects on build attributes. That would be nice, but I don't have time to finish it off, and perhaps it would be better suited to being mechanically generated rather than maintained by hand due to the size of such a test file.

Otherwise, LGTM.

Thanks, after your blessing of the above, I'll commit.

Thanks for reviewing,
Charlie.

[rengolin]

Makes sense. LGTM. Thanks!

[• chatur01]

Thanks Renato, committed r225348.

test/CodeGen/ARM/build-attributes.ll

 ; V6:   .eabi_attribute 23, 3
 ; V6:   .eabi_attribute 24, 1
 ; V6:   .eabi_attribute 25, 1
 ; V6-NOT:   .eabi_attribute 27
 ; V6-NOT:   .eabi_attribute 28
 ; V6-NOT:    .eabi_attribute 36
 ; V6:    .eabi_attribute 38, 1
 ; V6-NOT:    .eabi_attribute 42
+; V6-NOT:  .eabi_attribute 44
 ; V6-NOT:    .eabi_attribute 68
 
 ; V6-FAST-NOT:   .eabi_attribute 19
 ;; Despite the V6 CPU having no FPU by default, we chose to flush to
 ;; positive zero here. There's no hardware support doing this, but the
 ;; fast maths software library might.
 ; V6-FAST-NOT:   .eabi_attribute 20
 ; V6-FAST-NOT:   .eabi_attribute 21

 ; V6M:   .eabi_attribute 23, 3
 ; V6M:  .eabi_attribute 24, 1
 ; V6M:  .eabi_attribute 25, 1
 ; V6M-NOT:  .eabi_attribute 27
 ; V6M-NOT:  .eabi_attribute 28
 ; V6M-NOT:  .eabi_attribute 36
 ; V6M:  .eabi_attribute 38, 1
 ; V6M-NOT:  .eabi_attribute 42
+; V6M-NOT:  .eabi_attribute 44
 ; V6M-NOT:  .eabi_attribute 68
 
 ; V6M-FAST-NOT:   .eabi_attribute 19
 ;; Despite the V6M CPU having no FPU by default, we chose to flush to
 ;; positive zero here. There's no hardware support doing this, but the
 ;; fast maths software library might.
 ; V6M-FAST-NOT:  .eabi_attribute 20
 ; V6M-FAST-NOT:   .eabi_attribute 21

 ; ARM1156T2F-S: .eabi_attribute 23, 3
 ; ARM1156T2F-S: .eabi_attribute 24, 1
 ; ARM1156T2F-S: .eabi_attribute 25, 1
 ; ARM1156T2F-S-NOT: .eabi_attribute 27
 ; ARM1156T2F-S-NOT: .eabi_attribute 28
 ; ARM1156T2F-S-NOT: .eabi_attribute 36
 ; ARM1156T2F-S: .eabi_attribute 38, 1
 ; ARM1156T2F-S-NOT:    .eabi_attribute 42
+; ARM1156T2F-S-NOT:    .eabi_attribute 44
 ; ARM1156T2F-S-NOT:    .eabi_attribute 68
 
 ; ARM1156T2F-S-FAST-NOT:   .eabi_attribute 19
 ;; V6 cores default to flush to positive zero (value 0). Note that value 2 is also equally
 ;; valid for this core, it's an implementation defined question as to which of 0 and 2 you
 ;; select. LLVM historically picks 0.
 ; ARM1156T2F-S-FAST-NOT: .eabi_attribute 20
 ; ARM1156T2F-S-FAST-NOT:   .eabi_attribute 21

 ; V7: .eabi_attribute 23, 3
 ; V7: .eabi_attribute 24, 1
 ; V7: .eabi_attribute 25, 1
 ; V7-NOT: .eabi_attribute 27
 ; V7-NOT: .eabi_attribute 28
 ; V7-NOT: .eabi_attribute 36
 ; V7: .eabi_attribute 38, 1
 ; V7-NOT:    .eabi_attribute 42
+; V7-NOT:    .eabi_attribute 44
 ; V7-NOT:    .eabi_attribute 68
 
 ; V7-FAST-NOT:   .eabi_attribute 19
 ;; The default CPU does have an FPU and it must be VFPv3 or better, so it flushes
 ;; denormals to zero preserving the sign.
 ; V7-FAST: .eabi_attribute 20, 2
 ; V7-FAST-NOT:   .eabi_attribute 21
 ; V7-FAST-NOT:   .eabi_attribute 22
 ; V7-FAST:   .eabi_attribute 23, 1
 
 ; V8:      .syntax unified
 ; V8: .eabi_attribute 6, 14
 ; V8-NOT:   .eabi_attribute 19
 ; V8: .eabi_attribute 20, 1
 ; V8: .eabi_attribute 21, 1
 ; V8-NOT: .eabi_attribute 22
 ; V8: .eabi_attribute 23, 3
+; V8-NOT: .eabi_attribute 44
 
 ; V8-FAST-NOT:   .eabi_attribute 19
 ;; The default does have an FPU, and for V8-A, it flushes preserving sign.
 ; V8-FAST: .eabi_attribute 20, 2
 ; V8-FAST-NOT: .eabi_attribute 21
 ; V8-FAST-NOT: .eabi_attribute 22
 ; V8-FAST: .eabi_attribute 23, 1
 

 ;; We default to IEEE 754 compliance
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 20, 1
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 21, 1
 ; CORTEX-A5-DEFAULT-NOT:        .eabi_attribute 22
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 23, 3
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 24, 1
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 25, 1
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 42, 1
+; CORTEX-A5-DEFAULT-NOT:        .eabi_attribute 44
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 68, 1
 
 ; CORTEX-A5-DEFAULT-FAST-NOT:   .eabi_attribute 19
 ;; The A5 defaults to a VFPv4 FPU, so it flushed preserving sign when -ffast-math
 ;; is given.
 ; CORTEX-A5-DEFAULT-FAST:        .eabi_attribute 20, 2
 ; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 21
 ; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 22

 ; CORTEX-A9-SOFT:  .eabi_attribute 23, 3
 ; CORTEX-A9-SOFT:  .eabi_attribute 24, 1
 ; CORTEX-A9-SOFT:  .eabi_attribute 25, 1
 ; CORTEX-A9-SOFT-NOT:  .eabi_attribute 27
 ; CORTEX-A9-SOFT-NOT:  .eabi_attribute 28
 ; CORTEX-A9-SOFT:  .eabi_attribute 36, 1
 ; CORTEX-A9-SOFT:  .eabi_attribute 38, 1
 ; CORTEX-A9-SOFT:  .eabi_attribute 42, 1
+; CORTEX-A9-SOFT-NOT:  .eabi_attribute 44
 ; CORTEX-A9-SOFT:  .eabi_attribute 68, 1
 
 ; CORTEX-A9-SOFT-FAST-NOT:   .eabi_attribute 19
 ;; The A9 defaults to a VFPv3 FPU, so it flushes preseving sign when
 ;; -ffast-math is specified.
 ; CORTEX-A9-SOFT-FAST:  .eabi_attribute 20, 2
 ; CORTEX-A5-SOFT-FAST-NOT: .eabi_attribute 21
 ; CORTEX-A5-SOFT-FAST-NOT: .eabi_attribute 22

 ; CORTEX-M0:  .eabi_attribute 23, 3
 ; CORTEX-M0:  .eabi_attribute 24, 1
 ; CORTEX-M0:  .eabi_attribute 25, 1
 ; CORTEX-M0-NOT:  .eabi_attribute 27
 ; CORTEX-M0-NOT:  .eabi_attribute 28
 ; CORTEX-M0-NOT:  .eabi_attribute 36
 ; CORTEX-M0:  .eabi_attribute 38, 1
 ; CORTEX-M0-NOT:  .eabi_attribute 42
+; CORTEX-M0-NOT:  .eabi_attribute 44
 ; CORTEX-M0-NOT:  .eabi_attribute 68
 
 ; CORTEX-M0-FAST-NOT:   .eabi_attribute 19
 ;; Despite the M0 CPU having no FPU in this scenario, we chose to
 ;; flush to positive zero here. There's no hardware support doing
 ;; this, but the fast maths software library might and such behaviour
 ;; would match hardware support on this architecture revision if it
 ;; existed.