[AArch64] Add command-line option for SSBS

[pbarrio]

Summary

SSBS (Speculative Store Bypass Safe) is only mandatory from 8.5
onwards but is optional from Armv8.0-A. This patch adds a command
line option to enable SSBS, as it was previously only possible to
enable by selecting -march=armv8.5-a.

Similar patch upstream in GNU binutils:
https://sourceware.org/ml/binutils/2018-09/msg00274.html

[pbarrio]

The Armv8.5-A specification is available here: https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools

[samparker]

Hi Pablo,

Pardon my ignorance, but what's the interaction between the 'spec restrict' feature and ssbs? I see they both exist but in a couple of cases, FeaturesSSBS has replaced FeatureSpecRestrict. Also, is there a matching patch for clang?

[pbarrio]

Thank you for the review, Sam :)

FeatureSpecRestrict was really enabling two features, not one, both related to speculation restriction in the CPU. These features were the Software Context Number registers (SCXTNUM_ELx) and the Speculative Store Bypass Safe (SSBS) bit. We just added them into the same back-end feature initially because they are mandatory in 8.5 (i.e. no command line option required in 8.5). However, these security features are optional down to 8.0, so we want to allow them separately via a command-line option. This patch just spawns SSBS out of SpecRestrict.

Good point about the Clang patch. No changes inside clang itself (it picks up everything from tablegen directly) but I've added some testing. Now available for review at https://reviews.llvm.org/D54961. Feel free to point out there if I missed something.

[samparker]

Thanks for the explanation, LGTM!

[pbarrio]

Rebased onto master after a recent refactoring of the AArch64 target parser.

llvm/trunk/include/llvm/Support/AArch64TargetParser.h

enum ArchExtKind : unsigned {
   AEK_RDM =         1 << 12,
   AEK_SM4 =         1 << 13,
   AEK_SHA3 =        1 << 14,
   AEK_SHA2 =        1 << 15,
   AEK_AES =         1 << 16,
   AEK_FP16FML =     1 << 17,
   AEK_RAND =        1 << 18,
   AEK_MTE =         1 << 19,
+  AEK_SSBS =        1 << 20,
 };
 
 enum class ArchKind {
 #define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,
 #include "AArch64TargetParser.def"
 };
 
 const ARM::ArchNames<ArchKind> AArch64ARCHNames[] = {

llvm/trunk/include/llvm/Support/AArch64TargetParser.def

 AARCH64_ARCH_EXT_NAME("fp16",     AArch64::AEK_FP16,     "+fullfp16",  "-fullfp16")
 AARCH64_ARCH_EXT_NAME("fp16fml",  AArch64::AEK_FP16FML,  "+fp16fml", "-fp16fml")
 AARCH64_ARCH_EXT_NAME("profile",  AArch64::AEK_PROFILE,  "+spe",  "-spe")
 AARCH64_ARCH_EXT_NAME("ras",      AArch64::AEK_RAS,      "+ras",  "-ras")
 AARCH64_ARCH_EXT_NAME("sve",      AArch64::AEK_SVE,      "+sve",  "-sve")
 AARCH64_ARCH_EXT_NAME("rcpc",     AArch64::AEK_RCPC,     "+rcpc", "-rcpc")
 AARCH64_ARCH_EXT_NAME("rng",      AArch64::AEK_RAND,     "+rand",  "-rand")
 AARCH64_ARCH_EXT_NAME("memtag",   AArch64::AEK_MTE,      "+mte",   "-mte")
+AARCH64_ARCH_EXT_NAME("ssbs",     AArch64::AEK_SSBS,     "+ssbs",  "-ssbs")
 #undef AARCH64_ARCH_EXT_NAME
 
 #ifndef AARCH64_CPU_NAME
 #define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)
 #endif
 AARCH64_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
                 (AArch64::AEK_CRC))
 AARCH64_CPU_NAME("cortex-a53", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, true,

llvm/trunk/lib/Target/AArch64/AArch64.td

 
 def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
   "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
   "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >;
 
 def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
   "true", "Enable architectural speculation restriction" >;
 
+def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
+  "true", "Enable Speculative Store Bypass Safe bit" >;
+
 def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true",
   "Enable speculation control barrier" >;
 
 def FeaturePredCtrl : SubtargetFeature<"predctrl", "HasPredCtrl", "true",
   "Enable execution and data prediction invalidation instructions" >;
 
 def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
     "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >;
def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
   "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
   FeatureNV, FeatureRASv8_4, FeatureMPAM, FeatureDIT,
   FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI,
   FeatureFMI, FeatureRCPC_IMMO]>;
 
 def HasV8_5aOps : SubtargetFeature<
   "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
   [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
-   FeatureSpecCtrl, FeaturePredCtrl, FeatureCacheDeepPersist,
+   FeatureSSBS, FeatureSpecCtrl, FeaturePredCtrl, FeatureCacheDeepPersist,
    FeatureBranchTargetId]
 >;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "AArch64RegisterInfo.td"

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h

protected:
   bool HasRCPC = false;
   bool HasAggressiveFMA = false;
 
   // Armv8.5-A Extensions
   bool HasAlternativeNZCV = false;
   bool HasFRInt3264 = false;
   bool HasSpecRestrict = false;
   bool HasSpecCtrl = false;
+  bool HasSSBS = false;
   bool HasPredCtrl = false;
   bool HasCCDP = false;
   bool HasBTI = false;
   bool HasRandGen = false;
   bool HasMTE = false;
 
   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
   bool HasZeroCycleRegMove = false;
public:
   bool hasLSLFast() const { return HasLSLFast; }
   bool hasSVE() const { return HasSVE; }
   bool hasRCPC() const { return HasRCPC; }
   bool hasAggressiveFMA() const { return HasAggressiveFMA; }
   bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
   bool hasFRInt3264() const { return HasFRInt3264; }
   bool hasSpecRestrict() const { return HasSpecRestrict; }
   bool hasSpecCtrl() const { return HasSpecCtrl; }
+  bool hasSSBS() const { return HasSSBS; }
   bool hasPredCtrl() const { return HasPredCtrl; }
   bool hasCCDP() const { return HasCCDP; }
   bool hasBTI() const { return HasBTI; }
   bool hasRandGen() const { return HasRandGen; }
   bool hasMTE() const { return HasMTE; }
 
   bool isLittleEndian() const { return IsLittle; }
 

llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td

 
 // v8.2a "User Access Override" extension-specific PStates
 let Requires = [{ {AArch64::FeaturePsUAO} }] in
 def : PState<"UAO",     0b00011>;
 // v8.4a timining insensitivity of data processing instructions
 let Requires = [{ {AArch64::FeatureDIT} }] in
 def : PState<"DIT",     0b11010>;
 // v8.5a Spectre Mitigation
-let Requires = [{ {AArch64::FeatureSpecRestrict} }] in
+let Requires = [{ {AArch64::FeatureSSBS} }] in
 def : PState<"SSBS",    0b11001>;
 // v8.5a Memory Tagging Extension
 let Requires = [{ {AArch64::FeatureMTE} }] in
 def : PState<"TCO",     0b11100>;
 
 //===----------------------------------------------------------------------===//
 // PSB instruction options.
 //===----------------------------------------------------------------------===//

 def : RWSysReg<"ZCR_EL1",          0b11, 0b000, 0b0001, 0b0010, 0b000>;
 def : RWSysReg<"ZCR_EL2",          0b11, 0b100, 0b0001, 0b0010, 0b000>;
 def : RWSysReg<"ZCR_EL3",          0b11, 0b110, 0b0001, 0b0010, 0b000>;
 def : RWSysReg<"ZCR_EL12",         0b11, 0b101, 0b0001, 0b0010, 0b000>;
 }
 
 // V8.5a Spectre mitigation SSBS register
 //                     Op0   Op1    CRn     CRm     Op2
-let Requires = [{ {AArch64::FeatureSpecRestrict} }] in
+let Requires = [{ {AArch64::FeatureSSBS} }] in
 def : RWSysReg<"SSBS", 0b11, 0b011, 0b0100, 0b0010, 0b110>;
 
 // v8.5a Memory Tagging Extension
 //                                 Op0   Op1    CRn     CRm     Op2
 let Requires = [{ {AArch64::FeatureMTE} }] in {
 def : RWSysReg<"TCO",              0b11, 0b011, 0b0100, 0b0010, 0b111>;
 def : RWSysReg<"GCR_EL1",          0b11, 0b000, 0b0001, 0b0000, 0b110>;
 def : RWSysReg<"RGSR_EL1",         0b11, 0b000, 0b0001, 0b0000, 0b101>;

llvm/trunk/test/MC/AArch64/armv8.5a-specrestrict-error.s

-// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+specrestrict < %s 2>&1 | FileCheck %s
-// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a        < %s 2>&1 | FileCheck %s
-// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-specrestrict < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID
-
-msr SSBS, #2
-
-// CHECK:         error: immediate must be an integer in range [0, 1].
-// CHECK-NEXT:    msr SSBS, #2
-// NOSPECID:      error: expected writable system register or pstate
-// NOSPECID-NEXT: msr {{ssbs|SSBS}}, #2

llvm/trunk/test/MC/AArch64/armv8.5a-specrestrict.s

 // NOSPECID:      error: expected writable system register
 // NOSPECID-NEXT: {{scxtnum_el1|SCXTNUM_EL1}}
 // NOSPECID:      error: expected writable system register
 // NOSPECID-NEXT: {{scxtnum_el2|SCXTNUM_EL2}}
 // NOSPECID:      error: expected writable system register
 // NOSPECID-NEXT: {{scxtnum_el3|SCXTNUM_EL3}}
 // NOSPECID:      error: expected writable system register
 // NOSPECID-NEXT: {{scxtnum_el12|SCXTNUM_EL12}}
-
-mrs x2, SSBS
-
-// CHECK:         mrs x2, {{ssbs|SSBS}} // encoding: [0xc2,0x42,0x3b,0xd5]
-// NOSPECID:      error: expected readable system register
-// NOSPECID-NEXT: mrs x2, {{ssbs|SSBS}}
-
-msr SSBS, x3
-msr SSBS, #1
-
-// CHECK:         msr {{ssbs|SSBS}}, x3 // encoding: [0xc3,0x42,0x1b,0xd5]
-// CHECK:         msr {{ssbs|SSBS}}, #1 // encoding: [0x3f,0x41,0x03,0xd5]
-// NOSPECID:      error: expected writable system register or pstate
-// NOSPECID-NEXT: msr {{ssbs|SSBS}}, x3
-// NOSPECID:      error: expected writable system register or pstate
-// NOSPECID-NEXT: msr {{ssbs|SSBS}}, #1

llvm/trunk/test/MC/AArch64/armv8.5a-ssbs-error.s

+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+ssbs  < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-ssbs  < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID
+
+msr SSBS, #2
+
+// CHECK:         error: immediate must be an integer in range [0, 1].
+// CHECK-NEXT:    msr SSBS, #2
+// NOSPECID:      error: expected writable system register or pstate
+// NOSPECID-NEXT: msr {{ssbs|SSBS}}, #2

llvm/trunk/test/MC/AArch64/armv8.5a-ssbs.s

+// RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+ssbs  < %s      | FileCheck %s
+// RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s      | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-ssbs  < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID
+
+mrs x2, SSBS
+
+// CHECK:         mrs x2, {{ssbs|SSBS}} // encoding: [0xc2,0x42,0x3b,0xd5]
+// NOSPECID:      error: expected readable system register
+// NOSPECID-NEXT: mrs x2, {{ssbs|SSBS}}
+
+msr SSBS, x3
+msr SSBS, #1
+
+// CHECK:         msr {{ssbs|SSBS}}, x3 // encoding: [0xc3,0x42,0x1b,0xd5]
+// CHECK:         msr {{ssbs|SSBS}}, #1 // encoding: [0x3f,0x41,0x03,0xd5]
+// NOSPECID:      error: expected writable system register or pstate
+// NOSPECID-NEXT: msr {{ssbs|SSBS}}, x3
+// NOSPECID:      error: expected writable system register or pstate
+// NOSPECID-NEXT: msr {{ssbs|SSBS}}, #1

llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt

 # CHECK:    msr {{scxtnum_el2|SCXTNUM_EL2}},   x6
 # CHECK:    msr {{scxtnum_el3|SCXTNUM_EL3}},   x5
 # CHECK:    msr {{scxtnum_el12|SCXTNUM_EL12}}, x4
 # NOSPECID: msr S3_3_C13_C0_7, x8
 # NOSPECID: msr S3_0_C13_C0_7, x7
 # NOSPECID: msr S3_4_C13_C0_7, x6
 # NOSPECID: msr S3_6_C13_C0_7, x5
 # NOSPECID: msr S3_5_C13_C0_7, x4
-
-[0x3f 0x41 0x03 0xd5]
-[0xc3 0x42 0x1b 0xd5]
-[0xc2 0x42 0x3b 0xd5]
-# CHECK:    msr SSBS, #1
-# CHECK:    msr SSBS, x3
-# CHECK:    mrs x2, SSBS
-# NOSPECID: msr S0_3_C4_C1_1, xzr
-# NOSPECID: msr S3_3_C4_C2_6, x3
-# NOSPECID: mrs x2, S3_3_C4_C2_6

llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt

+# RUN: llvm-mc -triple=aarch64 -mattr=+ssbs  -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=-ssbs  -disassemble < %s | FileCheck %s --check-prefix=NOSPECID
+
+[0x3f 0x41 0x03 0xd5]
+[0xc3 0x42 0x1b 0xd5]
+[0xc2 0x42 0x3b 0xd5]
+# CHECK:    msr SSBS, #1
+# CHECK:    msr SSBS, x3
+# CHECK:    mrs x2, SSBS
+# NOSPECID: msr S0_3_C4_C1_1, xzr
+# NOSPECID: msr S3_3_C4_C2_6, x3
+# NOSPECID: mrs x2, S3_3_C4_C2_6

llvm/trunk/unittests/Support/TargetParserTest.cpp

TEST(TargetParserTest, testARMExtension) {
   EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::IWMMXT, "crc"));
   EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::IWMMXT2, "crc"));
   EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::XSCALE, "crc"));
   EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV7S, "crypto"));
   EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV7K, "crypto"));
 }
 
 TEST(TargetParserTest, ARMFPUVersion) {
-  for (ARM::FPUKind FK = static_cast<ARM::FPUKind>(0); 
+  for (ARM::FPUKind FK = static_cast<ARM::FPUKind>(0);
        FK <= ARM::FPUKind::FK_LAST;
        FK = static_cast<ARM::FPUKind>(static_cast<unsigned>(FK) + 1))
     if (FK == ARM::FK_LAST || ARM::getFPUName(FK) == "invalid" ||
         ARM::getFPUName(FK) == "none" || ARM::getFPUName(FK) == "softvfp")
       EXPECT_EQ(ARM::FPUVersion::NONE, ARM::getFPUVersion(FK));
     else
       EXPECT_NE(ARM::FPUVersion::NONE, ARM::getFPUVersion(FK));
 }
const char *ArchExt[][4] = {{"crc", "nocrc", "+crc", "-crc"},
                               {"profile", "noprofile", "+spe", "-spe"},
                               {"ras", "noras", "+ras", "-ras"},
                               {"lse", "nolse", "+lse", "-lse"},
                               {"rdm", "nordm", "+rdm", "-rdm"},
                               {"sve", "nosve", "+sve", "-sve"},
                               {"dotprod", "nodotprod", "+dotprod", "-dotprod"},
                               {"rcpc", "norcpc", "+rcpc", "-rcpc" },
                               {"rng", "norng", "+rand", "-rand"},
-                              {"memtag", "nomemtag", "+mte", "-mte"}};
+                              {"memtag", "nomemtag", "+mte", "-mte"},
+                              {"ssbs", "nossbs", "+ssbs", "-ssbs"}};
 
   for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
     EXPECT_EQ(StringRef(ArchExt[i][2]),
               AArch64::getArchExtFeature(ArchExt[i][0]));
     EXPECT_EQ(StringRef(ArchExt[i][3]),
               AArch64::getArchExtFeature(ArchExt[i][1]));
   }
 }
 }