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[AArch64] Fix an ISEL failure around half float data type

Authored by Jiangning on Aug 28 2014, 2:00 AM.



This patch is to fix an ISEL failure around half float data type. The fix covers two things,

  1. Some bitcast patterns around v8f16 are missing in AArch64 back-end.
  2. The promotion of v8f16 to v8i16 for the operand of load/store is missing. Since for little-end we only generate ldr/str, we can use big-endian to capture the failure exposed by pattern match for instruction ld1/st1.


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Jiangning updated this revision to Diff 13023.Aug 28 2014, 2:00 AM
Jiangning retitled this revision from to [AArch64] Fix an ISEL failure around half float data type.
Jiangning updated this object.
Jiangning edited the test plan for this revision. (Show Details)
Jiangning added a reviewer: t.p.northover.
Jiangning set the repository for this revision to rL LLVM.
Jiangning added a subscriber: Unknown Object (MLST).

Hi Jiangning,

You accidentally changed the file to be an executable in the repository.


jmolloy accepted this revision.Aug 28 2014, 3:01 AM
jmolloy added a reviewer: jmolloy.
jmolloy added a subscriber: jmolloy.

Hi Jiangning,

This patch looks good to me (with the accidental property change reverted). Are we going to add support for v4f16 too?



This revision is now accepted and ready to land.Aug 28 2014, 3:01 AM

Hi James and Renato,

I will not commit the file property change.

I've double checked the code and v4f16 has been perfectly supported, so we don't need change anything around v4f16.


mcrosier closed this revision.Aug 28 2014, 8:56 PM

Committed r216706.