[ARM] Relax condition for PerformSHLSimplify

[samparker]

Summary

PerformSHLSimplify previously would be bail if one of given node's users had a shl operand because the transformation wouldn't necessarily combine the shift into the user nodes. I guess this should have also happened for other shifts too... Anyway, by removing this restriction we can still remove mov instructions or a mov is replaced by a shift, which sometimes can help register pressure.

[john.brawn]

It looks like loosening this restriction doesn't necessarily lead to better code being generated, e.g. looking at load_i32_by_i8_bswap in load-combine-big-endian.ll that lsl r0, r0, #24 introduces a register dependency that wasn't there before which likely makes this worse on an in-order CPU.

Looking at the tests you added it looks like doing this is of benefit when it turns an immediate which can't be encoded (510) into an immediate which can (255), so maybe you should be checking for that? Maybe instead of removing the "is the other operand already a shift" check set a bool, and then later when you know the pre- and post-shift constants only proceed if that bool is false of if the constant is now better.

[samparker]

Thanks John, I'll try those changes.

[samparker]

Hi John,

I've changed the function to check the immediate to handle the subtle differences between Thumb and Arm immediate encoding. I also tried exiting early when there's a shifted user and the immediate is already valid, but this produced worse code for almost all my new tests. The problem is that a mov is still required because the bin op is using an immediate and a shifted operand. This is particularly worse for Thumb where code size increase is greater as well.

lib/Target/ARM/ARMISelLowering.cpp

10478

I'll remove this whitespace.

[john.brawn]

In D44098#1029809, @samparker wrote:

I also tried exiting early when there's a shifted user and the immediate is already valid, but this produced worse code for almost all my new tests. The problem is that a mov is still required because the bin op is using an immediate and a shifted operand. This is particularly worse for Thumb where code size increase is greater as well.

It looks like, in the added tests at least, what we should be trying to do is:

• We have this node N
• We want to transform this node so that its user can use it in a shifted operand, in a way that saves us an instruction
• If the user already has another operand that it can use as a shifted operand, then we won't actually be saving an instruction in that way
• But we can save an instruction if this transformation causes an immediate to be a valid operand meaning we can eliminate a mov

I think it's specifically the "check that the other operand of the user could be used as a shifted operand" that we need to be careful about. Just checking for a shift isn't right in thumb because it's only a shift by an immediate that can be used as an operand, but in arm we can do that so the check needs to take that into account.

[samparker]

Could you provide me with an example to illustrate your concern please? I keep going around in circles and I just see either the number of instructions or register pressure being reduced. Could the codegen of my new tests be improved?

lib/Target/ARM/ARMISelLowering.cpp

     case ISD::SETCC:
     case ARMISD::CMP:
       // Check that the user isn't already using a constant because there
       // aren't any instructions that support an immediate operand and a
       // shifted operand.
       if (isa<ConstantSDNode>(U->getOperand(0)) ||
           isa<ConstantSDNode>(U->getOperand(1)))
         return SDValue();
-
-      // Check that its not already using a shift.
-      if (U->getOperand(0).getOpcode() == ISD::SHL ||
-          U->getOperand(1).getOpcode() == ISD::SHL)
-        return SDValue();
       break;
     }
   }
 
   if (N->getOpcode() != ISD::ADD && N->getOpcode() != ISD::OR &&
       N->getOpcode() != ISD::XOR && N->getOpcode() != ISD::AND)
     return SDValue();
 

   APInt C1Int = C1ShlC2->getAPIntValue();
 
   // Check that performing a lshr will not lose any information.
   APInt Mask = APInt::getHighBitsSet(C2Int.getBitWidth(),
                                      C2Int.getBitWidth() - C2->getZExtValue());
   if ((C1Int & Mask) != C1Int)
     return SDValue();
 
   // Shift the first constant.
   C1Int.lshrInPlace(C2Int);
 
   // The immediates are encoded as an 8-bit value that can be rotated.
   auto LargeImm = [](const APInt &Imm) {
     unsigned Zeros = Imm.countLeadingZeros() + Imm.countTrailingZeros();
     return Imm.getBitWidth() - Zeros > 8;
   };
 

test/CodeGen/ARM/load-combine-big-endian.ll

 }
 
 ; i8* p; // p is 4 byte aligned
 ; (i32) p[0] | ((i32) p[1] << 8) | ((i32) p[2] << 16) | ((i32) p[3] << 24)
 define i32 @load_i32_by_i8_bswap(i32* %arg) {
 ; BSWAP is not supported by 32 bit target
 ; CHECK-LABEL: load_i32_by_i8_bswap:
 ; CHECK: ldr  r0, [r0]
-; CHECK: and
-; CHECK-NEXT: and
-; CHECK-NEXT: orr
-; CHECK-NEXT: orr
-; CHECK-NEXT: orr
+; CHECK-NEXT: mov r1, #65280
+; CHECK-NEXT: and r2, r0, #65280
+; CHECK-NEXT: and r1, r1, r0, lsr #8
+; CHECK-NEXT: orr r1, r1, r0, lsr #24
+; CHECK-NEXT: lsl r0, r0, #24
+; CHECK-NEXT: orr r0, r0, r2, lsl #8
+; CHECK-NEXT: orr r0, r0, r1
 ; CHECK-NEXT: mov pc, lr
 
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap:
 ; CHECK-ARMv6: ldr  r0, [r0]
 ; CHECK-ARMv6-NEXT: rev  r0, r0
 ; CHECK-ARMv6-NEXT: bx lr
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0

 }
 
 ; i8* p; // p is 8 byte aligned
 ; (i64) p[0] | ((i64) p[1] << 8) | ((i64) p[2] << 16) | ((i64) p[3] << 24) | ((i64) p[4] << 32) | ((i64) p[5] << 40) | ((i64) p[6] << 48) | ((i64) p[7] << 56)
 define i64 @load_i64_by_i8_bswap(i64* %arg) {
 ; CHECK-LABEL: load_i64_by_i8_bswap:
 ; CHECK: ldr{{.*}}r0
 ; CHECK: ldr{{.*}}r0
-; CHECK: and
-; CHECK-NEXT: and
-; CHECK-NEXT: orr
-; CHECK-NEXT: orr
-; CHECK-NEXT: and
-; CHECK-NEXT: orr
-; CHECK-NEXT: and
-; CHECK-NEXT: orr
-; CHECK-NEXT: orr
-; CHECK-NEXT: orr
-; CHECK: mov pc, lr
+; CHECK-NEXT: and r2, r0, #65280
+; CHECK-NEXT: and r3, r12, r0, lsr #8
+; CHECK-NEXT: orr r3, r3, r0, lsr #24
+; CHECK-NEXT: lsl r0, r0, #24
+; CHECK-NEXT: orr r0, r0, r2, lsl #8
+; CHECK-NEXT: and r2, r12, r1, lsr #8
+; CHECK-NEXT: orr r0, r0, r3
+; CHECK-NEXT: and r3, r1, #65280
+; CHECK-NEXT: orr r2, r2, r1, lsr #24
+; CHECK-NEXT: lsl r1, r1, #24
+; CHECK-NEXT: orr r1, r1, r3, lsl #8
+; CHECK-NEXT: orr r1, r1, r2
+; CHECK-NEXT: mov pc, lr
 
 ; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap:
 ; CHECK-ARMv6: ldrd  r2, r3, [r0]
 ; CHECK-ARMv6: rev r0, r3
 ; CHECK-ARMv6: rev r1, r2
 ; CHECK-ARMv6: bx  lr
   %tmp = bitcast i64* %arg to i8*
   %tmp1 = load i8, i8* %tmp, align 8

 }
 
 ; i8* p; // p[1] is 4 byte aligned
 ; (i32) p[1] | ((i32) p[2] << 8) | ((i32) p[3] << 16) | ((i32) p[4] << 24)
 define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_i8_nonzero_offset:
 ; CHECK: ldr r0, [r0, #1]
 ; CHECK-NEXT: mov r1, #65280
-; CHECK-NEXT: mov r2, #16711680
+; CHECK-NEXT: and r2, r0, #65280
 ; CHECK-NEXT: and r1, r1, r0, lsr #8
-; CHECK-NEXT: and r2, r2, r0, lsl #8
 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
-; CHECK-NEXT: orr r0, r2, r0, lsl #24
+; CHECK-NEXT: lsl r0, r0, #24
+; CHECK-NEXT: orr r0, r0, r2, lsl #8
 ; CHECK-NEXT: orr r0, r0, r1
 ; CHECK-NEXT: mov pc, lr
 
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset:
 ; CHECK-ARMv6: ldr r0, [r0, #1]
 ; CHECK-ARMv6-NEXT: rev r0, r0
 ; CHECK-ARMv6-NEXT: bx  lr
 

 }
 
 ; i8* p; // p[-4] is 4 byte aligned
 ; (i32) p[-4] | ((i32) p[-3] << 8) | ((i32) p[-2] << 16) | ((i32) p[-1] << 24)
 define i32 @load_i32_by_i8_neg_offset(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_i8_neg_offset:
 ; CHECK: ldr r0, [r0, #-4]
 ; CHECK-NEXT: mov r1, #65280
-; CHECK-NEXT: mov r2, #16711680
+; CHECK-NEXT: and r2, r0, #65280
 ; CHECK-NEXT: and r1, r1, r0, lsr #8
-; CHECK-NEXT: and r2, r2, r0, lsl #8
 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
-; CHECK-NEXT: orr r0, r2, r0, lsl #24
+; CHECK-NEXT: lsl r0, r0, #24
+; CHECK-NEXT: orr r0, r0, r2, lsl #8
 ; CHECK-NEXT: orr r0, r0, r1
 ; CHECK-NEXT: mov pc, lr
 
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset:
 ; CHECK-ARMv6: ldr r0, [r0, #-4]
 ; CHECK-ARMv6-NEXT: rev r0, r0
 ; CHECK-ARMv6-NEXT: bx  lr
 

 declare i16 @llvm.bswap.i16(i16)
 
 ; i16* p; // p is 4 byte aligned
 ; (i32) bswap(p[0]) | (i32) bswap(p[1] << 16)
 define i32 @load_i32_by_bswap_i16(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_bswap_i16:
 ; CHECK: ldr r0, [r0]
 ; CHECK-NEXT: mov r1, #65280
-; CHECK-NEXT: mov r2, #16711680
+; CHECK-NEXT: and r2, r0, #65280
 ; CHECK-NEXT: and r1, r1, r0, lsr #8
-; CHECK-NEXT: and r2, r2, r0, lsl #8
 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
-; CHECK-NEXT: orr r0, r2, r0, lsl #24
+; CHECK-NEXT: lsl r0, r0, #24
+; CHECK-NEXT: orr r0, r0, r2, lsl #8
 ; CHECK-NEXT: orr r0, r0, r1
 ; CHECK-NEXT: mov pc, lr
 
 ; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16:
 ; CHECK-ARMv6: ldr  r0, [r0]
 ; CHECK-ARMv6-NEXT: rev r0, r0
 ; CHECK-ARMv6-NEXT: bx  lr
 

 
 ; i8* arg; i32 i;
 ; p = arg + 12;
 ; (i32) p[i] | ((i32) p[i + 1] << 8) | ((i32) p[i + 2] << 16) | ((i32) p[i + 3] << 24)
 define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
 ; CHECK-LABEL: load_i32_by_i8_base_offset_index:
 ; CHECK: add r0, r0, r1
 ; CHECK-NEXT: mov r1, #65280
-; CHECK-NEXT: mov r2, #16711680
 ; CHECK-NEXT: ldr r0, [r0, #12]
+; CHECK-NEXT: and r2, r0, #65280
 ; CHECK-NEXT: and r1, r1, r0, lsr #8
-; CHECK-NEXT: and r2, r2, r0, lsl #8
 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
-; CHECK-NEXT: orr r0, r2, r0, lsl #24
+; CHECK-NEXT: lsl r0, r0, #24
+; CHECK-NEXT: orr r0, r0, r2, lsl #8
 ; CHECK-NEXT: orr r0, r0, r1
 ; CHECK-NEXT: mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index:
 ; CHECK-ARMv6: add r0, r0, r1
 ; CHECK-ARMv6-NEXT: ldr r0, [r0, #12]
 ; CHECK-ARMv6-NEXT: rev r0, r0
 ; CHECK-ARMv6-NEXT: bx  lr

 
 ; i8* arg; i32 i;
 ; p = arg + 12;
 ; (i32) p[i + 1] | ((i32) p[i + 2] << 8) | ((i32) p[i + 3] << 16) | ((i32) p[i + 4] << 24)
 define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
 ; CHECK-LABEL: load_i32_by_i8_base_offset_index_2:
 ; CHECK: add r0, r0, r1
 ; CHECK-NEXT: mov r1, #65280
-; CHECK-NEXT: mov r2, #16711680
 ; CHECK-NEXT: ldr r0, [r0, #13]
+; CHECK-NEXT: and r2, r0, #65280
 ; CHECK-NEXT: and r1, r1, r0, lsr #8
-; CHECK-NEXT: and r2, r2, r0, lsl #8
 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
-; CHECK-NEXT: orr r0, r2, r0, lsl #24
+; CHECK-NEXT: lsl r0, r0, #24
+; CHECK-NEXT: orr r0, r0, r2, lsl #8
 ; CHECK-NEXT: orr r0, r0, r1
 ; CHECK-NEXT: mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index_2:
 ; CHECK-ARMv6: add r0, r0, r1
 ; CHECK-ARMv6-NEXT: ldr r0, [r0, #13]
 ; CHECK-ARMv6-NEXT: rev r0, r0
 ; CHECK-ARMv6-NEXT: bx  lr

test/CodeGen/ARM/load-combine.ll

 }
 
 ; i8* p; // p is 4 byte aligned
 ; ((i32) p[0] << 24) | ((i32) p[1] << 16) | ((i32) p[2] << 8) | (i32) p[3]
 define i32 @load_i32_by_i8_bswap(i32* %arg) {
 ; BSWAP is not supported by 32 bit target
 ; CHECK-LABEL: load_i32_by_i8_bswap:
 ; CHECK: ldr r0, [r0]
-; CHECK: and
-; CHECK-NEXT: and
-; CHECK-NEXT: orr
-; CHECK-NEXT: orr
-; CHECK-NEXT: orr
+; CHECK-NEXT: mov r1, #65280
+; CHECK-NEXT: and r2, r0, #65280
+; CHECK-NEXT: and r1, r1, r0, lsr #8
+; CHECK-NEXT: orr r1, r1, r0, lsr #24
+; CHECK-NEXT: lsl r0, r0, #24
+; CHECK-NEXT: orr r0, r0, r2, lsl #8
+; CHECK-NEXT: orr r0, r0, r1
 ; CHECK: mov pc, lr
 
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap:
 ; CHECK-ARMv6: ldr  r0, [r0]
 ; CHECK-ARMv6-NEXT: rev  r0, r0
 ; CHECK-ARMv6-NEXT: bx lr
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = load i8, i8* %tmp, align 4

 
 ; i8* p; // p is 8 byte aligned
 ; ((i64) p[0] << 56) | ((i64) p[1] << 48) | ((i64) p[2] << 40) | ((i64) p[3] << 32) | ((i64) p[4] << 24) | ((i64) p[5] << 16) | ((i64) p[6] << 8) | (i64) p[7]
 define i64 @load_i64_by_i8_bswap(i64* %arg) {
 ; CHECK-LABEL: load_i64_by_i8_bswap:
 ; CHECK: ldr{{.*}}r0
 ; CHECK: ldr{{.*}}r0
 ; CHECK: and
-; CHECK-NEXT: and
-; CHECK-NEXT: orr
-; CHECK-NEXT: orr
-; CHECK-NEXT: and
-; CHECK-NEXT: orr
-; CHECK-NEXT: and
-; CHECK-NEXT: orr
-; CHECK-NEXT: orr
-; CHECK-NEXT: orr
-; CHECK: mov pc, lr
+; CHECK-NEXT: and r3, r12, r0, lsr #8
+; CHECK-NEXT: orr r3, r3, r0, lsr #24
+; CHECK-NEXT: lsl r0, r0, #24
+; CHECK-NEXT: orr r0, r0, r2, lsl #8
+; CHECK-NEXT: and r2, r12, r1, lsr #8
+; CHECK-NEXT: orr r0, r0, r3
+; CHECK-NEXT: and r3, r1, #65280
+; CHECK-NEXT: orr r2, r2, r1, lsr #24
+; CHECK-NEXT: lsl r1, r1, #24
+; CHECK-NEXT: orr r1, r1, r3, lsl #8
+; CHECK-NEXT: orr r1, r1, r2
+; CHECK-NEXT: mov pc, lr
 
 ; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap:
 ; CHECK-ARMv6: ldrd  r2, r3, [r0]
 ; CHECK-ARMv6: rev r0, r3
 ; CHECK-ARMv6: rev r1, r2
 ; CHECK-ARMv6: bx  lr
   %tmp = bitcast i64* %arg to i8*
   %tmp1 = load i8, i8* %tmp, align 8

 }
 
 ; i8* p; // p[1] is 4 byte aligned
 ; (i32) p[4] | ((i32) p[3] << 8) | ((i32) p[2] << 16) | ((i32) p[1] << 24)
 define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_i8_nonzero_offset_bswap:
 ; CHECK: ldr r0, [r0, #1]
 ; CHECK-NEXT: mov r1, #65280
-; CHECK-NEXT: mov r2, #16711680
+; CHECK-NEXT: and r2, r0, #65280
 ; CHECK-NEXT: and r1, r1, r0, lsr #8
-; CHECK-NEXT: and r2, r2, r0, lsl #8
 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
-; CHECK-NEXT: orr r0, r2, r0, lsl #24
+; CHECK-NEXT: lsl r0, r0, #24
+; CHECK-NEXT: orr r0, r0, r2, lsl #8
 ; CHECK-NEXT: orr r0, r0, r1
 ; CHECK-NEXT: mov pc, lr
 
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset_bswap:
 ; CHECK-ARMv6: ldr r0, [r0, #1]
 ; CHECK-ARMv6-NEXT: rev r0, r0
 ; CHECK-ARMv6-NEXT: bx  lr
 

 }
 
 ; i8* p; // p[-4] is 4 byte aligned
 ; (i32) p[-1] | ((i32) p[-2] << 8) | ((i32) p[-3] << 16) | ((i32) p[-4] << 24)
 define i32 @load_i32_by_i8_neg_offset_bswap(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_i8_neg_offset_bswap:
 ; CHECK: ldr r0, [r0, #-4]
 ; CHECK-NEXT: mov r1, #65280
-; CHECK-NEXT: mov r2, #16711680
+; CHECK-NEXT: and r2, r0, #65280
 ; CHECK-NEXT: and r1, r1, r0, lsr #8
-; CHECK-NEXT: and r2, r2, r0, lsl #8
 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
-; CHECK-NEXT: orr r0, r2, r0, lsl #24
+; CHECK-NEXT: lsl r0, r0, #24
+; CHECK-NEXT: orr r0, r0, r2, lsl #8
 ; CHECK-NEXT: orr r0, r0, r1
 ; CHECK-NEXT: mov pc, lr
 
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset_bswap:
 ; CHECK-ARMv6: ldr r0, [r0, #-4]
 ; CHECK-ARMv6-NEXT: rev r0, r0
 ; CHECK-ARMv6-NEXT: bx  lr
 

 declare i16 @llvm.bswap.i16(i16)
 
 ; i16* p; // p is 4 byte aligned
 ; (i32) bswap(p[1]) | (i32) bswap(p[0] << 16)
 define i32 @load_i32_by_bswap_i16(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_bswap_i16:
 ; CHECK: ldr  r0, [r0]
 ; CHECK-NEXT: mov r1, #65280
-; CHECK-NEXT: mov r2, #16711680
+; CHECK-NEXT: and r2, r0, #65280
 ; CHECK-NEXT: and r1, r1, r0, lsr #8
-; CHECK-NEXT: and r2, r2, r0, lsl #8
 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
-; CHECK-NEXT: orr r0, r2, r0, lsl #24
+; CHECK-NEXT: lsl r0, r0, #24
+; CHECK-NEXT: orr r0, r0, r2, lsl #8
 ; CHECK-NEXT: orr r0, r0, r1
 ; CHECK-NEXT: mov pc, lr
 
 ; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16:
 ; CHECK-ARMv6: ldr r0, [r0]
 ; CHECK-ARMv6-NEXT: rev r0, r0
 ; CHECK-ARMv6-NEXT: bx  lr
 

test/CodeGen/ARM/unfold-shifts.ll

-; RUN: llc -mtriple armv6t2 %s -o - | FileCheck %s
-; RUN: llc -mtriple thumbv6t2 %s -o - | FileCheck %s --check-prefix=CHECK-T2
-; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
-; RUN: llc -mtriple thumbv7 %s -o - | FileCheck %s --check-prefix=CHECK-T2
-; RUN: llc -mtriple thumbv7m %s -o - | FileCheck %s --check-prefix=CHECK-T2
-; RUN: llc -mtriple thumbv8m.main %s -o - | FileCheck %s --check-prefix=CHECK-T2
+; RUN: llc -mtriple armv6t2 %s -o - | FileCheck %s --check-prefix=CHECK-A32 --check-prefix=CHECK
+; RUN: llc -mtriple thumbv6t2 %s -o - | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK
+; RUN: llc -mtriple armv7 %s -o - | FileCheck %s --check-prefix=CHECK-A32 --check-prefix=CHECK
+; RUN: llc -mtriple thumbv7 %s -o - | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK
+; RUN: llc -mtriple thumbv7m %s -o - | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK
+; RUN: llc -mtriple thumbv8m.main %s -o - | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK
 
 ; CHECK-LABEL: unfold1
 ; CHECK-NOT: mov
-; CHECK: orr r0, r0, #255
-; CHECK: add r0, r1, r0, lsl #1
-; CHECK-T2-NOT: mov
+; CHECK-A32: orr r0, r0, #255
+; CHECK-A32: add r0, r1, r0, lsl #1
 ; CHECK-T2: orr r0, r0, #255
 ; CHECK-T2: add.w r0, r1, r0, lsl #1
 define arm_aapcscc i32 @unfold1(i32 %a, i32 %b) {
 entry:
   %or = shl i32 %a, 1
   %shl = or i32 %or, 510
   %add = add nsw i32 %shl, %b
   ret i32 %add
 }
 
 ; CHECK-LABEL: unfold2
 ; CHECK-NOT: mov
-; CHECK: orr r0, r0, #4080
-; CHECK: sub r0, r1, r0, lsl #2
-; CHECK-T2-NOT: mov
+; CHECK-A32: orr r0, r0, #4080
+; CHECK-A32: sub r0, r1, r0, lsl #2
 ; CHECK-T2: orr r0, r0, #4080
 ; CHECK-T2: sub.w r0, r1, r0, lsl #2
 define arm_aapcscc i32 @unfold2(i32 %a, i32 %b) {
 entry:
   %or = shl i32 %a, 2
   %shl = or i32 %or, 16320
   %sub = sub nsw i32 %b, %shl
   ret i32 %sub
 }
 
 ; CHECK-LABEL: unfold3
 ; CHECK-NOT: mov
-; CHECK: orr r0, r0, #65280
-; CHECK: and r0, r1, r0, lsl #4
-; CHECK-T2-NOT: mov
+; CHECK-A32: orr r0, r0, #65280
+; CHECK-A32: and r0, r1, r0, lsl #4
 ; CHECK-T2: orr r0, r0, #65280
 ; CHECK-T2: and.w r0, r1, r0, lsl #4
 define arm_aapcscc i32 @unfold3(i32 %a, i32 %b) {
 entry:
   %or = shl i32 %a, 4
   %shl = or i32 %or, 1044480
   %and = and i32 %shl, %b
   ret i32 %and
 }
 
 ; CHECK-LABEL: unfold4
 ; CHECK-NOT: mov
-; CHECK: orr r0, r0, #1044480
-; CHECK: eor r0, r1, r0, lsl #5
-; CHECK-T2-NOT: mov
+; CHECK-A32: orr r0, r0, #1044480
+; CHECK-A32: eor r0, r1, r0, lsl #5
 ; CHECK-T2: orr r0, r0, #1044480
 ; CHECK-T2: eor.w r0, r1, r0, lsl #5
 define arm_aapcscc i32 @unfold4(i32 %a, i32 %b) {
 entry:
   %or = shl i32 %a, 5
   %shl = or i32 %or, 33423360
   %xor = xor i32 %shl, %b
   ret i32 %xor
 }
 
 ; CHECK-LABEL: unfold5
 ; CHECK-NOT: mov
-; CHECK: add r0, r0, #496
-; CHECK: orr r0, r1, r0, lsl #6
+; CHECK-A32: add r0, r0, #496
+; CHECK-A32: orr r0, r1, r0, lsl #6
 ; CHECK-T2: add.w r0, r0, #496
 ; CHECK-T2: orr.w r0, r1, r0, lsl #6
 define arm_aapcscc i32 @unfold5(i32 %a, i32 %b) {
 entry:
   %add = shl i32 %a, 6
   %shl = add i32 %add, 31744
   %or = or i32 %shl, %b
   ret i32 %or
 }
 
 ; CHECK-LABEL: unfold6
 ; CHECK-NOT: mov
-; CHECK: add r0, r0, #7936
-; CHECK: and r0, r1, r0, lsl #8
-; CHECK-T2-NOT: mov
+; CHECK-A32: add r0, r0, #7936
+; CHECK-A32: and r0, r1, r0, lsl #8
 ; CHECK-T2: add.w r0, r0, #7936
 ; CHECK-T2: and.w r0, r1, r0, lsl #8
 define arm_aapcscc i32 @unfold6(i32 %a, i32 %b) {
 entry:
   %add = shl i32 %a, 8
   %shl = add i32 %add, 2031616
   %and = and i32 %shl, %b
   ret i32 %and
 }
 
 ; CHECK-LABEL: unfold7
 ; CHECK-NOT: mov
-; CHECK: and r0, r0, #256
-; CHECK: add r0, r1, r0, lsl #1
-; CHECK-T2-NOT: mov
+; CHECK-A32: and r0, r0, #256
+; CHECK-A32: add r0, r1, r0, lsl #1
 ; CHECK-T2: and r0, r0, #256
 ; CHECK-T2: add.w r0, r1, r0, lsl #1
 define arm_aapcscc i32 @unfold7(i32 %a, i32 %b) {
 entry:
   %shl = shl i32 %a, 1
   %and = and i32 %shl, 512
   %add = add nsw i32 %and, %b
   ret i32 %add
 }
 
 ; CHECK-LABEL: unfold8
 ; CHECK-NOT: mov
-; CHECK: add r0, r0, #126976
-; CHECK: eor r0, r1, r0, lsl #9
-; CHECK-T2-NOT: mov
+; CHECK-A32: add r0, r0, #126976
+; CHECK-A32: eor r0, r1, r0, lsl #9
 ; CHECK-T2: add.w r0, r0, #126976
 ; CHECK-T2: eor.w r0, r1, r0, lsl #9
 define arm_aapcscc i32 @unfold8(i32 %a, i32 %b) {
 entry:
   %add = shl i32 %a, 9
   %shl = add i32 %add, 65011712
   %xor = xor i32 %shl, %b
   ret i32 %xor
 }
 
 ; CHECK-LABEL: unfold9
 ; CHECK-NOT: mov
-; CHECK: eor r0, r0, #255
-; CHECK: add r0, r1, r0, lsl #1
-; CHECK-T2-NOT: mov
+; CHECK-A32: eor r0, r0, #255
+; CHECK-A32: add r0, r1, r0, lsl #1
 ; CHECK-T2: eor r0, r0, #255
 ; CHECK-T2: add.w r0, r1, r0, lsl #1
 define arm_aapcscc i32 @unfold9(i32 %a, i32 %b) {
 entry:
   %shl = shl i32 %a, 1
   %xor = xor i32 %shl, 510
   %add = add nsw i32 %xor, %b
   ret i32 %add
 }
 
 ; CHECK-LABEL: unfold10
 ; CHECK-NOT: mov r2
-; CHECK: orr r2, r0, #4080
-; CHECK: cmp r1, r2, lsl #10
-; CHECK-T2-NOT: mov.w r2
+; CHECK-A32: orr r2, r0, #4080
+; CHECK-A32: cmp r1, r2, lsl #10
 ; CHECK-T2: orr r2, r0, #4080
 ; CHECK-T2: cmp.w r1, r2, lsl #10
 define arm_aapcscc i32 @unfold10(i32 %a, i32 %b) {
 entry:
   %or = shl i32 %a, 10
   %shl = or i32 %or, 4177920
   %cmp = icmp sgt i32 %shl, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 ; CHECK-LABEL: unfold11
 ; CHECK-NOT: mov r2
-; CHECK: add r2, r0, #7936
-; CHECK: cmp r1, r2, lsl #11
-; CHECK-T2-NOT: mov.w r2
+; CHECK-A32: add r2, r0, #7936
+; CHECK-A32: cmp r1, r2, lsl #11
 ; CHECK-T2: add.w r2, r0, #7936
 ; CHECK-T2: cmp.w r1, r2, lsl #11
 define arm_aapcscc i32 @unfold11(i32 %a, i32 %b) {
 entry:
   %add = shl i32 %a, 11
   %shl = add i32 %add, 16252928
   %cmp = icmp sgt i32 %shl, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
+; CHECK-LABEL: using_shl
+; CHECK-NOT: mov
+; CHECK-A32: orr r0, r0, #255
+; CHECK-A32: lsl r0, r0, #1
+; CHECK-A32: add r0, r0, r1, lsl r2
+; CHECK-T2: orr r0, r0, #255
+; CHECK-T2: lsls r1, r2
+; CHECK-T2: add.w r0, r1, r0, lsl #1
+define arm_aapcscc i32 @using_shl(i32 %a, i32 %b, i32 %c) {
+entry:
+  %lsl0 = shl i32 %a, 1
+  %lsl1 = shl i32 %b, %c
+  %or = or i32 %lsl0, 510
+  %add = add nsw i32 %or, %lsl1
+  ret i32 %add
+}
+
+; CHECK-LABEL: using_srl
+; CHECK-NOT: mov
+; CHECK-A32: add r0, r0, #255
+; CHECK-A32: lsl r0, r0, #1
+; CHECK-A32: orr r0, r0, r1, lsr r2
+; CHECK-T2: adds r0, #255
+; CHECK-T2: lsrs r1, r2
+; CHECK-T2: orr.w r0, r1, r0, lsl #1
+define arm_aapcscc i32 @using_srl(i32 %a, i32 %b, i32 %c) {
+entry:
+  %lsl = shl i32 %a, 1
+  %lsr = lshr i32 %b, %c
+  %add = add nsw i32 %lsl, 510
+  %or = or i32 %add, %lsr
+  ret i32 %or
+}
+
+; CHECK-LABEL: using_sra
+; CHECK-NOT: mov
+; CHECK-A32: orr r0, r0, #255
+; CHECK-A32: lsl r0, r0, #1
+; CHECK-A32: and r0, r0, r1, asr r2
+; CHECK-T2: orr r0, r0, #255
+; CHECK-T2: asrs r1, r2
+; CHECK-T2: and.w r0, r1, r0, lsl #1
+define arm_aapcscc i32 @using_sra(i32 %a, i32 %b, i32 %c) {
+entry:
+  %lsl = shl i32 %a, 1
+  %asr = ashr i32 %b, %c
+  %or = or i32 %lsl, 510
+  %and = and i32 %or, %asr
+  ret i32 %and
+}