Preprocessor: improve ACLE 6.4 support

[compnerd]

Summary

This improves conformance with ACLE 6.4.1. Define additional macros that
indicate support for the ARM and Thumb instruction set architecture. This
includes the following set of macros:

__ARM_ARCH
__ARM_ARCH_ISA_ARM
__ARM_ARCH_ISA_THUMB
__ARM_32BIT_STATE

These help identify the environment that the code is intended to execute on.

[t.p.northover]

Hi Saleem,

I think this looks fine, but while you're in the area it looks like there's a bug in how __ARM_ARCH_PROFILE is defined:

test/Preprocessor/arm-acle-6.4.c

7

Just noticed this one, and I think it might be a misinterpretation of the ACLE. I would expect this to be the character value 'M' rather than some isolated token.

A quick GCC test suggests this is how they do it ("#define __ARM_ARCH_PROFILE 65" for Cortex-A15, which is also dodgy in C++ mode, but less so).

[rengolin]

With Tim's comment fixed, LGTM.

test/Preprocessor/arm-acle-6.4.c

7

I'd prefer a quoted char.

[t.p.northover]

A quick GCC test suggests this is how they do it ("#define __ARM_ARCH_PROFILE 65" for Cortex-A15, which is also dodgy in C++ mode, but less so).

I'd prefer a quoted char.

Me too. From the ACLE wording, I'd expect sizeof(__ARM_ARCH_PROFILE)

1 in C++ mode.

Cheers.

Tim.

[compnerd]

Actually, the current handling of 6.4.2 is incorrect. It is *supposed* to be a quoted char. If you look at the example provided in 6.4.10, you will notice that this:

#if __ARCH_ARM_PROFILE == 'R'

Fixed that as well. That was a great catch!

[compnerd]

Committed as SVN r210991.

lib/Basic/Targets.cpp

   bool setCPU(const std::string &Name) override {
     if (!getCPUDefineSuffix(Name))
       return false;
 
     CPU = Name;
     return true;
   }
   bool setFPMath(StringRef Name) override;
+  bool supportsThumb(StringRef ArchName, StringRef CPUArch,
+                     unsigned CPUArchVer) const {
+    return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
+           (CPUArch.find('M') != StringRef::npos);
+  }
+  bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
+                      unsigned CPUArchVer) const {
+    // We check both CPUArchVer and ArchName because when only triple is
+    // specified, the default CPU is arm1136j-s.
+    return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
+           ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
+  }
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override {
     // Target identification.
     Builder.defineMacro("__arm");
     Builder.defineMacro("__arm__");
 
     // Target properties.
     Builder.defineMacro("__REGISTER_PREFIX__", "");
 
     StringRef CPUArch = getCPUDefineSuffix(CPU);
     unsigned int CPUArchVer;
     if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) {
       llvm_unreachable("Invalid char for architecture version number");
     }
     Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
-    Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
+
+    // ACLE 6.4.1 ARM/Thumb instruction set architecture
     StringRef CPUProfile = getCPUProfile(CPU);
+    StringRef ArchName = getTriple().getArchName();
+
+    // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
+    Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
+
+    // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
+    // is not defined for the M-profile.
+    // NOTE that the deffault profile is assumed to be 'A'
+    if (CPUProfile.empty() || CPUProfile != "M")
+      Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
+
+    // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
+    // Thumb ISA (including v6-M).  It is set to 2 if the core supports the
+    // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
+    if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
+      Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
+    else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
+      Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
+
+    // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
+    // instruction set such as ARM or Thumb.
+    Builder.defineMacro("__ARM_32BIT_STATE", "1");
+
+    // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
+
+    // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
     if (!CPUProfile.empty())
       Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
 
     // Subtarget options.
 
     // FIXME: It's more complicated than this and we don't really support
     // interworking.
     // Windows on ARM does not "support" interworking

       Builder.defineMacro("__SOFTFP__");
 
     if (CPU == "xscale")
       Builder.defineMacro("__XSCALE__");
 
     if (IsThumb) {
       Builder.defineMacro("__THUMBEL__");
       Builder.defineMacro("__thumb__");
-      // We check both CPUArchVer and ArchName because when only triple is
-      // specified, the default CPU is arm1136j-s.
-      StringRef ArchName = getTriple().getArchName();
-      if (CPUArch == "6T2" || CPUArchVer >= 7 || ArchName.endswith("v6t2") ||
-          ArchName.endswith("v7") || ArchName.endswith("v8"))
+      if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
         Builder.defineMacro("__thumb2__");
     }
     if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
       Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
 
     // Note, this is always on in gcc, even though it doesn't make sense.
     Builder.defineMacro("__APCS_32__");
 

test/Preprocessor/arm-acle-6.4.c

+// RUN: %clang -target arm-eabi -mcpu=cortex-m0 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-CORTEX-M0
+
+// CHECK-CORTEX-M0: __ARM_32BIT_STATE 1
+// CHECK-CORTEX-M0: __ARM_ARCH 6
+// CHECK-CORTEX-M0-NOT: __ARM_ARCH_ISA_ARM
+// CHECK-CORTEX-M0: __ARM_ARCH_ISA_THUMB 1
+// CHECK-CORTEX-M0: __ARM_ARCH_PROFILE M
+
+// RUN: %clang -target arm-eabi -mcpu=arm810 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-ARM810
+
+// CHECK-ARM810: __ARM_32BIT_STATE 1
+// CHECK-ARM810: __ARM_ARCH 4
+// CHECK-ARM810: __ARM_ARCH_ISA_ARM 1
+// CHECK-ARM810-NOT: __ARM_ARCH_ISA_THUMB
+// CHECK-ARM810-NOT: __ARM_ARCH_PROFILE
+
+// RUN: %clang -target arm-eabi -mcpu=arm7tdmi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-ARM7TDMI
+
+// CHECK-ARM7TDMI: __ARM_32BIT_STATE 1
+// CHECK-ARM7TDMI: __ARM_ARCH 4
+// CHECK-ARM7TDMI: __ARM_ARCH_ISA_ARM 1
+// CHECK-ARM7TDMI: __ARM_ARCH_ISA_THUMB 1
+// CHECK-ARM7TDMI-NOT: __ARM_ARCH_PROFILE
+
+// RUN: %clang -target arm-eabi -mcpu=cortex-a7 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-CORTEX-A7
+
+// CHECK-CORTEX-A7: __ARM_32BIT_STATE 1
+// CHECK-CORTEX-A7: __ARM_ARCH 7
+// CHECK-CORTEX-A7: __ARM_ARCH_ISA_ARM 1
+// CHECK-CORTEX-A7: __ARM_ARCH_ISA_THUMB 2
+// CHECK-CORTEX-A7: __ARM_ARCH_PROFILE A
+
+// RUN: %clang -target arm-eabi -mcpu=cortex-r4 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-CORTEX-R4
+
+// CHECK-CORTEX-R4: __ARM_32BIT_STATE 1
+// CHECK-CORTEX-R4: __ARM_ARCH 7
+// CHECK-CORTEX-R4: __ARM_ARCH_ISA_ARM 1
+// CHECK-CORTEX-R4: __ARM_ARCH_ISA_THUMB 2
+// CHECK-CORTEX-R4: __ARM_ARCH_PROFILE R
+