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Differential D4120

[mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6
ClosedPublic

Authored by dsanders on Jun 12 2014, 5:53 AM.

Details

Reviewers
jkolek
vmedic
zoran.jovanovic
Commits
rG00463119a5f9: [mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6
rL211019: [mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6
Summary

There is no change to the restrictions, just the result register is stored
once in the encoding rather than twice. The rt field is zero in
MIPS32r6/MIPS64r6.

Depends on D4119

Diff Detail

Event Timeline

dsanders updated this revision to Diff 10357.Jun 12 2014, 5:53 AM
dsanders retitled this revision from to [mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6.
dsanders updated this object.
dsanders edited the test plan for this revision. (Show Details)
dsanders added reviewers: vmedic, zoran.jovanovic, jkolek.
dsanders added a parent revision: D4119: [mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6..
vmedic accepted this revision.Jun 13 2014, 5:34 AM
vmedic edited edge metadata.

LGTM

This revision is now accepted and ready to land.Jun 13 2014, 5:34 AM
dsanders closed this revision.Jun 16 2014, 6:26 AM

Revision Contents

PathSize
lib/
Target/
Mips/
18 lines
25 lines
4 lines
6 lines
9 lines
5 lines
test/
CodeGen/
Mips/
90 lines
66 lines
MC/
Disassembler/
Mips/
2 lines
4 lines
Mips/
mips32/
4 lines
mips32r2/
4 lines
mips32r6/
2 lines
mips64/
8 lines
mips64r2/
8 lines
mips64r6/
4 lines

Diff 10357

lib/Target/Mips/Mips32r6InstrFormats.td

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def OPCODE6_CACHE : OPCODE6<0b100101>; def OPCODE6_CACHE : OPCODE6<0b100101>;
def OPCODE6_PREF : OPCODE6<0b110101>; def OPCODE6_PREF : OPCODE6<0b110101>;
// The next four constants are unnamed in the spec. These names are taken from // The next four constants are unnamed in the spec. These names are taken from
// the OPGROUP names they are used with. // the OPGROUP names they are used with.
def OPCODE6_LL : OPCODE6<0b110110>; def OPCODE6_LL : OPCODE6<0b110110>;
def OPCODE6_LLD : OPCODE6<0b110111>; def OPCODE6_LLD : OPCODE6<0b110111>;
def OPCODE6_SC : OPCODE6<0b100110>; def OPCODE6_SC : OPCODE6<0b100110>;
def OPCODE6_SCD : OPCODE6<0b100111>; def OPCODE6_SCD : OPCODE6<0b100111>;
def OPCODE6_CLO : OPCODE6<0b010001>;
def OPCODE6_CLZ : OPCODE6<0b010000>;
def OPCODE6_DCLO : OPCODE6<0b010011>;
def OPCODE6_DCLZ : OPCODE6<0b010010>;
class FIELD_FMT<bits<5> Val> { class FIELD_FMT<bits<5> Val> {
bits<5> Value = Val; bits<5> Value = Val;
} }
def FIELD_FMT_S : FIELD_FMT<0b10000>; def FIELD_FMT_S : FIELD_FMT<0b10000>;
def FIELD_FMT_D : FIELD_FMT<0b10001>; def FIELD_FMT_D : FIELD_FMT<0b10001>;
class FIELD_CMP_COND<bits<5> Val> { class FIELD_CMP_COND<bits<5> Val> {
▲ Show 20 Lines • Show All 186 Lines • ▼ Show 20 Linesclass SPECIAL3_MEM_FM<OPCODE6 Operation> : MipsR6Inst {
let Inst{31-26} = OPGROUP_SPECIAL3.Value; let Inst{31-26} = OPGROUP_SPECIAL3.Value;
let Inst{25-21} = base; let Inst{25-21} = base;
let Inst{20-16} = hint; let Inst{20-16} = hint;
let Inst{15-7} = offset; let Inst{15-7} = offset;
let Inst{6} = 0; let Inst{6} = 0;
let Inst{5-0} = Operation.Value; let Inst{5-0} = Operation.Value;
} }
class SPECIAL_2R_FM<OPCODE6 Operation> : MipsR6Inst {
bits<5> rd;
bits<5> rs;
bits<32> Inst;
let Inst{31-26} = OPGROUP_SPECIAL.Value;
let Inst{25-21} = rs;
let Inst{20-16} = 0b00000;
let Inst{15-11} = rd;
let Inst{10-6} = 0b00001;
let Inst{5-0} = Operation.Value;
}
class SPECIAL_3R_FM<bits<5> mulop, bits<6> funct> : MipsR6Inst { class SPECIAL_3R_FM<bits<5> mulop, bits<6> funct> : MipsR6Inst {
bits<5> rd; bits<5> rd;
bits<5> rs; bits<5> rs;
bits<5> rt; bits<5> rt;
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = OPGROUP_SPECIAL.Value; let Inst{31-26} = OPGROUP_SPECIAL.Value;
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lib/Target/Mips/Mips32r6InstrInfo.td

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// This file describes Mips32r6 instructions. // This file describes Mips32r6 instructions.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
include "Mips32r6InstrFormats.td" include "Mips32r6InstrFormats.td"
// Notes about removals/changes from MIPS32r6: // Notes about removals/changes from MIPS32r6:
// Unclear: ssnop // Unclear: ssnop
// Reencoded: clo, clz
// Reencoded: jr -> jalr // Reencoded: jr -> jalr
// Reencoded: jr.hb -> jalr.hb // Reencoded: jr.hb -> jalr.hb
// Reencoded: sdbbp // Reencoded: sdbbp
def brtarget21 : Operand<OtherVT> { def brtarget21 : Operand<OtherVT> {
let EncoderMethod = "getBranchTarget21OpValue"; let EncoderMethod = "getBranchTarget21OpValue";
let OperandType = "OPERAND_PCREL"; let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTarget21"; let DecoderMethod = "DecodeBranchTarget21";
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class LDC2_R6_ENC : COP2LDST_FM<OPCODE5_LDC2>; class LDC2_R6_ENC : COP2LDST_FM<OPCODE5_LDC2>;
class LWC2_R6_ENC : COP2LDST_FM<OPCODE5_LWC2>; class LWC2_R6_ENC : COP2LDST_FM<OPCODE5_LWC2>;
class SDC2_R6_ENC : COP2LDST_FM<OPCODE5_SDC2>; class SDC2_R6_ENC : COP2LDST_FM<OPCODE5_SDC2>;
class SWC2_R6_ENC : COP2LDST_FM<OPCODE5_SWC2>; class SWC2_R6_ENC : COP2LDST_FM<OPCODE5_SWC2>;
class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>; class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>;
class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>; class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>;
class CLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLO>;
class CLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLZ>;
class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
RegisterOperand FGROpnd, RegisterOperand FGROpnd,
SDPatternOperator Op = null_frag> { SDPatternOperator Op = null_frag> {
dag OutOperandList = (outs FGRCCOpnd:$fd); dag OutOperandList = (outs FGRCCOpnd:$fd);
dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft"); string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))]; list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
} }
▲ Show 20 Lines • Show All 408 Lines • ▼ Show 20 Linesclass SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = []; list<dag> Pattern = [];
bit mayStore = 1; bit mayStore = 1;
string Constraints = "$rt = $dst"; string Constraints = "$rt = $dst";
} }
class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd>; class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd>;
class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
}
class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> :
CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> {
list<dag> Pattern = [(set GPROpnd:$rd, (ctlz (not GPROpnd:$rs)))];
}
class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> :
CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> {
list<dag> Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))];
}
class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd>;
class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction Definitions // Instruction Definitions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6; def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6; def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
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def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6; def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6; def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6; def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6; def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6; def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
def CACHE_R6 : CACHE_ENC, CACHE_DESC, ISA_MIPS32R6; def CACHE_R6 : CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6; def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6; def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
def CLO_R6 : CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
def CLZ_R6 : CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>; defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>; defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6; def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6; def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6; def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6; def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6; def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6; def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
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lib/Target/Mips/Mips64InstrInfo.td

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/// Sign Ext In Register Instructions. /// Sign Ext In Register Instructions.
def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>, def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>,
ISA_MIPS32R2; ISA_MIPS32R2;
def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>, def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
ISA_MIPS32R2; ISA_MIPS32R2;
} }
/// Count Leading /// Count Leading
def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64; def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64; def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
/// Double Word Swap Bytes/HalfWords /// Double Word Swap Bytes/HalfWords
def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2; def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2; def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2;
def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>; def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
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lib/Target/Mips/Mips64r6InstrInfo.td

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// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class DALIGN_ENC : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>; class DALIGN_ENC : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>;
class DAUI_ENC : DAUI_FM; class DAUI_ENC : DAUI_FM;
class DAHI_ENC : REGIMM_FM<OPCODE5_DAHI>; class DAHI_ENC : REGIMM_FM<OPCODE5_DAHI>;
class DATI_ENC : REGIMM_FM<OPCODE5_DATI>; class DATI_ENC : REGIMM_FM<OPCODE5_DATI>;
class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>; class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>;
class DCLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLO>;
class DCLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLZ>;
class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>; class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>;
class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>; class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>;
class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>; class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>;
class DMODU_ENC : SPECIAL_3R_FM<0b00011, 0b011111>; class DMODU_ENC : SPECIAL_3R_FM<0b00011, 0b011111>;
class DMUH_ENC : SPECIAL_3R_FM<0b00011, 0b111000>; class DMUH_ENC : SPECIAL_3R_FM<0b00011, 0b111000>;
class DMUHU_ENC : SPECIAL_3R_FM<0b00011, 0b111001>; class DMUHU_ENC : SPECIAL_3R_FM<0b00011, 0b111001>;
class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b111000>; class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b111000>;
class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b111001>; class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b111001>;
Show All 14 Linesclass AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
string Constraints = "$rs = $rt"; string Constraints = "$rs = $rt";
} }
class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>; class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
class DAHI_DESC : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd>; class DAHI_DESC : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd>;
class DATI_DESC : AHI_ATI_DESC_BASE<"dati", GPR64Opnd>; class DATI_DESC : AHI_ATI_DESC_BASE<"dati", GPR64Opnd>;
class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd>; class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd>;
class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd>; class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd>;
class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd>;
class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd>;
class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, sdiv>; class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, sdiv>;
class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, udiv>; class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, srem>; class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, srem>;
class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, urem>; class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, urem>;
class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, mulhs>; class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, mulhs>;
class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, mulhu>; class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, mulhu>;
class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, mul>; class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, mul>;
class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd>; class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd>;
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// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6; def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6; def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6; def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6; def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6; def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6; def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6; def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
// def DLSA; // See MSA // def DLSA; // See MSA
def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6; def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6; def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6; def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6; def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6; def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
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lib/Target/Mips/MipsInstrInfo.td

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class ISA_MIPS32_NOT_32R6_64R6 { class ISA_MIPS32_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6]; list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
} }
class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; } class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
class ISA_MIPS32R2_NOT_32R6_64R6 { class ISA_MIPS32R2_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6]; list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
} }
class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; } class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
class ISA_MIPS64_NOT_64R6 {
list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
}
class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; } class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; } class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; } class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
// The portions of MIPS-III that were also added to MIPS32 // The portions of MIPS-III that were also added to MIPS32
class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; } class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
// The portions of MIPS-III that were also added to MIPS32 but were removed in // The portions of MIPS-III that were also added to MIPS32 but were removed in
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/// Sign Ext In Register Instructions. /// Sign Ext In Register Instructions.
def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
SEB_FM<0x10, 0x20>, ISA_MIPS32R2; SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
SEB_FM<0x18, 0x20>, ISA_MIPS32R2; SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
/// Count Leading /// Count Leading
def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, ISA_MIPS32; def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, ISA_MIPS32; ISA_MIPS32_NOT_32R6_64R6;
def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
ISA_MIPS32_NOT_32R6_64R6;
/// Word Swap Bytes Within Halfwords /// Word Swap Bytes Within Halfwords
def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2; def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
/// No operation. /// No operation.
def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
// FrameIndexes are legalized when they are operands from load/store // FrameIndexes are legalized when they are operands from load/store
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lib/Target/Mips/MipsSubtarget.h

Show First 20 Lines • Show All 152 Lines • ▼ Show 20 Linespublic:
/// ParseSubtargetFeatures - Parses features string setting specified /// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen. /// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS); void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool hasMips2() const { return MipsArchVersion >= Mips2; } bool hasMips2() const { return MipsArchVersion >= Mips2; }
bool hasMips3() const { return MipsArchVersion >= Mips3; } bool hasMips3() const { return MipsArchVersion >= Mips3; }
bool hasMips4_32() const { return HasMips4_32; } bool hasMips4_32() const { return HasMips4_32; }
bool hasMips4_32r2() const { return HasMips4_32r2; } bool hasMips4_32r2() const { return HasMips4_32r2; }
bool hasMips32() const { return MipsArchVersion >= Mips32; } bool hasMips32() const {
return MipsArchVersion >= Mips32 && MipsArchVersion != Mips3 &&
MipsArchVersion != Mips4 && MipsArchVersion != Mips5;
}
bool hasMips32r2() const { bool hasMips32r2() const {
return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 || return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 ||
MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6; MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
} }
bool hasMips32r6() const { bool hasMips32r6() const {
return MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r6; return MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r6;
} }
bool hasMips64() const { return MipsArchVersion >= Mips64; } bool hasMips64() const { return MipsArchVersion >= Mips64; }
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test/CodeGen/Mips/countleading.ll

  • This file was added.
; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s
; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s
; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R6 -check-prefix=MIPS32-GT-R1 %s
; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
; R!N: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
; Prefixes:
; ALL - All
; MIPS32-GT-R1 - MIPS64r1 and above (does not include MIPS64's)
; MIPS64-GT-R1 - MIPS64r1 and above
define i32 @ctlz_i32(i32 %X) nounwind readnone {
entry:
; ALL-LABEL: ctlz_i32:
; MIPS4-NOT: clz
; MIPS32-GT-R1: clz $2, $4
; MIPS64-GT-R1: clz $2, $4
%tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true)
ret i32 %tmp1
}
declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
define i32 @ctlo_i32(i32 %X) nounwind readnone {
entry:
; ALL-LABEL: ctlo_i32:
; MIPS4-NOT: clo
; MIPS32-GT-R1: clo $2, $4
; MIPS64-GT-R1: clo $2, $4
%neg = xor i32 %X, -1
%tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true)
ret i32 %tmp1
}
define i64 @ctlz_i64(i64 %X) nounwind readnone {
entry:
; ALL-LABEL: ctlz_i64:
; MIPS4-NOT: dclz
; MIPS32-GT-R1-DAG: clz $[[R0:[0-9]+]], $4
; MIPS32-GT-R1-DAG: clz $[[R1:[0-9]+]], $5
; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32
; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $5
; MIPS32-R6-DAG: selnez $[[R5:[0-9]+]], $[[R2]], $5
; MIPS32-R6-DAG: seleqz $[[R6:[0-9]+]], $[[R1]], $5
; MIPS32-R6-DAG: or $2, $[[R5]], $[[R6]]
; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
; MIPS64-GT-R1: dclz $2, $4
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
ret i64 %tmp1
}
declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
define i64 @ctlo_i64(i64 %X) nounwind readnone {
entry:
; ALL-LABEL: ctlo_i64:
; MIPS4-NOT: dclo
; MIPS32-GT-R1-DAG: clo $[[R0:[0-9]+]], $4
; MIPS32-GT-R1-DAG: clo $[[R1:[0-9]+]], $5
; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32
; MIPS32-GT-R1-DAG: addiu $[[R3:[0-9]+]], $zero, -1
; MIPS32-GT-R1-DAG: xor $[[R4:[0-9]+]], $5, $[[R3]]
; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $[[R4]]
; MIPS32-R6-DAG: selnez $[[R5:[0-9]+]], $[[R1]], $[[R4]]
; MIPS32-R6-DAG: seleqz $[[R6:[0-9]+]], $[[R2]], $[[R4]]
; MIPS32-R6-DAG: or $2, $[[R5]], $[[R6]]
; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
; MIPS64-GT-R1: dclo $2, $4
%neg = xor i64 %X, -1
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
ret i64 %tmp1
}

test/CodeGen/Mips/mips64countleading.ll

  • This file was deleted.
; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS4 %s
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS64 %s
define i64 @t1(i64 %X) nounwind readnone {
entry:
; CHECK-LABEL: t1:
; MIPS4-NOT: dclz
; MIPS64: dclz
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
ret i64 %tmp1
}
declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
define i64 @t3(i64 %X) nounwind readnone {
entry:
; CHECK-LABEL: t3:
; MIPS4-NOT: dclo
; MIPS64: dclo
%neg = xor i64 %X, -1
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
ret i64 %tmp1
}

test/CodeGen/Mips/mips64instrs.ll

; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s ; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 -check-prefix=ACCMULDIV %s
; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 %s ; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=ACCMULDIV %s
; RUN: llc -march=mips64el -mcpu=mips64r2 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=ACCMULDIV %s
; RUN: llc -march=mips64el -mcpu=mips64r6 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=GPRMULDIV %s
@gll0 = common global i64 0, align 8 @gll0 = common global i64 0, align 8
@gll1 = common global i64 0, align 8 @gll1 = common global i64 0, align 8
define i64 @f0(i64 %a0, i64 %a1) nounwind readnone { define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
entry: entry:
; ALL-LABEL: f0: ; ALL-LABEL: f0:
; ALL: daddu $2, ${{[45]}}, ${{[45]}} ; ALL: daddu $2, ${{[45]}}, ${{[45]}}
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; ALL: xori $2, $4, 20 ; ALL: xori $2, $4, 20
%xor = xor i64 %a0, 20 %xor = xor i64 %a0, 20
ret i64 %xor ret i64 %xor
} }
define i64 @f12(i64 %a, i64 %b) nounwind readnone { define i64 @f12(i64 %a, i64 %b) nounwind readnone {
entry: entry:
; ALL-LABEL: f12: ; ALL-LABEL: f12:
; ALL: mult ${{[45]}}, ${{[45]}}
; ACCMULDIV: mult ${{[45]}}, ${{[45]}}
; GPRMULDIV: dmul $2, ${{[45]}}, ${{[45]}}
%mul = mul nsw i64 %b, %a %mul = mul nsw i64 %b, %a
ret i64 %mul ret i64 %mul
} }
define i64 @f13(i64 %a, i64 %b) nounwind readnone { define i64 @f13(i64 %a, i64 %b) nounwind readnone {
entry: entry:
; ALL-LABEL: f13: ; ALL-LABEL: f13:
; ALL: mult ${{[45]}}, ${{[45]}}
; ACCMULDIV: mult ${{[45]}}, ${{[45]}}
; GPRMULDIV: dmul $2, ${{[45]}}, ${{[45]}}
%mul = mul i64 %b, %a %mul = mul i64 %b, %a
ret i64 %mul ret i64 %mul
} }
define i64 @f14(i64 %a, i64 %b) nounwind readnone { define i64 @f14(i64 %a, i64 %b) nounwind readnone {
entry: entry:
; ALL-LABEL: f14: ; ALL-LABEL: f14:
; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)( ; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)(
; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)( ; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)(
; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]]) ; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]])
; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]]) ; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]])
; ALL: ddiv $zero, $[[T0]], $[[T1]]
; ALL: teq $[[T1]], $zero, 7 ; ACCMULDIV: ddiv $zero, $[[T0]], $[[T1]]
; ALL: mflo $2 ; ACCMULDIV: teq $[[T1]], $zero, 7
; ACCMULDIV: mflo $2
; GPRMULDIV: ddiv $2, $[[T0]], $[[T1]]
; GPRMULDIV: teq $[[T1]], $zero, 7
%0 = load i64* @gll0, align 8 %0 = load i64* @gll0, align 8
%1 = load i64* @gll1, align 8 %1 = load i64* @gll1, align 8
%div = sdiv i64 %0, %1 %div = sdiv i64 %0, %1
ret i64 %div ret i64 %div
} }
define i64 @f15() nounwind readnone { define i64 @f15() nounwind readnone {
entry: entry:
; ALL-LABEL: f15: ; ALL-LABEL: f15:
; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)( ; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)(
; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)( ; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)(
; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]]) ; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]])
; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]]) ; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]])
; ALL: ddivu $zero, $[[T0]], $[[T1]]
; ALL: teq $[[T1]], $zero, 7 ; ACCMULDIV: ddivu $zero, $[[T0]], $[[T1]]
; ALL: mflo $2 ; ACCMULDIV: teq $[[T1]], $zero, 7
; ACCMULDIV: mflo $2
; GPRMULDIV: ddivu $2, $[[T0]], $[[T1]]
; GPRMULDIV: teq $[[T1]], $zero, 7
%0 = load i64* @gll0, align 8 %0 = load i64* @gll0, align 8
%1 = load i64* @gll1, align 8 %1 = load i64* @gll1, align 8
%div = udiv i64 %0, %1 %div = udiv i64 %0, %1
ret i64 %div ret i64 %div
} }
define i64 @f16(i64 %a, i64 %b) nounwind readnone { define i64 @f16(i64 %a, i64 %b) nounwind readnone {
entry: entry:
; ALL-LABEL: f16: ; ALL-LABEL: f16:
; ALL: ddiv $zero, $4, $5
; ALL: teq $5, $zero, 7 ; ACCMULDIV: ddiv $zero, $4, $5
; ALL: mfhi $2 ; ACCMULDIV: teq $5, $zero, 7
; ACCMULDIV: mfhi $2
; GPRMULDIV: dmod $2, $4, $5
; GPRMULDIV: teq $5, $zero, 7
%rem = srem i64 %a, %b %rem = srem i64 %a, %b
ret i64 %rem ret i64 %rem
} }
define i64 @f17(i64 %a, i64 %b) nounwind readnone { define i64 @f17(i64 %a, i64 %b) nounwind readnone {
entry: entry:
; ALL-LABEL: f17: ; ALL-LABEL: f17:
; ALL: ddivu $zero, $4, $5
; ALL: teq $5, $zero, 7 ; ACCMULDIV: ddivu $zero, $4, $5
; ALL: mfhi $2 ; ACCMULDIV: teq $5, $zero, 7
; ACCMULDIV: mfhi $2
; GPRMULDIV: dmodu $2, $4, $5
; GPRMULDIV: teq $5, $zero, 7
%rem = urem i64 %a, %b %rem = urem i64 %a, %b
ret i64 %rem ret i64 %rem
} }
declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
define i64 @f18(i64 %X) nounwind readnone { define i64 @f18(i64 %X) nounwind readnone {
entry: entry:
; ALL-LABEL: f18: ; ALL-LABEL: f18:
; The MIPS4 version is too long to reasonably test. At least check we don't get dclz ; The MIPS4 version is too long to reasonably test. At least check we don't get dclz
; MIPS4-NOT: dclz ; MIPS4-NOT: dclz
; MIPS64: dclz $2, $4 ; HAS-DCLO: dclz $2, $4
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
ret i64 %tmp1 ret i64 %tmp1
} }
define i64 @f19(i64 %X) nounwind readnone { define i64 @f19(i64 %X) nounwind readnone {
entry: entry:
; ALL-LABEL: f19: ; ALL-LABEL: f19:
; The MIPS4 version is too long to reasonably test. At least check we don't get dclo ; The MIPS4 version is too long to reasonably test. At least check we don't get dclo
; MIPS4-NOT: dclo ; MIPS4-NOT: dclo
; MIPS64: dclo $2, $4 ; HAS-DCLO: dclo $2, $4
%neg = xor i64 %X, -1 %neg = xor i64 %X, -1
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
ret i64 %tmp1 ret i64 %tmp1
} }
define i64 @f20(i64 %a, i64 %b) nounwind readnone { define i64 @f20(i64 %a, i64 %b) nounwind readnone {
entry: entry:
; ALL-LABEL: f20: ; ALL-LABEL: f20:
; ALL: nor $2, ${{[45]}}, ${{[45]}} ; ALL: nor $2, ${{[45]}}, ${{[45]}}
%or = or i64 %b, %a %or = or i64 %b, %a
%neg = xor i64 %or, -1 %neg = xor i64 %or, -1
ret i64 %neg ret i64 %neg
} }

test/MC/Disassembler/Mips/mips32r6.txt

Show First 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4 0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4
0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4 0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4
0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4 0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4
0x00 0x80 0x04 0x09 # CHECK: jr.hb $4 0x00 0x80 0x04 0x09 # CHECK: jr.hb $4
0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18) 0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18)
0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19) 0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19)
0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5
0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp

test/MC/Disassembler/Mips/mips64r6.txt

Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Lines
0xec 0x58 0x3c 0x48 # CHECK: ldpc $2, 123456 0xec 0x58 0x3c 0x48 # CHECK: ldpc $2, 123456
0x00 0x80 0x04 0x09 # CHECK: jr.hb $4 0x00 0x80 0x04 0x09 # CHECK: jr.hb $4
0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18) 0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18)
0x7f 0xe0 0x38 0x37 # CHECK: lld $zero, 112($ra) 0x7f 0xe0 0x38 0x37 # CHECK: lld $zero, 112($ra)
0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19) 0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19)
0x7f 0xaf 0xe6 0xa7 # CHECK: scd $15, -51($sp) 0x7f 0xaf 0xe6 0xa7 # CHECK: scd $15, -51($sp)
0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5
0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
0x00 0xc0 0x90 0x53 # CHECK: dclo $18, $6
0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25

test/MC/Mips/mips32/valid.s

Show All 23 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08]
c.ngl.d $f29,$f29 c.ngl.d $f29,$f29
c.ngle.d $f0,$f16 c.ngle.d $f0,$f16
c.sf.d $f30,$f0 c.sf.d $f30,$f0
c.sf.s $f14,$f22 c.sf.s $f14,$f22
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.s $f22,$f28 cvt.d.s $f22,$f28
cvt.d.w $f26,$f11 cvt.d.w $f26,$f11
cvt.s.d $f26,$f8 cvt.s.d $f26,$f8
cvt.s.w $f22,$f15 cvt.s.w $f22,$f15
cvt.w.d $f20,$f14 cvt.w.d $f20,$f14
cvt.w.s $f20,$f24 cvt.w.s $f20,$f24
deret deret
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test/MC/Mips/mips32r2/valid.s

Show All 23 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08]
c.ngl.d $f29,$f29 c.ngl.d $f29,$f29
c.ngle.d $f0,$f16 c.ngle.d $f0,$f16
c.sf.d $f30,$f0 c.sf.d $f30,$f0
c.sf.s $f14,$f22 c.sf.s $f14,$f22
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.s $f22,$f28 cvt.d.s $f22,$f28
cvt.d.w $f26,$f11 cvt.d.w $f26,$f11
cvt.l.d $f24,$f15 cvt.l.d $f24,$f15
cvt.l.s $f11,$f29 cvt.l.s $f11,$f29
cvt.s.d $f26,$f8 cvt.s.d $f26,$f8
cvt.s.w $f22,$f15 cvt.s.w $f22,$f15
cvt.w.d $f20,$f14 cvt.w.d $f20,$f14
▲ Show 20 Lines • Show All 149 Lines • Show Last 20 Lines

test/MC/Mips/mips32r6/valid.s

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 | FileCheck %s
jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09]
jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43] ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43]
lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7] lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7]
sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75] sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75]
swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30] swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30]
ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6] ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6]
sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26] sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26]
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]

test/MC/Mips/mips64/valid.s

Show All 25 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s
c.ngle.d $f0,$f16 c.ngle.d $f0,$f16
c.sf.d $f30,$f0 c.sf.d $f30,$f0
c.sf.s $f14,$f22 c.sf.s $f14,$f22
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.l $f4,$f16 cvt.d.l $f4,$f16
cvt.d.s $f22,$f28 cvt.d.s $f22,$f28
cvt.d.w $f26,$f11 cvt.d.w $f26,$f11
cvt.l.d $f24,$f15 cvt.l.d $f24,$f15
cvt.l.s $f11,$f29 cvt.l.s $f11,$f29
cvt.s.d $f26,$f8 cvt.s.d $f26,$f8
cvt.s.l $f15,$f30 cvt.s.l $f15,$f30
cvt.s.w $f22,$f15 cvt.s.w $f22,$f15
cvt.w.d $f20,$f14 cvt.w.d $f20,$f14
cvt.w.s $f20,$f24 cvt.w.s $f20,$f24
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
dclo $s2,$a2 dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25]
dclz $s0,$25 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
deret deret
ddiv $zero,$k0,$s3 ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1 ddivu $zero,$s0,$s1
div $zero,$25,$11 div $zero,$25,$11
div.d $f29,$f20,$f27 div.d $f29,$f20,$f27
div.s $f4,$f5,$f15 div.s $f4,$f5,$f15
divu $zero,$25,$15 divu $zero,$25,$15
dmfc1 $12,$f13 dmfc1 $12,$f13
▲ Show 20 Lines • Show All 164 Lines • Show Last 20 Lines

test/MC/Mips/mips64r2/valid.s

Show All 25 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
c.ngle.d $f0,$f16 c.ngle.d $f0,$f16
c.sf.d $f30,$f0 c.sf.d $f30,$f0
c.sf.s $f14,$f22 c.sf.s $f14,$f22
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.l $f4,$f16 cvt.d.l $f4,$f16
cvt.d.s $f22,$f28 cvt.d.s $f22,$f28
cvt.d.w $f26,$f11 cvt.d.w $f26,$f11
cvt.l.d $f24,$f15 cvt.l.d $f24,$f15
cvt.l.s $f11,$f29 cvt.l.s $f11,$f29
cvt.s.d $f26,$f8 cvt.s.d $f26,$f8
cvt.s.l $f15,$f30 cvt.s.l $f15,$f30
cvt.s.w $f22,$f15 cvt.s.w $f22,$f15
cvt.w.d $f20,$f14 cvt.w.d $f20,$f14
cvt.w.s $f20,$f24 cvt.w.s $f20,$f24
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
dclo $s2,$a2 dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25]
dclz $s0,$25 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
deret deret
di $s8 di $s8
ddiv $zero,$k0,$s3 ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1 ddivu $zero,$s0,$s1
div $zero,$25,$11 div $zero,$25,$11
div.d $f29,$f20,$f27 div.d $f29,$f20,$f27
div.s $f4,$f5,$f15 div.s $f4,$f5,$f15
divu $zero,$25,$15 divu $zero,$25,$15
▲ Show 20 Lines • Show All 192 Lines • Show Last 20 Lines

test/MC/Mips/mips64r6/valid.s

Show First 20 Lines • Show All 146 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 | FileCheck %s
ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43] ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43]
lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7] lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7]
sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75] sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75]
swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30] swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30]
ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6] ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6]
lld $zero,112($ra) # CHECK: lld $zero, 112($ra) # encoding: [0x7f,0xe0,0x38,0x37] lld $zero,112($ra) # CHECK: lld $zero, 112($ra) # encoding: [0x7f,0xe0,0x38,0x37]
sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26] sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26]
scd $15,-51($sp) # CHECK: scd $15, -51($sp) # encoding: [0x7f,0xaf,0xe6,0xa7] scd $15,-51($sp) # CHECK: scd $15, -51($sp) # encoding: [0x7f,0xaf,0xe6,0xa7]
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x00,0xc0,0x90,0x53]
dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52]
test/CodeGen/Mips/countleading.ll