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Differential D4117

[mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates rather than 16-bit in MIPS32r6/MIPS64r6
ClosedPublic

Authored by dsanders on Jun 12 2014, 5:49 AM.

Details

Reviewers
jkolek
vmedic
zoran.jovanovic
Commits
rG5e6f54e07b8c: [mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates…
rL211012: [mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates…
Summary

The error message for the invalid.s cases isn't very helpful. It happens because
there is an instruction with a wider immediate that would have matched if the
NotMips32r6 predicate were true. I have some WIP to improve the message but it
affects most error messages for removed/re-encoded instructions on
MIPS32r6/MIPS64r6 and should therefore be a separate commit.

Depens on D4115

Diff Detail

Event Timeline

dsanders updated this revision to Diff 10354.Jun 12 2014, 5:49 AM
dsanders retitled this revision from to [mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates rather than 16-bit in MIPS32r6/MIPS64r6.
dsanders updated this object.
dsanders edited the test plan for this revision. (Show Details)
dsanders added reviewers: vmedic, zoran.jovanovic, jkolek.
dsanders added a parent revision: D4116: [mips] Add cache and pref instructions.Jun 13 2014, 6:24 AM
dsanders updated this object.Jun 16 2014, 1:45 AM
vmedic accepted this revision.Jun 16 2014, 2:12 AM
vmedic edited edge metadata.

LGTM

This revision is now accepted and ready to land.Jun 16 2014, 2:12 AM
dsanders closed this revision.Jun 16 2014, 3:08 AM

Revision Contents

PathSize
lib/
Target/
Mips/
AsmParser/
10 lines
23 lines
36 lines
12 lines
16 lines
test/
MC/
Mips/
mips1/
4 lines
mips2/
8 lines
mips3/
8 lines
mips32/
8 lines
mips32r2/
8 lines
mips32r6/
8 lines
4 lines
mips4/
8 lines
mips5/
8 lines
mips64/
8 lines
mips64r2/
8 lines
mips64r6/
6 lines
4 lines

Diff 10354

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Show First 20 Lines • Show All 614 Lines • ▼ Show 20 Lines bool isConstantImm() const {
return isImm() && dyn_cast<MCConstantExpr>(getImm()); return isImm() && dyn_cast<MCConstantExpr>(getImm());
} }
bool isToken() const override { bool isToken() const override {
// Note: It's not possible to pretend that other operand kinds are tokens. // Note: It's not possible to pretend that other operand kinds are tokens.
// The matcher emitter checks tokens first. // The matcher emitter checks tokens first.
return Kind == k_Token; return Kind == k_Token;
} }
bool isMem() const override { return Kind == k_Memory; } bool isMem() const override { return Kind == k_Memory; }
bool isConstantMemOff() const {
return isMem() && dyn_cast<MCConstantExpr>(getMemOff());
}
template <unsigned Bits> bool isMemWithSimmOffset() const {
return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff());
}
bool isInvNum() const { return Kind == k_Immediate; } bool isInvNum() const { return Kind == k_Immediate; }
bool isLSAImm() const { bool isLSAImm() const {
if (!isConstantImm()) if (!isConstantImm())
return false; return false;
int64_t Val = getConstantImm(); int64_t Val = getConstantImm();
return 1 <= Val && Val <= 4; return 1 <= Val && Val <= 4;
} }
Show All 28 Lines MipsOperand *getMemBase() const {
return Mem.Base; return Mem.Base;
} }
const MCExpr *getMemOff() const { const MCExpr *getMemOff() const {
assert((Kind == k_Memory) && "Invalid access!"); assert((Kind == k_Memory) && "Invalid access!");
return Mem.Off; return Mem.Off;
} }
int64_t getConstantMemOff() const {
return static_cast<const MCConstantExpr *>(getMemOff())->getValue();
}
static std::unique_ptr<MipsOperand> CreateToken(StringRef Str, SMLoc S, static std::unique_ptr<MipsOperand> CreateToken(StringRef Str, SMLoc S,
MipsAsmParser &Parser) { MipsAsmParser &Parser) {
auto Op = make_unique<MipsOperand>(k_Token, Parser); auto Op = make_unique<MipsOperand>(k_Token, Parser);
Op->Tok.Data = Str.data(); Op->Tok.Data = Str.data();
Op->Tok.Length = Str.size(); Op->Tok.Length = Str.size();
Op->StartLoc = S; Op->StartLoc = S;
Op->EndLoc = S; Op->EndLoc = S;
return Op; return Op;
▲ Show 20 Lines • Show All 1,986 Lines • Show Last 20 Lines

lib/Target/Mips/Mips32r6InstrFormats.td

Show All 34 Lines
def OPGROUP_BLEZL : OPGROUP<0b010110>; def OPGROUP_BLEZL : OPGROUP<0b010110>;
def OPGROUP_BGTZL : OPGROUP<0b010111>; def OPGROUP_BGTZL : OPGROUP<0b010111>;
def OPGROUP_DADDI : OPGROUP<0b011000>; def OPGROUP_DADDI : OPGROUP<0b011000>;
def OPGROUP_DAUI : OPGROUP<0b011101>; def OPGROUP_DAUI : OPGROUP<0b011101>;
def OPGROUP_PCREL : OPGROUP<0b111011>; def OPGROUP_PCREL : OPGROUP<0b111011>;
def OPGROUP_REGIMM : OPGROUP<0b000001>; def OPGROUP_REGIMM : OPGROUP<0b000001>;
def OPGROUP_SPECIAL : OPGROUP<0b000000>; def OPGROUP_SPECIAL : OPGROUP<0b000000>;
def OPGROUP_SPECIAL3 : OPGROUP<0b011111>; def OPGROUP_SPECIAL3 : OPGROUP<0b011111>;
// The spec names this constant LWC2, LDC2, SWC2, and SDC2 in different places.
def OPGROUP_COP2LDST : OPGROUP<0b010010>;
class OPCODE2<bits<2> Val> { class OPCODE2<bits<2> Val> {
bits<2> Value = Val; bits<2> Value = Val;
} }
def OPCODE2_ADDIUPC : OPCODE2<0b00>; def OPCODE2_ADDIUPC : OPCODE2<0b00>;
def OPCODE2_LWPC : OPCODE2<0b01>; def OPCODE2_LWPC : OPCODE2<0b01>;
def OPCODE2_LWUPC : OPCODE2<0b10>; def OPCODE2_LWUPC : OPCODE2<0b10>;
Show All 9 Lines
def OPCODE5_AUIPC : OPCODE5<0b11110>; def OPCODE5_AUIPC : OPCODE5<0b11110>;
def OPCODE5_DAHI : OPCODE5<0b00110>; def OPCODE5_DAHI : OPCODE5<0b00110>;
def OPCODE5_DATI : OPCODE5<0b11110>; def OPCODE5_DATI : OPCODE5<0b11110>;
def OPCODE5_BC1EQZ : OPCODE5<0b01001>; def OPCODE5_BC1EQZ : OPCODE5<0b01001>;
def OPCODE5_BC1NEZ : OPCODE5<0b01101>; def OPCODE5_BC1NEZ : OPCODE5<0b01101>;
def OPCODE5_BC2EQZ : OPCODE5<0b01001>; def OPCODE5_BC2EQZ : OPCODE5<0b01001>;
def OPCODE5_BC2NEZ : OPCODE5<0b01101>; def OPCODE5_BC2NEZ : OPCODE5<0b01101>;
def OPCODE5_BGEZAL : OPCODE5<0b10001>; def OPCODE5_BGEZAL : OPCODE5<0b10001>;
// The next four constants are unnamed in the spec. These names are taken from
// the OPGROUP names they are used with.
def OPCODE5_LDC2 : OPCODE5<0b01110>;
def OPCODE5_LWC2 : OPCODE5<0b01010>;
def OPCODE5_SDC2 : OPCODE5<0b01111>;
def OPCODE5_SWC2 : OPCODE5<0b01011>;
class OPCODE6<bits<6> Val> { class OPCODE6<bits<6> Val> {
bits<6> Value = Val; bits<6> Value = Val;
} }
def OPCODE6_ALIGN : OPCODE6<0b100000>; def OPCODE6_ALIGN : OPCODE6<0b100000>;
def OPCODE6_DALIGN : OPCODE6<0b100100>; def OPCODE6_DALIGN : OPCODE6<0b100100>;
def OPCODE6_BITSWAP : OPCODE6<0b100000>; def OPCODE6_BITSWAP : OPCODE6<0b100000>;
def OPCODE6_DBITSWAP : OPCODE6<0b100100>; def OPCODE6_DBITSWAP : OPCODE6<0b100100>;
▲ Show 20 Lines • Show All 364 Lines • ▼ Show 20 Linesclass JR_HB_R6_FM<OPCODE6 Operation> : MipsR6Inst {
let Inst{31-26} = OPGROUP_SPECIAL.Value; let Inst{31-26} = OPGROUP_SPECIAL.Value;
let Inst{25-21} = rs; let Inst{25-21} = rs;
let Inst{20-16} = 0; let Inst{20-16} = 0;
let Inst{15-11} = 0; let Inst{15-11} = 0;
let Inst{10} = 1; let Inst{10} = 1;
let Inst{9-6} = 0; let Inst{9-6} = 0;
let Inst{5-0} = Operation.Value; let Inst{5-0} = Operation.Value;
} }
class COP2LDST_FM<OPCODE5 Operation> : MipsR6Inst {
bits<5> rt;
bits<21> addr;
bits<5> base = addr{20-16};
bits<11> offset = addr{10-0};
bits<32> Inst;
let Inst{31-26} = OPGROUP_COP2LDST.Value;
let Inst{25-21} = Operation.Value;
let Inst{20-16} = rt;
let Inst{15-11} = base;
let Inst{10-0} = offset;
}

lib/Target/Mips/Mips32r6InstrInfo.td

Show All 12 Lines
include "Mips32r6InstrFormats.td" include "Mips32r6InstrFormats.td"
// Notes about removals/changes from MIPS32r6: // Notes about removals/changes from MIPS32r6:
// Unclear: ssnop // Unclear: ssnop
// Reencoded: clo, clz // Reencoded: clo, clz
// Reencoded: jr -> jalr // Reencoded: jr -> jalr
// Reencoded: jr.hb -> jalr.hb // Reencoded: jr.hb -> jalr.hb
// Reencoded: ldc2
// Reencoded: ll, sc // Reencoded: ll, sc
// Reencoded: lwc2
// Reencoded: sdbbp // Reencoded: sdbbp
// Reencoded: sdc2
// Reencoded: swc2
// Rencoded: [ls][wd]c2
def brtarget21 : Operand<OtherVT> { def brtarget21 : Operand<OtherVT> {
let EncoderMethod = "getBranchTarget21OpValue"; let EncoderMethod = "getBranchTarget21OpValue";
let OperandType = "OPERAND_PCREL"; let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTarget21"; let DecoderMethod = "DecodeBranchTarget21";
let ParserMatchClass = MipsJumpTargetAsmOperand; let ParserMatchClass = MipsJumpTargetAsmOperand;
} }
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>; class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>; class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>; class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>; class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
class CACHE_ENC : SPECIAL3_MEM_FM<OPCODE6_CACHE>; class CACHE_ENC : SPECIAL3_MEM_FM<OPCODE6_CACHE>;
class PREF_ENC : SPECIAL3_MEM_FM<OPCODE6_PREF>; class PREF_ENC : SPECIAL3_MEM_FM<OPCODE6_PREF>;
class LDC2_R6_ENC : COP2LDST_FM<OPCODE5_LDC2>;
class LWC2_R6_ENC : COP2LDST_FM<OPCODE5_LWC2>;
class SDC2_R6_ENC : COP2LDST_FM<OPCODE5_SDC2>;
class SWC2_R6_ENC : COP2LDST_FM<OPCODE5_SWC2>;
class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
RegisterOperand FGROpnd, RegisterOperand FGROpnd,
SDPatternOperator Op = null_frag> { SDPatternOperator Op = null_frag> {
dag OutOperandList = (outs FGRCCOpnd:$fd); dag OutOperandList = (outs FGRCCOpnd:$fd);
dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft"); string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))]; list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
} }
▲ Show 20 Lines • Show All 365 Lines • ▼ Show 20 Linesclass CACHE_HINT_DESC<string instr_asm, Operand MemOpnd,
dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
list<dag> Pattern = []; list<dag> Pattern = [];
} }
class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>; class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>;
class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, GPR32Opnd>; class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, GPR32Opnd>;
class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> {
dag OutOperandList = (outs COPOpnd:$rt);
dag InOperandList = (ins mem_simm11:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = [];
bit mayLoad = 1;
}
class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd>;
class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd>;
class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> {
dag OutOperandList = (outs);
dag InOperandList = (ins COPOpnd:$rt, mem_simm11:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = [];
bit mayStore = 1;
}
class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd>;
class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction Definitions // Instruction Definitions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6; def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6; def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
Show All 33 Lines
def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6; def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>; defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>; defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6; def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6; def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6; def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6; def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6; def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
// def LSA; // See MSA // def LSA; // See MSA
def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6; def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6; def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6; def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6; def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6; def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6; def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6; def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6; def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6; def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6; def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6; def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6; def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6; def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6; def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6; def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6; def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6; def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6; def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6; def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6; def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
def NAL; // BAL with rd=0 def NAL; // BAL with rd=0
def PREF_R6 : PREF_ENC, PREF_DESC, ISA_MIPS32R6; def PREF_R6 : PREF_ENC, PREF_DESC, ISA_MIPS32R6;
def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6; def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6; def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32; def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6; def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6; def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32; def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6; def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6; def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6; def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6; def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;
def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Patterns and Pseudo Instructions // Patterns and Pseudo Instructions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// f32 comparisons supported via another comparison // f32 comparisons supported via another comparison
▲ Show 20 Lines • Show All 70 Lines • Show Last 20 Lines

lib/Target/Mips/MipsInstrFPU.td

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def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>, def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>,
ISA_MIPS2, FGR_32; ISA_MIPS2, FGR_32;
def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>,
ISA_MIPS2, FGR_32; ISA_MIPS2, FGR_32;
// Cop2 Memory Instructions // Cop2 Memory Instructions
// FIXME: These aren't really FPU instructions and as such don't belong in this // FIXME: These aren't really FPU instructions and as such don't belong in this
// file // file
def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>; def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>; ISA_MIPS1_NOT_32R6_64R6;
def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>, ISA_MIPS2; def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>, ISA_MIPS2; ISA_MIPS1_NOT_32R6_64R6;
def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
ISA_MIPS2_NOT_32R6_64R6;
def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
ISA_MIPS2_NOT_32R6_64R6;
// Cop3 Memory Instructions // Cop3 Memory Instructions
// FIXME: These aren't really FPU instructions and as such don't belong in this // FIXME: These aren't really FPU instructions and as such don't belong in this
// file // file
let DecoderNamespace = "COP3_" in { let DecoderNamespace = "COP3_" in {
def LWC3 : LW_FT<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>; def LWC3 : LW_FT<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
def SWC3 : SW_FT<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>; def SWC3 : SW_FT<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
def LDC3 : LW_FT<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>, def LDC3 : LW_FT<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
▲ Show 20 Lines • Show All 230 Lines • Show Last 20 Lines

lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 345 Lines • ▼ Show 20 Lines
} }
def calltarget : Operand<iPTR> { def calltarget : Operand<iPTR> {
let EncoderMethod = "getJumpTargetOpValue"; let EncoderMethod = "getJumpTargetOpValue";
let ParserMatchClass = MipsJumpTargetAsmOperand; let ParserMatchClass = MipsJumpTargetAsmOperand;
} }
def simm9 : Operand<i32>; def simm9 : Operand<i32>;
def simm10 : Operand<i32>; def simm10 : Operand<i32>;
def simm11 : Operand<i32>;
def simm16 : Operand<i32> { def simm16 : Operand<i32> {
let DecoderMethod= "DecodeSimm16"; let DecoderMethod= "DecodeSimm16";
} }
def simm19_lsl2 : Operand<i32> { def simm19_lsl2 : Operand<i32> {
let EncoderMethod = "getSimm19Lsl2Encoding"; let EncoderMethod = "getSimm19Lsl2Encoding";
let DecoderMethod = "DecodeSimm19Lsl2"; let DecoderMethod = "DecodeSimm19Lsl2";
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
def pcrel16 : Operand<i32> { def pcrel16 : Operand<i32> {
} }
def MipsMemAsmOperand : AsmOperandClass { def MipsMemAsmOperand : AsmOperandClass {
let Name = "Mem"; let Name = "Mem";
let ParserMethod = "parseMemOperand"; let ParserMethod = "parseMemOperand";
} }
def MipsMemSimm11AsmOperand : AsmOperandClass {
let Name = "MemOffsetSimm11";
let SuperClasses = [MipsMemAsmOperand];
let RenderMethod = "addMemOperands";
let ParserMethod = "parseMemOperand";
let PredicateMethod = "isMemWithSimmOffset<11>";
//let DiagnosticType = "Simm11";
}
def MipsInvertedImmoperand : AsmOperandClass { def MipsInvertedImmoperand : AsmOperandClass {
let Name = "InvNum"; let Name = "InvNum";
let RenderMethod = "addImmOperands"; let RenderMethod = "addImmOperands";
let ParserMethod = "parseInvNum"; let ParserMethod = "parseInvNum";
} }
def InvertedImOperand : Operand<i32> { def InvertedImOperand : Operand<i32> {
let ParserMatchClass = MipsInvertedImmoperand; let ParserMatchClass = MipsInvertedImmoperand;
Show All 20 Linesdef mem_msa : mem_generic {
let EncoderMethod = "getMSAMemEncoding"; let EncoderMethod = "getMSAMemEncoding";
} }
def mem_simm9 : mem_generic { def mem_simm9 : mem_generic {
let MIOperandInfo = (ops ptr_rc, simm9); let MIOperandInfo = (ops ptr_rc, simm9);
let EncoderMethod = "getMemEncoding"; let EncoderMethod = "getMemEncoding";
} }
def mem_simm11 : mem_generic {
let MIOperandInfo = (ops ptr_rc, simm11);
let EncoderMethod = "getMemEncoding";
let ParserMatchClass = MipsMemSimm11AsmOperand;
}
def mem_ea : Operand<iPTR> { def mem_ea : Operand<iPTR> {
let PrintMethod = "printMemOperandEA"; let PrintMethod = "printMemOperandEA";
let MIOperandInfo = (ops ptr_rc, simm16); let MIOperandInfo = (ops ptr_rc, simm16);
let EncoderMethod = "getMemEncoding"; let EncoderMethod = "getMemEncoding";
let OperandType = "OPERAND_MEMORY"; let OperandType = "OPERAND_MEMORY";
} }
def PtrRC : Operand<iPTR> { def PtrRC : Operand<iPTR> {
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test/MC/Mips/mips1/valid.s

Show All 38 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | FileCheck %s
lb $24,-14515($10) lb $24,-14515($10)
lbu $8,30195($v1) lbu $8,30195($v1)
lh $11,-8556($s5) lh $11,-8556($s5)
lhu $s3,-22851($v0) lhu $s3,-22851($v0)
li $at,-29773 li $at,-29773
li $zero,-29889 li $zero,-29889
lw $8,5674($a1) lw $8,5674($a1)
lwc1 $f16,10225($k0) lwc1 $f16,10225($k0)
lwc2 $18,-841($a2) lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
lwc3 $10,-32265($k0) lwc3 $10,-32265($k0)
lwl $s4,-4231($15) lwl $s4,-4231($15)
lwr $zero,-19147($gp) lwr $zero,-19147($gp)
mfc1 $a3,$f27 mfc1 $a3,$f27
mfhi $s3 mfhi $s3
mfhi $sp mfhi $sp
mflo $s1 mflo $s1
mov.d $f20,$f14 mov.d $f20,$f14
Show All 38 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | FileCheck %s
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12 sub $s6,$s3,$12
sub.d $f18,$f3,$f17 sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22 sub.s $f23,$f22,$f22
subu $sp,$s6,$s6 subu $sp,$s6,$s6
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swc3 $10,-32265($k0) swc3 $10,-32265($k0)
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
xor $s2,$a0,$s8 xor $s2,$a0,$s8

test/MC/Mips/mips2/valid.s

Show All 37 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | FileCheck %s
div.s $f4,$f5,$f15 div.s $f4,$f5,$f15
divu $zero,$25,$15 divu $zero,$25,$15
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
lb $24,-14515($10) lb $24,-14515($10)
lbu $8,30195($v1) lbu $8,30195($v1)
ldc1 $f11,16391($s0) ldc1 $f11,16391($s0)
ldc2 $8,-21181($at) ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
ldc3 $29,-28645($s1) ldc3 $29,-28645($s1)
lh $11,-8556($s5) lh $11,-8556($s5)
lhu $s3,-22851($v0) lhu $s3,-22851($v0)
li $at,-29773 li $at,-29773
li $zero,-29889 li $zero,-29889
ll $v0,-7321($s2) ll $v0,-7321($s2)
lw $8,5674($a1) lw $8,5674($a1)
lwc1 $f16,10225($k0) lwc1 $f16,10225($k0)
lwc2 $18,-841($a2) lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
lwc3 $10,-32265($k0) lwc3 $10,-32265($k0)
lwl $s4,-4231($15) lwl $s4,-4231($15)
lwr $zero,-19147($gp) lwr $zero,-19147($gp)
mfc1 $a3,$f27 mfc1 $a3,$f27
mfhi $s3 mfhi $s3
mfhi $sp mfhi $sp
mflo $s1 mflo $s1
mov.d $f20,$f14 mov.d $f20,$f14
Show All 17 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | FileCheck %s
nop nop
nor $a3,$zero,$a3 nor $a3,$zero,$a3
or $12,$s0,$sp or $12,$s0,$sp
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) sc $15,18904($s3)
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdc3 $12,5835($10) sdc3 $12,5835($10)
sh $14,-6704($15) sh $14,-6704($15)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
Show All 12 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | FileCheck %s
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12 sub $s6,$s3,$12
sub.d $f18,$f3,$f17 sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22 sub.s $f23,$f22,$f22
subu $sp,$s6,$s6 subu $sp,$s6,$s6
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swc3 $10,-32265($k0) swc3 $10,-32265($k0)
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
teqi $s5,-17504 teqi $s5,-17504
tgei $s1,5025 tgei $s1,5025
tgeiu $sp,-28621 tgeiu $sp,-28621
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $14,-21059 tlti $14,-21059
tltiu $ra,-5076 tltiu $ra,-5076
tnei $12,-29647 tnei $12,-29647
trunc.w.d $f22,$f15 trunc.w.d $f22,$f15
trunc.w.s $f28,$f30 trunc.w.s $f28,$f30
xor $s2,$a0,$s8 xor $s2,$a0,$s8

test/MC/Mips/mips3/valid.s

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 | FileCheck %s
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
lb $24,-14515($10) lb $24,-14515($10)
lbu $8,30195($v1) lbu $8,30195($v1)
ld $sp,-28645($s1) ld $sp,-28645($s1)
ldc1 $f11,16391($s0) ldc1 $f11,16391($s0)
ldc2 $8,-21181($at) ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
ldl $24,-4167($24) ldl $24,-4167($24)
ldr $14,-30358($s4) ldr $14,-30358($s4)
lh $11,-8556($s5) lh $11,-8556($s5)
lhu $s3,-22851($v0) lhu $s3,-22851($v0)
li $at,-29773 li $at,-29773
li $zero,-29889 li $zero,-29889
ll $v0,-7321($s2) ll $v0,-7321($s2)
lld $zero,-14736($ra) lld $zero,-14736($ra)
lw $8,5674($a1) lw $8,5674($a1)
lwc1 $f16,10225($k0) lwc1 $f16,10225($k0)
lwc2 $18,-841($a2) lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
lwl $s4,-4231($15) lwl $s4,-4231($15)
lwr $zero,-19147($gp) lwr $zero,-19147($gp)
lwu $s3,-24086($v1) lwu $s3,-24086($v1)
mfc1 $a3,$f27 mfc1 $a3,$f27
mfhi $s3 mfhi $s3
mfhi $sp mfhi $sp
mflo $s1 mflo $s1
mov.d $f20,$f14 mov.d $f20,$f14
Show All 23 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 | FileCheck %s
round.l.s $f25,$f5 round.l.s $f25,$f5
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) sc $15,18904($s3)
scd $15,-8243($sp) scd $15,-8243($sp)
sd $12,5835($10) sd $12,5835($10)
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdl $a3,-20961($s8) sdl $a3,-20961($s8)
sdr $11,-20423($12) sdr $11,-20423($12)
sh $14,-6704($15) sh $14,-6704($15)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
Show All 13 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 | FileCheck %s
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12 sub $s6,$s3,$12
sub.d $f18,$f3,$f17 sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22 sub.s $f23,$f22,$f22
subu $sp,$s6,$s6 subu $sp,$s6,$s6
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
teqi $s5,-17504 teqi $s5,-17504
tgei $s1,5025 tgei $s1,5025
tgeiu $sp,-28621 tgeiu $sp,-28621
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
Show All 9 Lines

test/MC/Mips/mips32/valid.s

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s
divu $zero,$25,$15 divu $zero,$25,$15
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
eret eret
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
lb $24,-14515($10) lb $24,-14515($10)
lbu $8,30195($v1) lbu $8,30195($v1)
ldc1 $f11,16391($s0) ldc1 $f11,16391($s0)
ldc2 $8,-21181($at) ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
lh $11,-8556($s5) lh $11,-8556($s5)
lhu $s3,-22851($v0) lhu $s3,-22851($v0)
li $at,-29773 li $at,-29773
li $zero,-29889 li $zero,-29889
ll $v0,-7321($s2) ll $v0,-7321($s2)
lw $8,5674($a1) lw $8,5674($a1)
lwc1 $f16,10225($k0) lwc1 $f16,10225($k0)
lwc2 $18,-841($a2) lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
lwl $s4,-4231($15) lwl $s4,-4231($15)
lwr $zero,-19147($gp) lwr $zero,-19147($gp)
madd $s6,$13 madd $s6,$13
madd $zero,$9 madd $zero,$9
maddu $s3,$gp maddu $s3,$gp
maddu $24,$s2 maddu $24,$s2
mfc0 $a2,$14,1 mfc0 $a2,$14,1
mfc1 $a3,$f27 mfc1 $a3,$f27
Show All 38 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s
nor $a3,$zero,$a3 nor $a3,$zero,$a3
or $12,$s0,$sp or $12,$s0,$sp
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) sc $15,18904($s3)
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sh $14,-6704($15) sh $14,-6704($15)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
Show All 11 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12 sub $s6,$s3,$12
sub.d $f18,$f3,$f17 sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22 sub.s $f23,$f22,$f22
subu $sp,$s6,$s6 subu $sp,$s6,$s6
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
teqi $s5,-17504 teqi $s5,-17504
tgei $s1,5025 tgei $s1,5025
tgeiu $sp,-28621 tgeiu $sp,-28621
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $14,-21059 tlti $14,-21059
tltiu $ra,-5076 tltiu $ra,-5076
tnei $12,-29647 tnei $12,-29647
trunc.w.d $f22,$f15 trunc.w.d $f22,$f15
trunc.w.s $f28,$f30 trunc.w.s $f28,$f30
xor $s2,$a0,$s8 xor $s2,$a0,$s8

test/MC/Mips/mips32r2/valid.s

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08]
jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09]
jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
lb $24,-14515($10) lb $24,-14515($10)
lbu $8,30195($v1) lbu $8,30195($v1)
ldc1 $f11,16391($s0) ldc1 $f11,16391($s0)
ldc2 $8,-21181($at) ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
ldxc1 $f8,$s7($15) ldxc1 $f8,$s7($15)
lh $11,-8556($s5) lh $11,-8556($s5)
lhu $s3,-22851($v0) lhu $s3,-22851($v0)
li $at,-29773 li $at,-29773
li $zero,-29889 li $zero,-29889
ll $v0,-7321($s2) ll $v0,-7321($s2)
luxc1 $f19,$s6($s5) luxc1 $f19,$s6($s5)
lw $8,5674($a1) lw $8,5674($a1)
lwc1 $f16,10225($k0) lwc1 $f16,10225($k0)
lwc2 $18,-841($a2) lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
lwl $s4,-4231($15) lwl $s4,-4231($15)
lwr $zero,-19147($gp) lwr $zero,-19147($gp)
lwxc1 $f12,$s1($s8) lwxc1 $f12,$s1($s8)
madd $s6,$13 madd $s6,$13
madd $zero,$9 madd $zero,$9
madd.d $f18,$f19,$f26,$f20 madd.d $f18,$f19,$f26,$f20
madd.s $f1,$f31,$f19,$f25 madd.s $f1,$f31,$f19,$f25
maddu $s3,$gp maddu $s3,$gp
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) sc $15,18904($s3)
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdxc1 $f11,$10($14) sdxc1 $f11,$10($14)
seb $25,$15 seb $25,$15
seh $v1,$12 seh $v1,$12
sh $14,-6704($15) sh $14,-6704($15)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
Show All 15 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12 sub $s6,$s3,$12
sub.d $f18,$f3,$f17 sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22 sub.s $f23,$f22,$f22
subu $sp,$s6,$s6 subu $sp,$s6,$s6
suxc1 $f12,$k1($13) suxc1 $f12,$k1($13)
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
teqi $s5,-17504 teqi $s5,-17504
tgei $s1,5025 tgei $s1,5025
tgeiu $sp,-28621 tgeiu $sp,-28621
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
Show All 9 Lines

test/MC/Mips/mips32r6/invalid.s

# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g. # Instructions that are available for the current ISA but should be rejected by
# invalid set of operands or operand's restrictions not met). # the assembler (e.g. invalid set of operands or operand's restrictions not met).
# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r6 2>%t1 # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r6 2>%t1
# RUN: FileCheck %s < %t1 -check-prefix=ASM # RUN: FileCheck %s < %t1 -check-prefix=ASM
.text .text
.set noreorder .set noreorder
.set noat
jalr.hb $31 jalr.hb $31
# ASM: :[[@LINE-1]]:9: error: source and destination must be different # ASM: :[[@LINE-1]]:9: error: source and destination must be different
jalr.hb $31, $31 jalr.hb $31, $31
# ASM: :[[@LINE-1]]:9: error: source and destination must be different # ASM: :[[@LINE-1]]:9: error: source and destination must be different
ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sdc2 $20,23157($s2) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swc2 $25,24880($s0) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

test/MC/Mips/mips32r6/valid.s

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 | FileCheck %s
selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17] selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17]
rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9a] rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9a]
rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a] rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a]
class.s $f2, $f4 # CHECK: class.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9b] class.s $f2, $f4 # CHECK: class.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9b]
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9b] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9b]
jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x09] jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x09]
jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09]
jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43]
lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7]
sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75]
swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30]

test/MC/Mips/mips4/valid.s

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | FileCheck %s
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
lb $24,-14515($10) lb $24,-14515($10)
lbu $8,30195($v1) lbu $8,30195($v1)
ld $sp,-28645($s1) ld $sp,-28645($s1)
ldc1 $f11,16391($s0) ldc1 $f11,16391($s0)
ldc2 $8,-21181($at) ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
ldl $24,-4167($24) ldl $24,-4167($24)
ldr $14,-30358($s4) ldr $14,-30358($s4)
ldxc1 $f8,$s7($15) ldxc1 $f8,$s7($15)
lh $11,-8556($s5) lh $11,-8556($s5)
lhu $s3,-22851($v0) lhu $s3,-22851($v0)
li $at,-29773 li $at,-29773
li $zero,-29889 li $zero,-29889
ll $v0,-7321($s2) ll $v0,-7321($s2)
lld $zero,-14736($ra) lld $zero,-14736($ra)
lw $8,5674($a1) lw $8,5674($a1)
lwc1 $f16,10225($k0) lwc1 $f16,10225($k0)
lwc2 $18,-841($a2) lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
lwl $s4,-4231($15) lwl $s4,-4231($15)
lwr $zero,-19147($gp) lwr $zero,-19147($gp)
lwu $s3,-24086($v1) lwu $s3,-24086($v1)
lwxc1 $f12,$s1($s8) lwxc1 $f12,$s1($s8)
mfc1 $a3,$f27 mfc1 $a3,$f27
mfhi $s3 mfhi $s3
mfhi $sp mfhi $sp
mflo $s1 mflo $s1
Show All 37 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | FileCheck %s
round.l.s $f25,$f5 round.l.s $f25,$f5
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) sc $15,18904($s3)
scd $15,-8243($sp) scd $15,-8243($sp)
sd $12,5835($10) sd $12,5835($10)
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdl $a3,-20961($s8) sdl $a3,-20961($s8)
sdr $11,-20423($12) sdr $11,-20423($12)
sdxc1 $f11,$10($14) sdxc1 $f11,$10($14)
sh $14,-6704($15) sh $14,-6704($15)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
Show All 14 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | FileCheck %s
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12 sub $s6,$s3,$12
sub.d $f18,$f3,$f17 sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22 sub.s $f23,$f22,$f22
subu $sp,$s6,$s6 subu $sp,$s6,$s6
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
teqi $s5,-17504 teqi $s5,-17504
tgei $s1,5025 tgei $s1,5025
tgeiu $sp,-28621 tgeiu $sp,-28621
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
Show All 10 Lines

test/MC/Mips/mips5/valid.s

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | FileCheck %s
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
lb $24,-14515($10) lb $24,-14515($10)
lbu $8,30195($v1) lbu $8,30195($v1)
ld $sp,-28645($s1) ld $sp,-28645($s1)
ldc1 $f11,16391($s0) ldc1 $f11,16391($s0)
ldc2 $8,-21181($at) ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
ldl $24,-4167($24) ldl $24,-4167($24)
ldr $14,-30358($s4) ldr $14,-30358($s4)
ldxc1 $f8,$s7($15) ldxc1 $f8,$s7($15)
lh $11,-8556($s5) lh $11,-8556($s5)
lhu $s3,-22851($v0) lhu $s3,-22851($v0)
li $at,-29773 li $at,-29773
li $zero,-29889 li $zero,-29889
ll $v0,-7321($s2) ll $v0,-7321($s2)
lld $zero,-14736($ra) lld $zero,-14736($ra)
luxc1 $f19,$s6($s5) luxc1 $f19,$s6($s5)
lw $8,5674($a1) lw $8,5674($a1)
lwc1 $f16,10225($k0) lwc1 $f16,10225($k0)
lwc2 $18,-841($a2) lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
lwl $s4,-4231($15) lwl $s4,-4231($15)
lwr $zero,-19147($gp) lwr $zero,-19147($gp)
lwu $s3,-24086($v1) lwu $s3,-24086($v1)
lwxc1 $f12,$s1($s8) lwxc1 $f12,$s1($s8)
mfc1 $a3,$f27 mfc1 $a3,$f27
mfhi $s3 mfhi $s3
mfhi $sp mfhi $sp
mflo $s1 mflo $s1
Show All 37 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | FileCheck %s
round.l.s $f25,$f5 round.l.s $f25,$f5
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) sc $15,18904($s3)
scd $15,-8243($sp) scd $15,-8243($sp)
sd $12,5835($10) sd $12,5835($10)
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdl $a3,-20961($s8) sdl $a3,-20961($s8)
sdr $11,-20423($12) sdr $11,-20423($12)
sdxc1 $f11,$10($14) sdxc1 $f11,$10($14)
sh $14,-6704($15) sh $14,-6704($15)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
Show All 15 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | FileCheck %s
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12 sub $s6,$s3,$12
sub.d $f18,$f3,$f17 sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22 sub.s $f23,$f22,$f22
subu $sp,$s6,$s6 subu $sp,$s6,$s6
suxc1 $f12,$k1($13) suxc1 $f12,$k1($13)
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
teqi $s5,-17504 teqi $s5,-17504
tgei $s1,5025 tgei $s1,5025
tgeiu $sp,-28621 tgeiu $sp,-28621
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
Show All 10 Lines

test/MC/Mips/mips64/valid.s

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
lb $24,-14515($10) lb $24,-14515($10)
lbu $8,30195($v1) lbu $8,30195($v1)
ld $sp,-28645($s1) ld $sp,-28645($s1)
ldc1 $f11,16391($s0) ldc1 $f11,16391($s0)
ldc2 $8,-21181($at) ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
ldl $24,-4167($24) ldl $24,-4167($24)
ldr $14,-30358($s4) ldr $14,-30358($s4)
ldxc1 $f8,$s7($15) ldxc1 $f8,$s7($15)
lh $11,-8556($s5) lh $11,-8556($s5)
lhu $s3,-22851($v0) lhu $s3,-22851($v0)
li $at,-29773 li $at,-29773
li $zero,-29889 li $zero,-29889
ll $v0,-7321($s2) ll $v0,-7321($s2)
lld $zero,-14736($ra) lld $zero,-14736($ra)
luxc1 $f19,$s6($s5) luxc1 $f19,$s6($s5)
lw $8,5674($a1) lw $8,5674($a1)
lwc1 $f16,10225($k0) lwc1 $f16,10225($k0)
lwc2 $18,-841($a2) lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
lwl $s4,-4231($15) lwl $s4,-4231($15)
lwr $zero,-19147($gp) lwr $zero,-19147($gp)
lwu $s3,-24086($v1) lwu $s3,-24086($v1)
lwxc1 $f12,$s1($s8) lwxc1 $f12,$s1($s8)
madd $s6,$13 madd $s6,$13
madd $zero,$9 madd $zero,$9
maddu $s3,$gp maddu $s3,$gp
maddu $24,$s2 maddu $24,$s2
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s
round.l.s $f25,$f5 round.l.s $f25,$f5
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) sc $15,18904($s3)
scd $15,-8243($sp) scd $15,-8243($sp)
sd $12,5835($10) sd $12,5835($10)
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdl $a3,-20961($s8) sdl $a3,-20961($s8)
sdr $11,-20423($12) sdr $11,-20423($12)
sdxc1 $f11,$10($14) sdxc1 $f11,$10($14)
sh $14,-6704($15) sh $14,-6704($15)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
Show All 15 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12 sub $s6,$s3,$12
sub.d $f18,$f3,$f17 sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22 sub.s $f23,$f22,$f22
subu $sp,$s6,$s6 subu $sp,$s6,$s6
suxc1 $f12,$k1($13) suxc1 $f12,$k1($13)
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
teqi $s5,-17504 teqi $s5,-17504
tgei $s1,5025 tgei $s1,5025
tgeiu $sp,-28621 tgeiu $sp,-28621
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
Show All 10 Lines

test/MC/Mips/mips64r2/valid.s

Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
floor.w.s $f8,$f9 floor.w.s $f8,$f9
jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08]
jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09]
jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
lb $24,-14515($10) lb $24,-14515($10)
lbu $8,30195($v1) lbu $8,30195($v1)
ld $sp,-28645($s1) ld $sp,-28645($s1)
ldc1 $f11,16391($s0) ldc1 $f11,16391($s0)
ldc2 $8,-21181($at) ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
ldl $24,-4167($24) ldl $24,-4167($24)
ldr $14,-30358($s4) ldr $14,-30358($s4)
ldxc1 $f8,$s7($15) ldxc1 $f8,$s7($15)
lh $11,-8556($s5) lh $11,-8556($s5)
lhu $s3,-22851($v0) lhu $s3,-22851($v0)
li $at,-29773 li $at,-29773
li $zero,-29889 li $zero,-29889
ll $v0,-7321($s2) ll $v0,-7321($s2)
lld $zero,-14736($ra) lld $zero,-14736($ra)
luxc1 $f19,$s6($s5) luxc1 $f19,$s6($s5)
lw $8,5674($a1) lw $8,5674($a1)
lwc1 $f16,10225($k0) lwc1 $f16,10225($k0)
lwc2 $18,-841($a2) lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
lwl $s4,-4231($15) lwl $s4,-4231($15)
lwr $zero,-19147($gp) lwr $zero,-19147($gp)
lwu $s3,-24086($v1) lwu $s3,-24086($v1)
lwxc1 $f12,$s1($s8) lwxc1 $f12,$s1($s8)
madd $s6,$13 madd $s6,$13
madd $zero,$9 madd $zero,$9
madd.s $f1,$f31,$f19,$f25 madd.s $f1,$f31,$f19,$f25
maddu $s3,$gp maddu $s3,$gp
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
round.l.s $f25,$f5 round.l.s $f25,$f5
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) sc $15,18904($s3)
scd $15,-8243($sp) scd $15,-8243($sp)
sd $12,5835($10) sd $12,5835($10)
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdl $a3,-20961($s8) sdl $a3,-20961($s8)
sdr $11,-20423($12) sdr $11,-20423($12)
sdxc1 $f11,$10($14) sdxc1 $f11,$10($14)
seb $25,$15 seb $25,$15
seh $v1,$12 seh $v1,$12
sh $14,-6704($15) sh $14,-6704($15)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
Show All 17 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12 sub $s6,$s3,$12
sub.d $f18,$f3,$f17 sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22 sub.s $f23,$f22,$f22
subu $sp,$s6,$s6 subu $sp,$s6,$s6
suxc1 $f12,$k1($13) suxc1 $f12,$k1($13)
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
teqi $s5,-17504 teqi $s5,-17504
tgei $s1,5025 tgei $s1,5025
tgeiu $sp,-28621 tgeiu $sp,-28621
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
Show All 11 Lines

test/MC/Mips/mips64r6/invalid.s

# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g. # Instructions that are available for the current ISA but should be rejected by
# invalid set of operands or operand's restrictions not met). # the assembler (e.g. invalid set of operands or operand's restrictions not met).
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r6 2>%t1 # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r6 2>%t1
# RUN: FileCheck %s < %t1 -check-prefix=ASM # RUN: FileCheck %s < %t1 -check-prefix=ASM
.text .text
.set noreorder .set noreorder
.set noat
jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

test/MC/Mips/mips64r6/valid.s

Show First 20 Lines • Show All 138 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 | FileCheck %s
selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17] selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17]
rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9a] rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9a]
rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a] rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a]
class.s $f2, $f4 # CHECK: class.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9b] class.s $f2, $f4 # CHECK: class.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9b]
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9b] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9b]
jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x09] jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x09]
jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09]
jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43]
lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7]
sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75]
swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30]