[X86][LLVM]Adding SMAP feature and test

[m_zuckerman]

Summary

Adding SMAP feature and test

lib/Target/X86/X86.td

def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
                                      "HasSlowDivide32", "true",
                                      "Use 8-bit divide for positive values less than 256">;
 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
                                      "HasSlowDivide64", "true",
                                      "Use 32-bit divide for positive values less than 2^32">;
 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
                                      "PadShortFunctions", "true",
                                      "Pad short functions">;
+def FeatureSMAP    : SubtargetFeature<"smap", "HasSMAP", "true",
+                                      "Supervisor Mode Access Protection">;
 def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
                                       "Enable Software Guard Extensions">;
 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
                                       "Flush A Cache Line Optimized">;
 def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
                                       "Cache Line Write Back">;
 // TODO: This feature ought to be renamed.
 // What it really refers to are CPUs for which certain instructions

lib/Target/X86/X86InstrInfo.td

 def NoBWI        : Predicate<"!Subtarget->hasBWI()">;
 def HasVLX       : Predicate<"Subtarget->hasVLX()">,
                      AssemblerPredicate<"FeatureVLX", "AVX-512 VL ISA">;
 def NoVLX        : Predicate<"!Subtarget->hasVLX()">;
 def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">;
 def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">;
 def PKU        : Predicate<"Subtarget->hasPKU()">;
 
+def hasSMAP      : Predicate<"Subtarget->hasSMAP()">,
+                   AssemblerPredicate<"FeatureSMAP","smap">;
 def HasPOPCNT    : Predicate<"Subtarget->hasPOPCNT()">;
 def HasAES       : Predicate<"Subtarget->hasAES()">;
 def HasFXSR      : Predicate<"Subtarget->hasFXSR()">;
 def HasXSAVE     : Predicate<"Subtarget->hasXSAVE()">;
 def HasXSAVEOPT  : Predicate<"Subtarget->hasXSAVEOPT()">;
 def HasXSAVEC    : Predicate<"Subtarget->hasXSAVEC()">;
 def HasXSAVES    : Predicate<"Subtarget->hasXSAVES()">;
 def HasPCLMUL    : Predicate<"Subtarget->hasPCLMUL()">;

lib/Target/X86/X86InstrSystem.td

def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
                 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
                 Requires<[Not64BitMode]>;
 def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
                 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
                 Requires<[In64BitMode]>;
 
 //===----------------------------------------------------------------------===//
 // SMAP Instruction
+let Predicates = [hasSMAP] in {
   let Defs = [EFLAGS] in {
     def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
     def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
   }
+}
 
 //===----------------------------------------------------------------------===//
 // SMX Instruction
 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
   def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, TB;
 }

lib/Target/X86/X86Subtarget.h

protected:
   bool HasVLX;
 
   /// Processor has PKU extenstions
   bool HasPKU;
 
   /// Processor supports MPX - Memory Protection Extensions
   bool HasMPX;
 
+  /// Processor has Supervisor Mode Access Protection
+  bool HasSMAP;
+
   /// Processor has Software Guard Extensions
   bool HasSGX;
 
   /// Processor supports Flush Cache Line instruction
   bool HasCLFLUSHOPT;
 
   /// Processor supports Cache Line Write Back instruction
   bool HasCLWB;
public:
   bool hasCDI() const { return HasCDI; }
   bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
   bool hasPFI() const { return HasPFI; }
   bool hasERI() const { return HasERI; }
   bool hasDQI() const { return HasDQI; }
   bool hasBWI() const { return HasBWI; }
   bool hasVLX() const { return HasVLX; }
   bool hasPKU() const { return HasPKU; }
+  bool hasSMAP() const {return HasSMAP; }
   bool hasMPX() const { return HasMPX; }
   bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
 
   bool isXRaySupported() const override { return is64Bit(); }
 
   bool isAtom() const { return X86ProcFamily == IntelAtom; }
   bool isSLM() const { return X86ProcFamily == IntelSLM; }
   bool useSoftFloat() const { return UseSoftFloat; }

test/MC/X86/X86_64-smap.s

+// RUN: llvm-mc -triple x86_64-unknown-unknown -mattr=+smap --show-encoding < %s | FileCheck --check-prefix=SMAP-ON %s
+// RUN: not llvm-mc -triple x86_64-unknown-unknown -mattr=-smap --show-encoding %s 2> %t
+// RUN: FileCheck --check-prefix=SMAP-OFF < %t %s
+
+ // SMAP-ON: clac
+ // SMAP-ON: encoding: [0x0f,0x01,0xca]
+ // SMAP-OFF: instruction requires: smap
+ clac
+
+ // SMAP-ON: stac
+ // SMAP-ON: encoding: [0x0f,0x01,0xcb]
+ // SMAP-OFF: instruction requires: smap
+ stac
+

test/MC/X86/x86-64.s

 // CHECK: sysexitl
 // CHECK: encoding: [0x0f,0x35]
 sysexitl
 
 // CHECK: sysexitq
 // CHECK: encoding: [0x48,0x0f,0x35]
 sysexitq
 
-// CHECK: clac
-// CHECK: encoding: [0x0f,0x01,0xca]
-clac
-
-// CHECK: stac
-// CHECK: encoding: [0x0f,0x01,0xcb]
-stac
-
 // CHECK: faddp %st(1)
 // CHECK: fmulp %st(1)
 // CHECK: fsubp %st(1)
 // CHECK: fsubrp %st(1)
 // CHECK: fdivp %st(1)
 // CHECK: fdivrp %st(1)
 faddp %st(0), %st(1)
 fmulp %st(0), %st(1)