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[X86] Improve 64-bit shifts on 32-bit targets (PR14593)

Authored by RKSimon on Jul 31 2016, 8:13 AM.



As discussed on PR14593, this patch adds support for lowering to SHLD/SHRD from the patterns generated by DAGTypeLegalizer::ExpandShiftWithKnownAmountBit.

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RKSimon updated this revision to Diff 66243.Jul 31 2016, 8:13 AM
RKSimon retitled this revision from to [X86] Improve 64-bit shifts on 32-bit targets (PR14593).
RKSimon updated this object.
RKSimon added reviewers: eli.friedman, bkramer, spatel.
RKSimon set the repository for this revision to rL LLVM.
RKSimon added a subscriber: llvm-commits.
eli.friedman edited edge metadata.Jul 31 2016, 8:51 AM

Might be nice to have a test which triggers this combine without going through legalization. (Should be possible, I think?)

28675 ↗(On Diff #66243)

Maybe it makes sense to split this into two separate if statements; one checking that the two outer shifts match, one checking that the inner shift is a shift by one. I found it a bit tricky to pick through. (I sort of wish we had an equivalent to IR pattern matching in SelectionDAG.)

majnemer added inline comments.
28675 ↗(On Diff #66243)

I actually worked on such a thing:

Think it makes sense for me to return to it?

RKSimon updated this revision to Diff 66245.Jul 31 2016, 11:07 AM
RKSimon edited edge metadata.

Updated based on Feedback

RKSimon added inline comments.Jul 31 2016, 11:13 AM
28675 ↗(On Diff #66245)

Possibly - I'm interested in being able to match a lot of DAGCombiner patterns for both scalar and vector types.

Currently, at best we only match vector types with 'splatted' constant values - being able to generalize this would be very useful, I've played with some basic all_of style approaches but nothing has been great.

Could your template patterns make this any easier?

eli.friedman accepted this revision.Jul 31 2016, 12:15 PM
eli.friedman edited edge metadata.


28679 ↗(On Diff #66245)

If DAGCombine doesn't transform Y+Y to Y<<1, it should. (instcombine definitely does this.) Not really important for now, though.

This revision is now accepted and ready to land.Jul 31 2016, 12:15 PM

Thanks Eli.

28679 ↗(On Diff #66245)

In the old codegen we were seeing code like 'leal (%edx,%edx), %eax' being lowered from shl( v, 1 ) IR.

eli.friedman added inline comments.Jul 31 2016, 12:49 PM
28679 ↗(On Diff #66245)

There's a pattern in which does a shift->add transform because it's more efficient on x86... but we want to keep the SelectionDAG in canonical form as long as possible.

This revision was automatically updated to reflect the committed changes.