AMDGPU: Unify MOVRELSOffset and MOVRELDOffset

[nhaehnle]

Summary

Previously, constant index insertelements would be turned into SI_INDIRECT_DST,
which is bound to prevent some optimization opportunities. Worse, it mislead
the heuristic that decides whether immediates should be lowered to S_MOV_B32
or V_MOV_B32 in a way that resulted in unnecessary v_readfirstlanes.

[arsenm]

LGTM. Just to be sure the constant indexed insert element still always emits an INSERT_SUBREG? I think I wasn't getting this before which is why the check was there

[michel.daenzer]

This breaks test/CodeGen/AMDGPU/llvm.SI.gather4.ll for me:

/home/daenzer/src/llvm-git/llvm/test/CodeGen/AMDGPU/llvm.SI.gather4.ll:472:9: error: expected string not found in input
;CHECK: v_readfirstlane_b32 s[[LO:[0-9]+]], v{{[0-9]+}}
        ^
<stdin>:1767:19: note: scanning from here
gather4_sgpr_bug: ; @gather4_sgpr_bug
                  ^
<stdin>:1782:2: note: possible intended match here
 v_add_f32_e32 v0, v0, v1
 ^

[nhaehnle]

Yeah, that's an interaction with the recent D22210 (I wrote the patches in the other order). I'll fix it before committing.

llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

private:
   bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
                   bool &Imm) const;
   bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
   bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
   bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
   bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const;
   bool SelectSMRDBufferImm32(SDValue Addr, SDValue &Offset) const;
   bool SelectSMRDBufferSgpr(SDValue Addr, SDValue &Offset) const;
-  bool selectMOVRELOffsetImpl(SDValue Index, SDValue &Base,
-                              SDValue &Offset, bool IsInsert) const;
-  bool selectMOVRELSOffset(SDValue Index, SDValue &Base, SDValue &Offset) const;
-  bool selectMOVRELDOffset(SDValue Index, SDValue &Base, SDValue &Offset) const;
+  bool SelectMOVRELOffset(SDValue Index, SDValue &Base, SDValue &Offset) const;
   bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
   bool SelectVOP3NoMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
   bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
                        SDValue &Clamp, SDValue &Omod) const;
   bool SelectVOP3NoMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
                          SDValue &Clamp, SDValue &Omod) const;
 
   bool SelectVOP3Mods0Clamp(SDValue In, SDValue &Src, SDValue &SrcMods,

 
 bool AMDGPUDAGToDAGISel::SelectSMRDBufferSgpr(SDValue Addr,
                                               SDValue &Offset) const {
   bool Imm;
   return SelectSMRDOffset(Addr, Offset, Imm) && !Imm &&
          !isa<ConstantSDNode>(Offset);
 }
 
-bool AMDGPUDAGToDAGISel::selectMOVRELOffsetImpl(SDValue Index,
-                                                SDValue &Base,
-                                                SDValue &Offset,
-                                                bool IsInsert) const {
+bool AMDGPUDAGToDAGISel::SelectMOVRELOffset(SDValue Index,
+                                            SDValue &Offset) const {
   SDLoc DL(Index);
 
   if (CurDAG->isBaseWithConstantOffset(Index)) {
     SDValue N0 = Index.getOperand(0);
     SDValue N1 = Index.getOperand(1);
     ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
 
     // (add n0, c0)
     Base = N0;
     Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32);
     return true;
   }
 
-  if (IsInsert) {
-    if (ConstantSDNode *CBase = dyn_cast<ConstantSDNode>(Index)) {
-      Base = CurDAG->getRegister(AMDGPU::NoRegister, MVT::i32);
-      Offset = CurDAG->getTargetConstant(CBase->getZExtValue(), DL, MVT::i32);
-      return true;
-    }
-  } else {
-    if (isa<ConstantSDNode>(Index))
-      return false;
-  }
 
   Base = Index;
   Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
   return true;
 }
 
-bool AMDGPUDAGToDAGISel::selectMOVRELSOffset(SDValue Index,
-                                             SDValue &Base,
-                                             SDValue &Offset) const {
-  return selectMOVRELOffsetImpl(Index, Base, Offset, false);
-}
-
-bool AMDGPUDAGToDAGISel::selectMOVRELDOffset(SDValue Index,
-                                             SDValue &Base,
-                                             SDValue &Offset) const {
-  return selectMOVRELOffsetImpl(Index, Base, Offset, true);
-}
-
 SDNode *AMDGPUDAGToDAGISel::getS_BFE(unsigned Opcode, const SDLoc &DL,
                                      SDValue Val, uint32_t Offset,
                                      uint32_t Width) {
   // Transformation function, pack the offset and width of a BFE into
   // the format expected by the S_BFE_I32 / S_BFE_U32. In the second
   // source, bits [5:0] contain the offset and bits [22:16] the width.
   uint32_t PackedVal = Offset | (Width << 16);
   SDValue PackedConst = CurDAG->getTargetConstant(PackedVal, DL, MVT::i32);

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td

 
 def SMRDImm   : ComplexPattern<i64, 2, "SelectSMRDImm">;
 def SMRDImm32 : ComplexPattern<i64, 2, "SelectSMRDImm32">;
 def SMRDSgpr  : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
 def SMRDBufferImm   : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
 def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
 def SMRDBufferSgpr  : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">;
 
-def MOVRELSOffset : ComplexPattern<i32, 2, "selectMOVRELSOffset">;
-def MOVRELDOffset : ComplexPattern<i32, 2, "selectMOVRELDOffset">;
+def MOVRELOffset : ComplexPattern<i32, 2, "SelectMOVRELOffset">;
 
 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
 def VOP3NoMods0 : ComplexPattern<untyped, 4, "SelectVOP3NoMods0">;
 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
 def VOP3Mods  : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
 def VOP3NoMods : ComplexPattern<untyped, 2, "SelectVOP3NoMods">;
 

llvm/trunk/lib/Target/AMDGPU/SIInstructions.td

 
 /********** ====================== **********/
 /**********   Indirect adressing   **********/
 /********** ====================== **********/
 
 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> {
   // Extract with offset
   def : Pat<
-    (eltvt (extractelt vt:$src, (MOVRELSOffset i32:$idx, (i32 imm:$offset)))),
+    (eltvt (extractelt vt:$src, (MOVRELOffset i32:$idx, (i32 imm:$offset)))),
     (!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $src, $idx, imm:$offset)
   >;
 
   // Insert with offset
   def : Pat<
-    (insertelt vt:$src, eltvt:$val, (MOVRELDOffset i32:$idx, (i32 imm:$offset))),
+    (insertelt vt:$src, eltvt:$val, (MOVRELOffset i32:$idx, (i32 imm:$offset))),
     (!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $src, $idx, imm:$offset, $val)
   >;
 }
 
 defm : SI_INDIRECT_Pattern <v2f32, f32, "V2">;
 defm : SI_INDIRECT_Pattern <v4f32, f32, "V4">;
 defm : SI_INDIRECT_Pattern <v8f32, f32, "V8">;
 defm : SI_INDIRECT_Pattern <v16f32, f32, "V16">;

llvm/trunk/test/CodeGen/AMDGPU/insert_vector_elt.ll

 
 ; GCN-LABEL: {{^}}insertelement_v3f32_3:
 define void @insertelement_v3f32_3(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind {
   %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 3
   store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
   ret void
 }
 
+; GCN-LABEL: {{^}}insertelement_to_sgpr:
+; GCN-NOT: v_readfirstlane
+define amdgpu_ps <4 x float> @insertelement_to_sgpr() nounwind {
+  %tmp = load <4 x i32>, <4 x i32> addrspace(2)* undef
+  %tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 0
+  %tmp2 = call <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> %tmp1, i32 8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
+  ret <4 x float> %tmp2
+}
+
 ; GCN-LABEL: {{^}}dynamic_insertelement_v2f32:
 ; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000
 ; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]]
 ; GCN: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]:
 define void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, i32 %b) nounwind {
   %vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 %b
   store <2 x float> %vecins, <2 x float> addrspace(1)* %out, align 8
   ret void

 ; GCN: buffer_store_dwordx4
 ; GCN: s_endpgm
 ; GCN: ScratchSize: 128
 define void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, i32 %b) nounwind {
   %vecins = insertelement <8 x double> %a, double 8.0, i32 %b
   store <8 x double> %vecins, <8 x double> addrspace(1)* %out, align 16
   ret void
 }
+
+declare <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) nounwind readnone

llvm/trunk/test/CodeGen/AMDGPU/llvm.SI.gather4.ll

main_body:
   ret void
 }
 
 ;CHECK-LABEL: {{^}}gather4_sgpr_bug:
 ;
 ; This crashed at some point due to a bug in FixSGPRCopies. Derived from the
 ; report in https://bugs.freedesktop.org/show_bug.cgi?id=96877
 ;
-;TODO: the readfirstlanes are unnecessary, see http://reviews.llvm.org/D22217
-;
-;CHECK: v_readfirstlane_b32 s[[LO:[0-9]+]], v{{[0-9]+}}
-;CHECK: v_readfirstlane_b32
-;CHECK: v_readfirstlane_b32
-;CHECK: v_readfirstlane_b32 s[[HI:[0-9]+]], v{{[0-9]+}}
+;CHECK: s_load_dwordx4 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0
+;CHECK: s_waitcnt lgkmcnt(0)
+;CHECK: s_mov_b32 s[[LO]], 0
 ;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, s{{\[}}[[LO]]:[[HI]]] dmask:0x8
 define amdgpu_ps float @gather4_sgpr_bug() {
 main_body:
   %tmp = load <4 x i32>, <4 x i32> addrspace(2)* undef, align 16
   %tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 0
   %tmp2 = call <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> %tmp1, i32 8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
   %tmp4 = extractelement <4 x float> %tmp2, i32 1
   %tmp9 = fadd float undef, %tmp4