[LLD][ARM] Thunk support framework for ARM and Mips

[peter.smith]

Summary

Add Thunk support framework for ARM and Mips

Generalise the Mips LA25 Thunk code and implement ARM and Thumb interworking Thunks.

• Introduce a new module Thunks.cpp to store the mapping between SymbolBody and Thunk
• SymbolBody now has no Thunk specific fields
• A Target can more easily have more than one type of Thunk
• Support PC-relative calls to Thunks
• Support Thunks to PLT entries
• Existing Mips LA25 Thunk code integrated with no change in behaviour
• Support for ARMv7A interworking Thunks
• Added pc-relative versions of MOVT/MOVW relocations needed by ARM Thunks
• Tests for new functionality added.

Limitations:

• Only one Thunk per SymbolBody, this is sufficient for all currently implemented Thunks.
• ARM thunks assume presence of V6T2 MOVT and MOVW instructions.

Notes for reviewers:

• It is just about possible to implement ARM/Thumb interworking Thunks in the same framework as the Mips LA25 Thunks. However this does mean adding new fields in RegularSymbol and SharedSymbol to record information about the InputSection that the Thunk will be written to. Given that the majority of Symbols even in ARM will have no Thunks I thought it better to move the Thunk information away from SymbolBody.
• The code in Thunk.cpp could be moved into Target.cpp although if the ThunkInfo class were merged into TargetInfo it would mean templating TargetInfo with ELFT. I also thought that the Thunk code was less interesting to Targets other than ARM or Mips.
• In this patch I've chosen to keep the Mips Thunk code in Target undisturbed rather than moving it into Thunks.cpp. This is partly due to the MipsTargetInfo<ELFT>::writeThunk member function calling local static functions in Target.cpp. It also means less rework if Thunks.cpp isn't the right design.
• Most of the other changes are moving existing code around to deal with the Thunks module.
• I think that the implementation can be extended to cope with range-extension Thunks. In summary a SymbolBody will map to multiple Thunks, a caller will select the most appropriate Thunk out of the possible candidates.

[ruiu]

ELF/InputSection.cpp

142–145

total -> Total

ELF/Thunks.cpp

47

In general, the class hierarchy defined in this file looks too deep. Please move more features to "leaf" classes to reduce number of classes.

ELF/Thunks.h

32–34

I think this class does not have to be a class. It can be a non-member function instead.

[ruiu]

ELF/Thunks.cpp

45

Add a newline.

344

What is this for? If you don't need this now, please remove.

348–355

We want to group them by class by convention.

template class ThunkInfo<ELF32LE>;
template class ThunkInfo<ELF32BE>;
template class ThunkInfo<ELF64LE>;
template class ThunkInfo<ELF64BE>;

template ThunkInfo<ELF32LE> *createThunkInfo<ELF32LE>();
template ThunkInfo<ELF32BE> *createThunkInfo<ELF32BE>();
template ThunkInfo<ELF64LE> *createThunkInfo<ELF64LE>();
template ThunkInfo<ELF64BE> *createThunkInfo<ELF64BE>();

ELF/Thunks.h

23

This is a good place to describe the class a bit more in detail.

// Class to describe an instance of a Thunk. Thunks are pieces of data
// that are attached to input sections. MIPS and ARM needs them to
// place small pieces of code for function calls that cannot directly be called.

40

Add a newline before this line.

45

Ditto

ELF/Writer.cpp

25 ↗

(On Diff #62351)

Remove.

[peter.smith]

Thank you very much for the comments. Apologies for the delay in responding.

Changes:

• Made all formatting suggestions.
• Added some more comments describing classes.
• Flattened the class hierarchy to two levels.
• Only Thunk::getVA() was being used after a call to getThunk(S) so I simplified to getThunkVA(S).

I've put some further explanations as response to comments.

[ruiu]

ELF/Thunks.h

81

What's the reason to manage thunks separately from SymbolBodies? It seems you can add a new member to the symbol to store a thunk.

[ruiu]

ELF/Thunks.cpp

295–296

This should be a fatal(), no?

[peter.smith]

I've added some inline responses to comments.

ELF/InputSection.cpp

142–145

Ok, made change.

ELF/Thunks.cpp

45

Ok, have made change.

47

I've squashed the hierarchy down to two levels. This has meant moving some of the implementation details into the header file. Given that the implementation details moved are not target specific, this is probably better than duplicating functionality in the leaf classes.

295–296

Currently the ThunkInfo() implementation of adjustExprForThunk() is needed to return the expression unaltered. If adjustExprForThunk() were either removed from the class or guarded by something like Target->needsThunk() then creating ThunkInfo would not be needed and this would indeed be fatal.

344

It is needed so that a Target that doesn't need thunks always returns the same RelExpr in adjustExprForThunk(). I've flattened the hierarchy so that ThunkInfoBase is no longer required, but I've kept the ThunkInfo for the moment.

The alternative is to move adjustExprFOrThunk out of the ThunkInfo class, perhaps into TargetInfo? This would mean that only ARM and Mips would create an object but would mean that code very similar to the other Thunks is spread out over two files. Let me know if you'd prefer that?

348–355

Ok, have made change.

ELF/Thunks.h

23

Ok, have added some more comments.

32–34

I'm not sure about this yet. With the class hierarchy flattening I've moved some more information into the header files to remove the need for an intermediate layer so this might be a bit clearer why it is a class.

I think it could be done, with non-member functions forwarding to a class internal to Thunks.cpp. The bit I'm not happy about yet is the initialisation and finalisation of the persistent state. I can give this another try next week if you think it is important.

40

Ok, have made change.

45

Ok, have made change.

81

My reasons for separating out thunks:

• Avoiding adding a field for all symbols when only a small proportion need thunks, and only for targets that need thunks.
• Thunk field either has to go in both Shared (thunks to PLT imports) and DefinedRegular or in their shared ancestor Defined. The former means casting to the appropriate Defined sub-class when accessing the thunk and the latter puts a field only needed by a small proportion of symbols into most of them. Neither of these options felt attractive.
• Range extension thunks will need to support multiple thunks per symbol, a container of thunks, or a pointer to one may not as acceptable.

I don't think any of these are especially strong arguments right now although I think we'll end up separating thunks when multiple thunks per symbol are needed.

ELF/Writer.cpp

25 ↗

(On Diff #62351)

Ok, have made change.

[peter.smith]

I had a go at implementing interworking thunks by storing the pointer to Thunk in the Symbol. I think that this simplifies the implementation enough to be worth doing. The implementation can be revisited when range extension thunks are implemented.

Changes:

• Removed ThunkInfo class and its sub-classes
• Moved adjustExprForThunk into TargetInfo
• Shared and DefinedRegular have a pointer to their Thunk

[ruiu]

I think this is in general looking good. My comments are mostly on style.

ELF/Symbols.h

238

Please use C++11 member initialization.

std::unique_ptr<Thunk<ELFT>> Alt = nullptr;

I don't think Alt is a good name because there are a lot of things associated to symbols that can be called "alt" such as PLT, GOT or copy relocations, etc. Because Thunk is a class name, we can't use the same name, so I don't have a good suggestion. Maybe ThunkData or ThunkObj?

ELF/Target.cpp

1566

Remove else because it is after return.

1956–1960

Can you define variables for the boolean values?

ELFFile<ELFT> &File = D->Section->getFile()->getObj();
bool PicFile = File->e_flags & EF_MIPS_PIC;
bool PicSym = (D->StOther & STO_MIPS_MIPS16) == STO_MIPS_PIC;
return (PicFile || PicSym) ? R_THUNK_ABS : Expr;

ELF/Target.h

60–61

You can remove thunkSize member function from all Targets and return 16 from MipsThunk<ELFT>::size().

ELF/Thunks.cpp

50

ARMThunkDestVA -> armThunkDestVA (or getARMThunkDestVA) because function names should start with lowercase letters.

57

Please enclose the class definitions in this file with an anonymous namespace.

59

We omit virtual if override is given.

59–60

I'd put a blank line between them.

70–71

Ditto

163

armAddThunk (or addThunkARM or anything that starts with a lowercase letter.)

202

Error messages should start with lowercase letters.

205

Lowercase.

224

llvm_unreachable is better because it is unreacahable unless there is a bug in LLD's code. The general guideline is

• if it is unreachable unless there is a programmer's error, llvm_unreachable (or assert)
• if it is unreachable unless input files are corrupted, fatal
• otherwise, error.

227–239

I don't think you need to instantiate these templates because no other compilation units use them.

241–248

Nit: we omit parameter names in template instantiation. E.g.

template void AddThunk<ELF64BE>(uint32_t, SymbolBody &,
                                InputSection<ELF64BE> &);

ELF/Thunks.h

52

AddThunk -> addThunk

[ruiu]

ELF/Thunks.h

37

You don't redefine this function in a derived class, so please remove virtual.

[ruiu]

ELF/Thunks.h

15

You can remove this #include.

test/ELF/arm-thumb-interwork-thunk.s

82–86

Remove trailing whitespaces.

[peter.smith]

Thanks again for the review comments. I've updated the diff to hopefully cover all raised so far.

[ruiu]

ELF/InputSection.cpp

133

Ditto.

190–194

I think you want to add A.

ELF/InputSection.h

213

Parameters need to be in camel case as a rule, so thunk is not okay. In this context, I'd just name this T.

ELF/Relocations.cpp

608

AddThunk -> addThunk

ELF/Symbols.h

238

I noticed that you can remove = nullptr as a std::unique_ptr is initialized to a nullptr by default.

314

Ditto

ELF/Target.cpp

185–187

Because we already have getRelExpr, I'd name this getThunkExpr. I believe existing adjust* functions have side effects (mutates parameters) which is different from this function.

ELF/Thunks.cpp

101

What's the naming convention in this file? This class is named ThumbARM but the other classes are named ARMThumb. Can you rename this ARMThumbV7ABSLongThunk?

122

Ditto

229

AddThunk -> addThunk (all function names need to start with lowercase letters.)

235

Remove \n. A newline is automatically appended.

ELF/Thunks.h

15

Remove this #include because it's unused.

[peter.smith]

Thank you for the extra comments. I've updated diff to hopefully address the most recent comments.

[peter.smith]

Adding llvm-commits to subscribers. My apologies for forgetting to put this on earlier.

ELF/InputSection.cpp

133

Made corresponding change.

190–194

The A wasn't in the original Mips R_THUNK, I didn't change it just in case it was deliberate. Adding it doesn't cause the mips test to fail, presumably as the addend for jump instruction will be 0. Given that this has been generalised I've added the A.

ELF/InputSection.h

213

Ok, made change to T.

ELF/Relocations.cpp

608

Ok, made change.

ELF/Symbols.h

238

Agreed, I used Alt as short for alternative. I've gone with ThunkData.

238

Ok, made change.

314

Ok, made change.

ELF/Target.cpp

185–187

Ok, I've made the change. I chose adjustThunkExpr to follow adjustRelaxExpr which also doesn't mutate its parameters.

1566

Ok, made change.

1956–1960

Ok, made very similar change to above.

ELF/Thunks.cpp

50

Ok, made change to getARMThunkDestVA

57

Ok, made change.

59

Ok, removed all virtual keywords where override is also present.

59–60

Ok, made change.

70–71

Have added a blank line between all similar cases.

101

There is a comment above:
Specific ARM Thunk implementations. The naming convention is:
Source State, TargetState, Target Requirement, ABS or PI, Range

I've added a "To" in between ARMThumb and ThumbARM to make this clearer: For example the classes are now:
ARMToThumbV7ABSLongThunk and ThumbToARMV7ABSLongThunk

122

Should be addressed by the naming convention comment above.

163

Ok, have gone with addThunkARM.

202

Ok, made change.

205

Used addThunkMips and made static to match addThunkARM

224

Ok, have used llvm_unreachable in this case.

227–239

Yes you are right, I've removed them.

229

Ok, made change.

I thought that in the original review comment AddThunk being globally visible had a different convention.

235

Ok, made change.

241–248

Ok removed parameter names.

ELF/Thunks.h

15

Ok, have made the change.

37

Ok, done.

test/ELF/arm-thumb-interwork-thunk.s

82–86

Ok, done, apologies that those slipped through.

[ruiu]

LGTM

[peter.smith]

Committed -r 274863 closing this revision.

ELF/CMakeLists.txt

add_lld_library(lldELF
   OutputSections.cpp
   Relocations.cpp
   ScriptParser.cpp
   Strings.cpp
   SymbolListFile.cpp
   SymbolTable.cpp
   Symbols.cpp
   Target.cpp
+  Thunks.cpp
   Writer.cpp
 
   LINK_COMPONENTS
   ${LLVM_TARGETS_TO_BUILD}
   Analysis
   BitReader
   BitWriter
   Codegen

ELF/InputSection.h

 //===- InputSection.h -------------------------------------------*- C++ -*-===//
 //
 //                             The LLVM Linker
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLD_ELF_INPUT_SECTION_H
 #define LLD_ELF_INPUT_SECTION_H
 
 #include "Config.h"
 #include "Relocations.h"
+#include "Thunks.h"
 #include "lld/Core/LLVM.h"
 #include "llvm/ADT/DenseSet.h"
 #include "llvm/ADT/TinyPtrVector.h"
 #include "llvm/Object/ELF.h"
 
 namespace lld {
 namespace elf {
 
public:
   uint64_t OutSecOff = 0;
 
   static bool classof(const InputSectionBase<ELFT> *S);
 
   InputSectionBase<ELFT> *getRelocatedSection();
 
   // Register thunk related to the symbol. When the section is written
   // to a mmap'ed file, target is requested to write an actual thunk code.
-  // Now thunks is supported for MIPS target only.
-  void addThunk(SymbolBody &Body);
+  // Now thunks is supported for MIPS and ARM target only.
+  void addThunk(const Thunk<ELFT> *T);
 
   // The offset of synthetic thunk code from beginning of this section.
   uint64_t getThunkOff() const;
 
   // Size of chunk with thunks code.
   uint64_t getThunksSize() const;
 
   template <class RelTy>
   void relocateNonAlloc(uint8_t *Buf, llvm::ArrayRef<RelTy> Rels);
 
 private:
   template <class RelTy>
   void copyRelocations(uint8_t *Buf, llvm::ArrayRef<RelTy> Rels);
 
   // Called by ICF to merge two input sections.
   void replace(InputSection<ELFT> *Other);
 
   // Used by ICF.
   uint64_t GroupId = 0;
 
-  llvm::TinyPtrVector<const SymbolBody *> Thunks;
+  llvm::TinyPtrVector<const Thunk<ELFT> *> Thunks;
 };
 
 // MIPS .reginfo section provides information on the registers used by the code
 // in the object file. Linker should collect this information and write a single
 // .reginfo section in the output file. The output section contains a union of
 // used registers masks taken from input .reginfo sections and final value
 // of the `_gp` symbol.  For details: Chapter 4 / "Register Information" at
 // ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf

ELF/InputSection.cpp

 //===- InputSection.cpp ---------------------------------------------------===//
 //
 //                             The LLVM Linker
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "InputSection.h"
 #include "Config.h"
 #include "EhFrame.h"
 #include "Error.h"
 #include "InputFiles.h"
 #include "OutputSections.h"
 #include "Target.h"
+#include "Thunks.h"
 
 #include "llvm/Support/Compression.h"
 #include "llvm/Support/Endian.h"
 
 using namespace llvm;
 using namespace llvm::ELF;
 using namespace llvm::object;
 using namespace llvm::support::endian;

 
 template <class ELFT>
 InputSectionBase<ELFT> *InputSection<ELFT>::getRelocatedSection() {
   assert(this->Header->sh_type == SHT_RELA || this->Header->sh_type == SHT_REL);
   ArrayRef<InputSectionBase<ELFT> *> Sections = this->File->getSections();
   return Sections[this->Header->sh_info];
 }
 
-template <class ELFT> void InputSection<ELFT>::addThunk(SymbolBody &Body) {
-  Body.ThunkIndex = Thunks.size();
-  Thunks.push_back(&Body);
+template <class ELFT>
+void InputSection<ELFT>::addThunk(const Thunk<ELFT> *T) {
+  Thunks.push_back(T);
 }
 
 template <class ELFT> uint64_t InputSection<ELFT>::getThunkOff() const {
   return this->Header->sh_size;
 }
 
 template <class ELFT> uint64_t InputSection<ELFT>::getThunksSize() const {
-  return Thunks.size() * Target->ThunkSize;
+  uint64_t Total = 0;
+  for (const Thunk<ELFT> *T : Thunks)
+    Total += T->size();
+  return Total;
 }
 
 // This is used for -r. We can't use memcpy to copy relocations because we need
 // to update symbol table offset and section index for each relocation. So we
 // copy relocations one by one.
 template <class ELFT>
 template <class RelTy>
 void InputSection<ELFT>::copyRelocations(uint8_t *Buf, ArrayRef<RelTy> Rels) {
getSymVA(uint32_t Type, typename ELFT::uint A, typename ELFT::uint P,
   switch (Expr) {
   case R_HINT:
     llvm_unreachable("cannot relocate hint relocs");
   case R_TLSLD:
     return Out<ELFT>::Got->getTlsIndexOff() + A -
            Out<ELFT>::Got->getNumEntries() * sizeof(uintX_t);
   case R_TLSLD_PC:
     return Out<ELFT>::Got->getTlsIndexVA() + A - P;
-  case R_THUNK:
-    return Body.getThunkVA<ELFT>();
+  case R_THUNK_ABS:
+    return Body.getThunkVA<ELFT>() + A;
+  case R_THUNK_PC:
+  case R_THUNK_PLT_PC:
+    return Body.getThunkVA<ELFT>() + A - P;
   case R_PPC_TOC:
     return getPPC64TocBase() + A;
   case R_TLSGD:
     return Out<ELFT>::Got->getGlobalDynOffset(Body) + A -
            Out<ELFT>::Got->getNumEntries() * sizeof(uintX_t);
   case R_TLSGD_PC:
     return Out<ELFT>::Got->getGlobalDynAddr(Body) + A - P;
   case R_TLSDESC:
template <class ELFT> void InputSection<ELFT>::writeTo(uint8_t *Buf) {
 
   // The section might have a data/code generated by the linker and need
   // to be written after the section. Usually these are thunks - small piece
   // of code used to jump between "incompatible" functions like PIC and non-PIC
   // or if the jump target too far and its address does not fit to the short
   // jump istruction.
   if (!Thunks.empty()) {
     Buf += OutSecOff + getThunkOff();
-    for (const SymbolBody *S : Thunks) {
-      Target->writeThunk(Buf, S->getVA<ELFT>());
-      Buf += Target->ThunkSize;
+    for (const Thunk<ELFT> *T : Thunks) {
+      T->writeTo(Buf);
+      Buf += T->size();
     }
   }
 }
 
 template <class ELFT>
 void InputSection<ELFT>::replace(InputSection<ELFT> *Other) {
   this->Alignment = std::max(this->Alignment, Other->Alignment);
   Other->Repl = this->Repl;

ELF/Relocations.h

enum RelExpr {
   R_RELAX_TLS_GD_TO_IE_END,
   R_RELAX_TLS_GD_TO_IE_ABS,
   R_RELAX_TLS_GD_TO_IE_PAGE_PC,
   R_RELAX_TLS_GD_TO_LE,
   R_RELAX_TLS_GD_TO_LE_NEG,
   R_RELAX_TLS_IE_TO_LE,
   R_RELAX_TLS_LD_TO_LE,
   R_SIZE,
-  R_THUNK,
+  R_THUNK_ABS,
+  R_THUNK_PC,
+  R_THUNK_PLT_PC,
   R_TLS,
   R_TLSDESC,
   R_TLSDESC_PAGE,
   R_TLSGD,
   R_TLSGD_PC,
   R_TLSLD,
   R_TLSLD_PC
 };

ELF/Relocations.cpp

 //
 //===----------------------------------------------------------------------===//
 
 #include "Relocations.h"
 #include "Config.h"
 #include "OutputSections.h"
 #include "SymbolTable.h"
 #include "Target.h"
+#include "Thunks.h"
 
 #include "llvm/Support/Endian.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 using namespace llvm::ELF;
 using namespace llvm::object;
 using namespace llvm::support::endian;
if (Body.isUndefined())
     return !Body.isLocal() && Body.symbol()->isWeak();
   if (const auto *DR = dyn_cast<DefinedRegular<ELFT>>(&Body))
     return DR->Section == nullptr; // Absolute symbol.
   return false;
 }
 
 static bool needsPlt(RelExpr Expr) {
   return Expr == R_PLT_PC || Expr == R_PPC_PLT_OPD || Expr == R_PLT ||
-         Expr == R_PLT_PAGE_PC;
+         Expr == R_PLT_PAGE_PC || Expr == R_THUNK_PLT_PC;
 }
 
 // True if this expression is of the form Sym - X, where X is a position in the
 // file (PC, or GOT for example).
 static bool isRelExpr(RelExpr Expr) {
   return Expr == R_PC || Expr == R_GOTREL || Expr == R_PAGE_PC ||
-         Expr == R_RELAX_GOT_PC;
+         Expr == R_RELAX_GOT_PC || Expr == R_THUNK_PC || Expr == R_THUNK_PLT_PC;
 }
 
 template <class ELFT>
 static bool isStaticLinkTimeConstant(RelExpr E, uint32_t Type,
                                      const SymbolBody &Body) {
   // These expressions always compute a constant
   if (E == R_SIZE || E == R_GOT_FROM_END || E == R_GOT_OFF ||
       E == R_MIPS_GOT_LOCAL_PAGE || E == R_MIPS_GOT_OFF || E == R_MIPS_TLSGD ||
       E == R_GOT_PAGE_PC || E == R_GOT_PC || E == R_PLT_PC || E == R_TLSGD_PC ||
-      E == R_TLSGD || E == R_PPC_PLT_OPD || E == R_TLSDESC_PAGE || E == R_HINT)
+      E == R_TLSGD || E == R_PPC_PLT_OPD || E == R_TLSDESC_PAGE ||
+      E == R_HINT || E == R_THUNK_PC || E == R_THUNK_PLT_PC)
     return true;
 
   // These never do, except if the entire file is position dependent or if
   // only the low bits are used.
   if (E == R_GOT || E == R_PLT || E == R_TLSDESC)
     return Target->usesOnlyLowPageBits(Type) || !Config->Pic;
 
   if (isPreemptible(Body, Type))
template <class ELFT> static void addCopyRelSymbol(SharedSymbol<ELFT> *SS) {
   Out<ELFT>::RelaDyn->addReloc(
       {Target->CopyRel, Out<ELFT>::Bss, SS->OffsetInBss, false, SS, 0});
 }
 
 template <class ELFT>
 static RelExpr adjustExpr(const elf::ObjectFile<ELFT> &File, SymbolBody &Body,
                           bool IsWrite, RelExpr Expr, uint32_t Type,
                           const uint8_t *Data) {
-  if (Target->needsThunk(Type, File, Body))
-    return R_THUNK;
   bool Preemptible = isPreemptible(Body, Type);
   if (Body.isGnuIFunc()) {
     Expr = toPlt(Expr);
   } else if (!Preemptible) {
     if (needsPlt(Expr))
       Expr = fromPlt(Expr);
     if (Expr == R_GOT_PC)
       Expr = Target->adjustRelaxExpr(Type, Data, Expr);
   }
+  Expr = Target->getThunkExpr(Expr, Type, File, Body);
 
   if (IsWrite || isStaticLinkTimeConstant<ELFT>(Expr, Type, Body))
     return Expr;
 
   // This relocation would require the dynamic linker to write a value to read
   // only memory. We can hack around it if we are producing an executable and
   // the refered symbol can be preemepted to refer to the executable.
   if (Config->Shared || (Config->Pic && !isRelExpr(Expr))) {
if (unsigned Processed = handleTlsRelocation<ELFT>(
       I += (Processed - 1);
       continue;
     }
 
     // Ignore "hint" relocation because it is for optional code optimization.
     if (Expr == R_HINT)
       continue;
 
-    if (needsPlt(Expr) || Expr == R_THUNK || refersToGotEntry(Expr) ||
+    if (needsPlt(Expr) || Expr == R_THUNK_ABS || Expr == R_THUNK_PC ||
+        Expr == R_THUNK_PLT_PC || refersToGotEntry(Expr) ||
         !isPreemptible(Body, Type)) {
       // If the relocation points to something in the file, we can process it.
       bool Constant = isStaticLinkTimeConstant<ELFT>(Expr, Type, Body);
 
       // If the output being produced is position independent, the final value
       // is still not known. In that case we still need some help from the
       // dynamic linker. We can however do better than just copying the incoming
       // relocation. We can process some of it and and just ask the dynamic
if (needsPlt(Expr) || Expr == R_THUNK_ABS || Expr == R_THUNK_PC ||
       // ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf p.4-19
       if (Config->EMachine == EM_MIPS)
         Out<ELFT>::Got->addMipsEntry(Body, Addend, Expr);
       continue;
     }
 
     // Some targets might require creation of thunks for relocations.
     // Now we support only MIPS which requires LA25 thunk to call PIC
-    // code from non-PIC one.
-    if (Expr == R_THUNK) {
-      if (!Body.hasThunk()) {
-        auto *Sec = cast<InputSection<ELFT>>(
-            cast<DefinedRegular<ELFT>>(&Body)->Section);
-        Sec->addThunk(Body);
-      }
-      continue;
+    // code from non-PIC one, and ARM which requires interworking.
+    if (Expr == R_THUNK_ABS || Expr == R_THUNK_PC || Expr == R_THUNK_PLT_PC) {
+      auto *Sec = cast<InputSection<ELFT>>(&C);
+      addThunk<ELFT>(Type, Body, *Sec);
     }
 
     // At this point we are done with the relocated position. Some relocations
     // also require us to create a got or plt entry.
 
     // If a relocation needs PLT, we create a PLT and a GOT slot for the symbol.
     if (needsPlt(Expr)) {
       if (Body.isInPlt())

ELF/Symbols.h

public:
   }
 
   uint8_t getVisibility() const { return StOther & 0x3; }
 
   unsigned DynsymIndex = 0;
   uint32_t GotIndex = -1;
   uint32_t GotPltIndex = -1;
   uint32_t PltIndex = -1;
-  uint32_t ThunkIndex = -1;
   uint32_t GlobalDynIndex = -1;
   bool isInGot() const { return GotIndex != -1U; }
   bool isInPlt() const { return PltIndex != -1U; }
-  bool hasThunk() const { return ThunkIndex != -1U; }
+  template <class ELFT> bool hasThunk() const;
 
   template <class ELFT>
   typename ELFT::uint getVA(typename ELFT::uint Addend = 0) const;
 
   template <class ELFT> typename ELFT::uint getGotOffset() const;
   template <class ELFT> typename ELFT::uint getGotVA() const;
   template <class ELFT> typename ELFT::uint getGotPltOffset() const;
   template <class ELFT> typename ELFT::uint getGotPltVA() const;
public:
   // The input section this symbol belongs to. Notice that this is
   // a reference to a pointer. We are using two levels of indirections
   // because of ICF. If ICF decides two sections need to be merged, it
   // manipulates this Section pointers so that they point to the same
   // section. This is a bit tricky, so be careful to not be confused.
   // If this is null, the symbol is an absolute symbol.
   InputSectionBase<ELFT> *&Section;
 
+  // If non-null the symbol has a Thunk that may be used as an alternative
+  // destination for callers of this Symbol.
+  std::unique_ptr<Thunk<ELFT>> ThunkData;
+
 private:
   static InputSectionBase<ELFT> *NullInputSection;
 };
 
 template <class ELFT>
 InputSectionBase<ELFT> *DefinedRegular<ELFT>::NullInputSection;
 
 // DefinedSynthetic is a class to represent linker-generated ELF symbols.
public:
   const Elf_Sym &Sym;
 
   // This field is a pointer to the symbol's version definition.
   const Elf_Verdef *Verdef;
 
   // OffsetInBss is significant only when needsCopy() is true.
   uintX_t OffsetInBss = 0;
 
+  // If non-null the symbol has a Thunk that may be used as an alternative
+  // destination for callers of this Symbol.
+  std::unique_ptr<Thunk<ELFT>> ThunkData;
   bool needsCopy() const { return this->NeedsCopyOrPltAddr && !this->isFunc(); }
 };
 
 // This class represents a symbol defined in an archive file. It is
 // created from an archive file header, and it knows how to load an
 // object file from an archive to replace itself with a defined
 // symbol. If the resolver finds both Undefined and Lazy for
 // the same name, it will ask the Lazy to load a file.

ELF/Symbols.cpp

bool SymbolBody::isPreemptible() const {
 
   // Normally only default visibility symbols can be preempted, but -Bsymbolic
   // means that not even they can be preempted.
   if (Config->Bsymbolic || (Config->BsymbolicFunctions && isFunc()))
     return !isDefined();
   return symbol()->Visibility == STV_DEFAULT;
 }
 
+template <class ELFT> bool SymbolBody::hasThunk() const {
+  if (auto *DR = dyn_cast<DefinedRegular<ELFT>>(this))
+    return DR->ThunkData != nullptr;
+  if (auto *S = dyn_cast<SharedSymbol<ELFT>>(this))
+    return S->ThunkData != nullptr;
+  return false;
+}
+
 template <class ELFT> InputFile *SymbolBody::getSourceFile() {
   if (auto *S = dyn_cast<DefinedRegular<ELFT>>(this))
     return S->Section ? S->Section->getFile() : nullptr;
   if (auto *S = dyn_cast<SharedSymbol<ELFT>>(this))
     return S->File;
   if (auto *S = dyn_cast<DefinedBitcode>(this))
     return S->File;
   if (auto *S = dyn_cast<Undefined>(this))

 }
 
 template <class ELFT> typename ELFT::uint SymbolBody::getPltVA() const {
   return Out<ELFT>::Plt->getVA() + Target->PltHeaderSize +
          PltIndex * Target->PltEntrySize;
 }
 
 template <class ELFT> typename ELFT::uint SymbolBody::getThunkVA() const {
-  auto *D = cast<DefinedRegular<ELFT>>(this);
-  auto *S = cast<InputSection<ELFT>>(D->Section);
-  return S->OutSec->getVA() + S->OutSecOff + S->getThunkOff() +
-         ThunkIndex * Target->ThunkSize;
+  if (const auto *DR = dyn_cast<DefinedRegular<ELFT>>(this))
+    return DR->ThunkData->getVA();
+  if (const auto *S = dyn_cast<SharedSymbol<ELFT>>(this))
+    return S->ThunkData->getVA();
+  fatal("getThunkVA() not supported for Symbol class\n");
 }
 
 template <class ELFT> typename ELFT::uint SymbolBody::getSize() const {
   if (const auto *C = dyn_cast<DefinedCommon>(this))
     return C->Size;
   if (const auto *DR = dyn_cast<DefinedRegular<ELFT>>(this))
     return DR->Size;
   if (const auto *S = dyn_cast<SharedSymbol<ELFT>>(this))

 }
 
 bool Symbol::includeInDynsym() const {
   if (Visibility != STV_DEFAULT && Visibility != STV_PROTECTED)
     return false;
   return (ExportDynamic && VersionId != VER_NDX_LOCAL) || body()->isShared() ||
          (body()->isUndefined() && Config->Shared);
 }
+template bool SymbolBody::hasThunk<ELF32LE>() const;
+template bool SymbolBody::hasThunk<ELF32BE>() const;
+template bool SymbolBody::hasThunk<ELF64LE>() const;
+template bool SymbolBody::hasThunk<ELF64BE>() const;
 
 template InputFile *SymbolBody::template getSourceFile<ELF32LE>();
 template InputFile *SymbolBody::template getSourceFile<ELF32BE>();
 template InputFile *SymbolBody::template getSourceFile<ELF64LE>();
 template InputFile *SymbolBody::template getSourceFile<ELF64BE>();
 
 template uint32_t SymbolBody::template getVA<ELF32LE>(uint32_t) const;
 template uint32_t SymbolBody::template getVA<ELF32BE>(uint32_t) const;

 template uint64_t SymbolBody::template getGotOffset<ELF64LE>() const;
 template uint64_t SymbolBody::template getGotOffset<ELF64BE>() const;
 
 template uint32_t SymbolBody::template getGotPltVA<ELF32LE>() const;
 template uint32_t SymbolBody::template getGotPltVA<ELF32BE>() const;
 template uint64_t SymbolBody::template getGotPltVA<ELF64LE>() const;
 template uint64_t SymbolBody::template getGotPltVA<ELF64BE>() const;
 
+template uint32_t SymbolBody::template getThunkVA<ELF32LE>() const;
+template uint32_t SymbolBody::template getThunkVA<ELF32BE>() const;
+template uint64_t SymbolBody::template getThunkVA<ELF64LE>() const;
+template uint64_t SymbolBody::template getThunkVA<ELF64BE>() const;
+
 template uint32_t SymbolBody::template getGotPltOffset<ELF32LE>() const;
 template uint32_t SymbolBody::template getGotPltOffset<ELF32BE>() const;
 template uint64_t SymbolBody::template getGotPltOffset<ELF64LE>() const;
 template uint64_t SymbolBody::template getGotPltOffset<ELF64BE>() const;
 
 template uint32_t SymbolBody::template getPltVA<ELF32LE>() const;
 template uint32_t SymbolBody::template getPltVA<ELF32BE>() const;
 template uint64_t SymbolBody::template getPltVA<ELF64LE>() const;
 template uint64_t SymbolBody::template getPltVA<ELF64BE>() const;
 
 template uint32_t SymbolBody::template getSize<ELF32LE>() const;
 template uint32_t SymbolBody::template getSize<ELF32BE>() const;
 template uint64_t SymbolBody::template getSize<ELF64LE>() const;
 template uint64_t SymbolBody::template getSize<ELF64BE>() const;
 
-template uint32_t SymbolBody::template getThunkVA<ELF32LE>() const;
-template uint32_t SymbolBody::template getThunkVA<ELF32BE>() const;
-template uint64_t SymbolBody::template getThunkVA<ELF64LE>() const;
-template uint64_t SymbolBody::template getThunkVA<ELF64BE>() const;
-
 template class elf::DefinedSynthetic<ELF32LE>;
 template class elf::DefinedSynthetic<ELF32BE>;
 template class elf::DefinedSynthetic<ELF64LE>;
 template class elf::DefinedSynthetic<ELF64BE>;

ELF/Target.h

public:
 
   // Returns true if a relocation only uses the low bits of a value such that
   // all those bits are in in the same page. For example, if the relocation
   // only uses the low 12 bits in a system with 4k pages. If this is true, the
   // bits will always have the same value at runtime and we don't have to emit
   // a dynamic relocation.
   virtual bool usesOnlyLowPageBits(uint32_t Type) const;
 
-  virtual bool needsThunk(uint32_t Type, const InputFile &File,
+  // Decide whether a Thunk is needed for the relocation from File
+  // targeting S. Returns one of:
+  // Expr if there is no Thunk required
+  // R_THUNK_ABS if thunk is required and expression is absolute
+  // R_THUNK_PC if thunk is required and expression is pc rel
+  // R_THUNK_PLT_PC if thunk is required to PLT entry and expression is pc rel
+  virtual RelExpr getThunkExpr(RelExpr Expr, uint32_t RelocType,
+                               const InputFile &File,
                                const SymbolBody &S) const;
-
   virtual void writeThunk(uint8_t *Buf, uint64_t S) const {}
-
   virtual RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const = 0;
   virtual void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const = 0;
   virtual ~TargetInfo();
 
   unsigned TlsGdRelaxSkip = 1;
   unsigned PageSize = 4096;
 
   // On freebsd x86_64 the first page cannot be mmaped.
   // On linux that is controled by vm.mmap_min_addr. At least on some x86_64
public:
 
   // At least on x86_64 positions 1 and 2 are used by the first plt entry
   // to support lazy loading.
   unsigned GotPltHeaderEntriesNum = 3;
 
   // Set to 0 for variant 2
   unsigned TcbSize = 0;
 
-  uint32_t ThunkSize = 0;
-
   virtual RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
                                   RelExpr Expr) const;
   virtual void relaxGot(uint8_t *Loc, uint64_t Val) const;
   virtual void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const;
   virtual void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const;
   virtual void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const;
   virtual void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const;
 };

ELF/Target.cpp

 //
 //===----------------------------------------------------------------------===//
 
 #include "Target.h"
 #include "Error.h"
 #include "InputFiles.h"
 #include "OutputSections.h"
 #include "Symbols.h"
+#include "Thunks.h"
 
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/Object/ELF.h"
 #include "llvm/Support/Endian.h"
 #include "llvm/Support/ELF.h"
 
 using namespace llvm;
 using namespace llvm::object;
public:
   ARMTargetInfo();
   RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
   uint32_t getDynRel(uint32_t Type) const override;
   uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
   void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
   void writePltHeader(uint8_t *Buf) const override;
   void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
+  RelExpr getThunkExpr(RelExpr Expr, uint32_t RelocType,
+                       const InputFile &File,
+                       const SymbolBody &S) const override;
   void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
 };
 
 template <class ELFT> class MipsTargetInfo final : public TargetInfo {
 public:
   MipsTargetInfo();
   RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
   uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
   uint32_t getDynRel(uint32_t Type) const override;
   bool isTlsLocalDynamicRel(uint32_t Type) const override;
   bool isTlsGlobalDynamicRel(uint32_t Type) const override;
   void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
   void writePltHeader(uint8_t *Buf) const override;
   void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
   void writeThunk(uint8_t *Buf, uint64_t S) const override;
-  bool needsThunk(uint32_t Type, const InputFile &File,
+  RelExpr getThunkExpr(RelExpr Expr, uint32_t RelocType,
+                       const InputFile &File,
                        const SymbolBody &S) const override;
   void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
   bool usesOnlyLowPageBits(uint32_t Type) const override;
 };
 } // anonymous namespace
 
 TargetInfo *createTarget() {
   switch (Config->EMachine) {
   case EM_386:
uint64_t TargetInfo::getImplicitAddend(const uint8_t *Buf,
                                        uint32_t Type) const {
   return 0;
 }
 
 uint64_t TargetInfo::getVAStart() const { return Config->Pic ? 0 : VAStart; }
 
 bool TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { return false; }
 
-bool TargetInfo::needsThunk(uint32_t Type, const InputFile &File,
+RelExpr TargetInfo::getThunkExpr(RelExpr Expr, uint32_t RelocType,
+                                 const InputFile &File,
                                  const SymbolBody &S) const {
-  return false;
+  return Expr;
 }
 
 bool TargetInfo::isTlsInitialExecRel(uint32_t Type) const { return false; }
 
 bool TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { return false; }
 
 bool TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const {
   return false;
RelExpr ARMTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
   case R_ARM_GOT_PREL:
     // GOT(S) + - GOT_ORG
     return R_GOT_PC;
   case R_ARM_BASE_PREL:
     // B(S) + A - P
     // FIXME: currently B(S) assumed to be .got, this may not hold for all
     // platforms.
     return R_GOTONLY_PC;
+  case R_ARM_MOVW_PREL_NC:
+  case R_ARM_MOVT_PREL:
   case R_ARM_PREL31:
   case R_ARM_REL32:
+  case R_ARM_THM_MOVW_PREL_NC:
+  case R_ARM_THM_MOVT_PREL:
     return R_PC;
   }
 }
 
 uint32_t ARMTargetInfo::getDynRel(uint32_t Type) const {
   if (Type == R_ARM_ABS32)
     return Type;
   // Keep it going with a dummy value so that we can find more reloc errors.
const uint8_t PltData[] = {
       0x00, 0xf0, 0x9c, 0xe5, //     ldr pc, [ip]
       0x00, 0x00, 0x00, 0x00, // L2: .word   Offset(&(.plt.got) - L1 - 8
   };
   memcpy(Buf, PltData, sizeof(PltData));
   uint64_t L1 = PltEntryAddr + 4;
   write32le(Buf + 12, GotEntryAddr - L1 - 8);
 }
 
+RelExpr ARMTargetInfo::getThunkExpr(RelExpr Expr, uint32_t RelocType,
+                                    const InputFile &File,
+                                    const SymbolBody &S) const {
+  // A state change from ARM to Thumb and vice versa must go through an
+  // interworking thunk if the relocation type is not R_ARM_CALL or
+  // R_ARM_THM_CALL.
+  switch (RelocType) {
+  case R_ARM_PC24:
+  case R_ARM_PLT32:
+  case R_ARM_JUMP24:
+    // Source is ARM, all PLT entries are ARM so no interworking required.
+    // Otherwise we need to interwork if Symbol has bit 0 set (Thumb).
+    if (Expr == R_PC && ((S.getVA<ELF32LE>() & 1) == 1))
+      return R_THUNK_PC;
+    break;
+  case R_ARM_THM_JUMP19:
+  case R_ARM_THM_JUMP24:
+    // Source is Thumb, all PLT entries are ARM so interworking is required.
+    // Otherwise we need to interwork if Symbol has bit 0 clear (ARM).
+    if (Expr == R_PLT_PC)
+      return R_THUNK_PLT_PC;
+    if ((S.getVA<ELF32LE>() & 1) == 0)
+      return R_THUNK_PC;
+    break;
+  }
+  return Expr;
+}
+
 void ARMTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
                                 uint64_t Val) const {
   switch (Type) {
   case R_ARM_NONE:
     break;
   case R_ARM_ABS32:
   case R_ARM_BASE_PREL:
   case R_ARM_GOTOFF32:
write16le(Loc,
                   ((Val >> 12) & 0x03ff)); // imm10
     write16le(Loc + 2,
               (read16le(Loc + 2) & 0xd000) |                  // opcode
                   (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1
                   (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2
                   ((Val >> 1) & 0x07ff));                     // imm11
     break;
   case R_ARM_MOVW_ABS_NC:
+  case R_ARM_MOVW_PREL_NC:
     write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) |
                        (Val & 0x0fff));
     break;
   case R_ARM_MOVT_ABS:
-    checkUInt<32>(Val, Type);
+  case R_ARM_MOVT_PREL:
+    checkInt<32>(Val, Type);
     write32le(Loc, (read32le(Loc) & ~0x000f0fff) |
                        (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff));
     break;
   case R_ARM_THM_MOVT_ABS:
+  case R_ARM_THM_MOVT_PREL:
     // Encoding T1: A = imm4:i:imm3:imm8
-    checkUInt<32>(Val, Type);
+    checkInt<32>(Val, Type);
     write16le(Loc,
               0xf2c0 |                     // opcode
                   ((Val >> 17) & 0x0400) | // i
                   ((Val >> 28) & 0x000f)); // imm4
     write16le(Loc + 2,
               (read16le(Loc + 2) & 0x8f00) | // opcode
                   ((Val >> 12) & 0x7000) |   // imm3
                   ((Val >> 16) & 0x00ff));   // imm8
     break;
   case R_ARM_THM_MOVW_ABS_NC:
+  case R_ARM_THM_MOVW_PREL_NC:
     // Encoding T3: A = imm4:i:imm3:imm8
     write16le(Loc,
               0xf240 |                     // opcode
                   ((Val >> 1) & 0x0400) |  // i
                   ((Val >> 12) & 0x000f)); // imm4
     write16le(Loc + 2,
               (read16le(Loc + 2) & 0x8f00) | // opcode
                   ((Val << 4) & 0x7000) |    // imm3
case R_ARM_THM_JUMP19: {
     uint16_t Hi = read16le(Buf);
     uint16_t Lo = read16le(Buf + 2);
     return SignExtend64<20>(((Hi & 0x0400) << 10) | // S
                             ((Lo & 0x0800) << 8) |  // J2
                             ((Lo & 0x2000) << 5) |  // J1
                             ((Hi & 0x003f) << 12) | // imm6
                             ((Lo & 0x07ff) << 1));  // imm11:0
   }
-  case R_ARM_THM_JUMP24:
-  case R_ARM_THM_CALL: {
+  case R_ARM_THM_CALL:
+  case R_ARM_THM_JUMP24: {
     // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0
     // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S)
     // FIXME: I1 and I2 require v6T2ops
     uint16_t Hi = read16le(Buf);
     uint16_t Lo = read16le(Buf + 2);
     return SignExtend64<24>(((Hi & 0x0400) << 14) |                    // S
                             (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1
                             (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2
                             ((Hi & 0x003ff) << 12) |                   // imm0
                             ((Lo & 0x007ff) << 1)); // imm11:0
   }
   // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and
   // MOVT is in the range -32768 <= A < 32768
   case R_ARM_MOVW_ABS_NC:
-  case R_ARM_MOVT_ABS: {
+  case R_ARM_MOVT_ABS:
+  case R_ARM_MOVW_PREL_NC:
+  case R_ARM_MOVT_PREL: {
     uint64_t Val = read32le(Buf) & 0x000f0fff;
     return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff));
   }
   case R_ARM_THM_MOVW_ABS_NC:
-  case R_ARM_THM_MOVT_ABS: {
+  case R_ARM_THM_MOVT_ABS:
+  case R_ARM_THM_MOVW_PREL_NC:
+  case R_ARM_THM_MOVT_PREL: {
     // Encoding T3: A = imm4:i:imm3:imm8
     uint16_t Hi = read16le(Buf);
     uint16_t Lo = read16le(Buf + 2);
     return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4
                             ((Hi & 0x0400) << 1) |  // i
                             ((Lo & 0x7000) >> 4) |  // imm3
                             (Lo & 0x00ff));         // imm8
   }
   }
 }
 
 template <class ELFT> MipsTargetInfo<ELFT>::MipsTargetInfo() {
   GotPltHeaderEntriesNum = 2;
   PageSize = 65536;
   PltEntrySize = 16;
   PltHeaderSize = 32;
-  ThunkSize = 16;
   CopyRel = R_MIPS_COPY;
   PltRel = R_MIPS_JUMP_SLOT;
   if (ELFT::Is64Bits) {
     RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
     TlsGotRel = R_MIPS_TLS_TPREL64;
     TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
     TlsOffsetRel = R_MIPS_TLS_DTPREL64;
   } else {
void MipsTargetInfo<ELFT>::writeThunk(uint8_t *Buf, uint64_t S) const {
   write32<E>(Buf + 4, 0x08000000 | (S >> 2)); // j     func
   write32<E>(Buf + 8, 0x27390000);            // addiu $25, $25, %lo(func)
   write32<E>(Buf + 12, 0x00000000);           // nop
   writeMipsHi16<E>(Buf, S);
   writeMipsLo16<E>(Buf + 8, S);
 }
 
 template <class ELFT>
-bool MipsTargetInfo<ELFT>::needsThunk(uint32_t Type, const InputFile &File,
+RelExpr MipsTargetInfo<ELFT>::getThunkExpr(RelExpr Expr, uint32_t Type,
+                                           const InputFile &File,
                                            const SymbolBody &S) const {
   // Any MIPS PIC code function is invoked with its address in register $t9.
   // So if we have a branch instruction from non-PIC code to the PIC one
   // we cannot make the jump directly and need to create a small stubs
   // to save the target function address.
   // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
   if (Type != R_MIPS_26)
-    return false;
+    return Expr;
   auto *F = dyn_cast<ELFFileBase<ELFT>>(&File);
   if (!F)
-    return false;
+    return Expr;
   // If current file has PIC code, LA25 stub is not required.
   if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
-    return false;
+    return Expr;
   auto *D = dyn_cast<DefinedRegular<ELFT>>(&S);
   if (!D || !D->Section)
-    return false;
+    return Expr;
   // LA25 is required if target file has PIC code
   // or target symbol is a PIC symbol.
-  return (D->Section->getFile()->getObj().getHeader()->e_flags & EF_MIPS_PIC) ||
-         (D->StOther & STO_MIPS_MIPS16) == STO_MIPS_PIC;
+  const ELFFile<ELFT> &DefFile = D->Section->getFile()->getObj();
+  bool PicFile = DefFile.getHeader()->e_flags & EF_MIPS_PIC;
+  bool PicSym = (D->StOther & STO_MIPS_MIPS16) == STO_MIPS_PIC;
+  return (PicFile || PicSym) ? R_THUNK_ABS : Expr;
 }
 
 template <class ELFT>
 uint64_t MipsTargetInfo<ELFT>::getImplicitAddend(const uint8_t *Buf,
                                                  uint32_t Type) const {
   const endianness E = ELFT::TargetEndianness;
   switch (Type) {
   default:
     return 0;

ELF/Thunks.h

+//===- Thunks.h --------------------------------------------------------===//
+//
+//                             The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLD_ELF_THUNKS_H
+#define LLD_ELF_THUNKS_H
+
+#include "Relocations.h"
+
+namespace lld {
+namespace elf {
+class SymbolBody;
+class InputFile;
+template <class ELFT> class InputSection;
+template <class ELFT> class InputSectionBase;
+
+// Class to describe an instance of a Thunk.
+// A Thunk is a code-sequence inserted by the linker in between a caller and
+// the callee. The relocation to the callee is redirected to the Thunk, which
+// after executing transfers control to the callee. Typical uses of Thunks
+// include transferring control from non-pi to pi and changing state on
+// targets like ARM.
+//
+// Thunks can be created for DefinedRegular and Shared Symbols. The Thunk
+// is stored in a field of the Symbol Destination.
+// Thunks to be written to an InputSection are recorded by the InputSection.
+template <class ELFT> class Thunk {
+public:
+  virtual uint32_t size() const = 0;
+  typename ELFT::uint getVA() const;
+  virtual void writeTo(uint8_t *Buf) const = 0;
+  Thunk(const SymbolBody &Destination, const InputSection<ELFT> &Owner);
+  virtual ~Thunk();
+
+protected:
+  const SymbolBody &Destination;
+  const InputSection<ELFT> &Owner;
+  uint64_t Offset;
+};
+
+// For a Relocation to symbol S from InputSection Src, create a Thunk and
+// update the fields of S and the InputSection that the Thunk body will be
+// written to. At present there are implementations for ARM and Mips Thunks.
+template <class ELFT>
+void addThunk(uint32_t RelocType, SymbolBody &S, InputSection<ELFT> &Src);
+
+} // namespace elf
+} // namespace lld
+
+#endif

ELF/Thunks.cpp

+//===- Thunks.cpp --------------------------------------------------------===//
+//
+//                             The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===---------------------------------------------------------------------===//
+//
+// This file contains both the Target independent and Target specific Thunk
+// classes
+//
+// A Thunk Object represents a single Thunk that will be written to an
+// InputSection when the InputSection contents are written. The InputSection
+// maintains a list of Thunks that it owns.
+//===---------------------------------------------------------------------===//
+
+#include "Thunks.h"
+#include "Error.h"
+#include "InputFiles.h"
+#include "InputSection.h"
+#include "OutputSections.h"
+#include "Symbols.h"
+#include "Target.h"
+
+#include "llvm/Object/ELF.h"
+#include "llvm/Support/ELF.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+using namespace llvm::object;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+
+namespace lld {
+namespace elf {
+
+template <class ELFT> Thunk<ELFT>::~Thunk() {}
+
+template <class ELFT>
+Thunk<ELFT>::Thunk(const SymbolBody &D, const InputSection<ELFT> &O)
+    : Destination(D), Owner(O), Offset(O.getThunkOff() + O.getThunksSize()) {}
+
+template <class ELFT> typename ELFT::uint Thunk<ELFT>::getVA() const {
+  return Owner.OutSec->getVA() + Owner.OutSecOff + Offset;
+}
+
+// ARM Target Thunks
+template <class ELFT> static uint64_t getARMThunkDestVA(const SymbolBody &S) {
+  return S.isInPlt() ? S.getPltVA<ELFT>() : S.getVA<ELFT>();
+}
+
+// Specific ARM Thunk implementations. The naming convention is:
+// Source State, TargetState, Target Requirement, ABS or PI, Range
+namespace {
+template <class ELFT>
+class ARMToThumbV7ABSLongThunk final : public Thunk<ELFT> {
+public:
+  uint32_t size() const override { return 12; }
+
+  void writeTo(uint8_t *Buf) const override {
+    const uint8_t ATData[] = {
+        0x00, 0xc0, 0x00, 0xe3, // movw         ip,:lower16:S
+        0x00, 0xc0, 0x40, 0xe3, // movt         ip,:upper16:S
+        0x1c, 0xff, 0x2f, 0xe1, // bx   ip
+    };
+    uint64_t S = getARMThunkDestVA<ELFT>(this->Destination);
+    memcpy(Buf, ATData, sizeof(ATData));
+    Target->relocateOne(Buf, R_ARM_MOVW_ABS_NC, S);
+    Target->relocateOne(Buf + 4, R_ARM_MOVT_ABS, S);
+  }
+
+  ARMToThumbV7ABSLongThunk(const SymbolBody &Destination,
+                           const InputSection<ELFT> &Owner)
+      : Thunk<ELFT>(Destination, Owner) {}
+};
+
+template <class ELFT> class ARMToThumbV7PILongThunk final : public Thunk<ELFT> {
+public:
+  uint32_t size() const override { return 16; }
+
+  void writeTo(uint8_t *Buf) const override {
+    const uint8_t ATData[] = {
+        0xf0, 0xcf, 0x0f, 0xe3, // P:  movw ip,:lower16:S - (P + (L1-P) +8)
+        0x00, 0xc0, 0x40, 0xe3, //     movt ip,:upper16:S - (P + (L1-P+4) +8)
+        0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc
+        0x1c, 0xff, 0x2f, 0xe1, //     bx r12
+    };
+    uint64_t S = getARMThunkDestVA<ELFT>(this->Destination);
+    uint64_t P = this->getVA();
+    memcpy(Buf, ATData, sizeof(ATData));
+    Target->relocateOne(Buf, R_ARM_MOVW_PREL_NC, S - P - 16);
+    Target->relocateOne(Buf + 4, R_ARM_MOVT_PREL, S - P - 12);
+  }
+
+  ARMToThumbV7PILongThunk(const SymbolBody &Destination,
+                          const InputSection<ELFT> &Owner)
+      : Thunk<ELFT>(Destination, Owner) {}
+};
+
+template <class ELFT>
+class ThumbToARMV7ABSLongThunk final : public Thunk<ELFT> {
+public:
+  uint32_t size() const override { return 10; }
+
+  void writeTo(uint8_t *Buf) const override {
+    const uint8_t TAData[] = {
+        0x40, 0xf2, 0x00, 0x0c, // movw         ip, :lower16:S
+        0xc0, 0xf2, 0x00, 0x0c, // movt         ip, :upper16:S
+        0x60, 0x47,             // bx   ip
+    };
+    uint64_t S = getARMThunkDestVA<ELFT>(this->Destination);
+    memcpy(Buf, TAData, sizeof(TAData));
+    Target->relocateOne(Buf, R_ARM_THM_MOVW_ABS_NC, S);
+    Target->relocateOne(Buf + 4, R_ARM_THM_MOVT_ABS, S);
+  }
+
+  ThumbToARMV7ABSLongThunk(const SymbolBody &Destination,
+                           const InputSection<ELFT> &Owner)
+      : Thunk<ELFT>(Destination, Owner) {}
+};
+
+template <class ELFT> class ThumbToARMV7PILongThunk final : public Thunk<ELFT> {
+public:
+  uint32_t size() const override { return 12; }
+
+  void writeTo(uint8_t *Buf) const override {
+    const uint8_t TAData[] = {
+        0x4f, 0xf6, 0xf4, 0x7c, // P:  movw ip,:lower16:S - (P + (L1-P) + 4)
+        0xc0, 0xf2, 0x00, 0x0c, //     movt ip,:upper16:S - (P + (L1-P+4) + 4)
+        0xfc, 0x44,             // L1: add  r12, pc
+        0x60, 0x47,             //     bx   r12
+    };
+    uint64_t S = getARMThunkDestVA<ELFT>(this->Destination);
+    uint64_t P = this->getVA();
+    memcpy(Buf, TAData, sizeof(TAData));
+    Target->relocateOne(Buf, R_ARM_THM_MOVW_PREL_NC, S - P - 12);
+    Target->relocateOne(Buf + 4, R_ARM_THM_MOVT_PREL, S - P - 8);
+  }
+
+  ThumbToARMV7PILongThunk(const SymbolBody &Destination,
+                          const InputSection<ELFT> &Owner)
+      : Thunk<ELFT>(Destination, Owner) {}
+};
+
+// Mips Thunks
+// Only the MIPS LA25 Thunk is supported, the implementation is delegated
+// to the MipsTargetInfo class in Target.cpp
+template <class ELFT> class MipsThunk : public Thunk<ELFT> {
+public:
+  MipsThunk(const SymbolBody &Destination, const InputSection<ELFT> &Owner);
+  uint32_t size() const override;
+  void writeTo(uint8_t *Buf) const override;
+};
+
+template <class ELFT>
+MipsThunk<ELFT>::MipsThunk(const SymbolBody &Destination,
+                           const InputSection<ELFT> &Owner)
+    : Thunk<ELFT>(Destination, Owner) {}
+
+template <class ELFT> uint32_t MipsThunk<ELFT>::size() const { return 16; }
+
+template <class ELFT> void MipsThunk<ELFT>::writeTo(uint8_t *Buf) const {
+  const SymbolBody &D = this->Destination;
+  uint64_t S = D.getVA<ELFT>();
+  Target->writeThunk(Buf, S);
+}
+}
+
+template <class ELFT>
+static void addThunkARM(uint32_t RelocType, SymbolBody &S,
+                        InputSection<ELFT> &IS) {
+  if (S.hasThunk<ELFT>())
+    // only one Thunk supported per symbol
+    return;
+
+  bool NeedsPI = Config->Pic || Config->Pie || Config->Shared;
+  Thunk<ELFT> *thunk;
+  // ARM relocations need ARM to Thumb interworking Thunks, Thumb relocations
+  // need Thumb to ARM relocations. Use position independent Thunks if we
+  // require position independent code.
+  switch (RelocType) {
+  case R_ARM_PC24:
+  case R_ARM_PLT32:
+  case R_ARM_JUMP24:
+    if (NeedsPI)
+      thunk = new ARMToThumbV7PILongThunk<ELFT>(S, IS);
+    else
+      thunk = new ARMToThumbV7ABSLongThunk<ELFT>(S, IS);
+    break;
+  case R_ARM_THM_JUMP19:
+  case R_ARM_THM_JUMP24:
+    if (NeedsPI)
+      thunk = new ThumbToARMV7PILongThunk<ELFT>(S, IS);
+    else
+      thunk = new ThumbToARMV7ABSLongThunk<ELFT>(S, IS);
+    break;
+  default:
+    fatal("Unrecognised Relocation type\n");
+  }
+  // ARM Thunks are added to the same InputSection as the relocation. This
+  // isn't strictly necessary but it makes it more likely that a limited range
+  // branch can reach the Thunk, and it makes Thunks to the PLT section easier
+  IS.addThunk(thunk);
+  if (DefinedRegular<ELFT> *DR = dyn_cast<DefinedRegular<ELFT>>(&S))
+    DR->ThunkData.reset(thunk);
+  else if (SharedSymbol<ELFT> *SH = dyn_cast<SharedSymbol<ELFT>>(&S))
+    SH->ThunkData.reset(thunk);
+  else
+    fatal("symbol not DefinedRegular or Shared\n");
+}
+
+template <class ELFT>
+static void addThunkMips(uint32_t RelocType, SymbolBody &S) {
+  if (S.hasThunk<ELFT>())
+    // only one Thunk supported per symbol
+    return;
+  // Mips Thunks are added to the InputSection defining S
+  auto *R = cast<DefinedRegular<ELFT>>(&S);
+  auto *Sec = cast<InputSection<ELFT>>(R->Section);
+  auto *T = new MipsThunk<ELFT>(S, *Sec);
+  Sec->addThunk(T);
+  R->ThunkData.reset(T);
+}
+
+template <class ELFT>
+void addThunk(uint32_t RelocType, SymbolBody &S, InputSection<ELFT> &IS) {
+  if (Config->EMachine == EM_ARM)
+    addThunkARM<ELFT>(RelocType, S, IS);
+  else if (Config->EMachine == EM_MIPS)
+    addThunkMips<ELFT>(RelocType, S);
+  else
+    llvm_unreachable("add Thunk only supported for ARM and Mips");
+}
+
+template void addThunk<ELF32LE>(uint32_t, SymbolBody &,
+                                InputSection<ELF32LE> &);
+template void addThunk<ELF32BE>(uint32_t, SymbolBody &,
+                                InputSection<ELF32BE> &);
+template void addThunk<ELF64LE>(uint32_t, SymbolBody &,
+                                InputSection<ELF64LE> &);
+template void addThunk<ELF64BE>(uint32_t, SymbolBody &,
+                                InputSection<ELF64BE> &);
+
+} // namespace elf
+} // namespace lld

test/ELF/arm-mov-relocs.s

  movt r4, :upper16:label3 + (4 * 65536)
 // CHECK: Disassembly of section .R_ARM_MOVT_ABS
 // CHECK: movt  r0, #2
 // CHECK: movt  r1, #2
 // CHECK: movt  r2, #2
 // CHECK: movt  r3, #2
 // CHECK: movt  r4, #3
 
+.section .R_ARM_MOVW_PREL_NC, "ax",%progbits
+ movw r0, :lower16:label - .
+ movw r1, :lower16:label1 - .
+ movw r2, :lower16:label2 + 4 - .
+ movw r3, :lower16:label3 - .
+ movw r4, :lower16:label3 + 0x103c - .
+// 0x20000 - 0x11028 = :lower16:0xefd8 (61400)
+// CHECK: 11028:  {{.*}}     movw    r0, #61400
+// 0x20004 = 0x1102c = :lower16:0xefd8 (61400)
+// CHECK: 1102c:  {{.*}}     movw    r1, #61400
+// 0x20008 - 0x11030 + 4 = :lower16:0xefdc (61404)
+// CHECK: 11030:  {{.*}}     movw    r2, #61404
+// 0x2fffc - 0x11034 = :lower16:0x1efc8 (61384)
+// CHECK: 11034:  {{.*}}     movw    r3, #61384
+// 0x2fffc - 0x11038 +0x103c :lower16:0x20000 (0)
+// CHECK: 11038:  {{.*}}     movw    r4, #0
+
+.section .R_ARM_MOVT_PREL, "ax",%progbits
+ movt r0, :upper16:label - .
+ movt r1, :upper16:label1 - .
+ movt r2, :upper16:label2 + 0x4 - .
+ movt r3, :upper16:label3 - .
+ movt r4, :upper16:label3 + 0x1050 - .
+// 0x20000 - 0x1103c = :upper16:0xefc4  = 0
+// CHECK: 1103c:  {{.*}}     movt    r0, #0
+// 0x20004 - 0x11040 = :upper16:0xefc0 = 0
+// CHECK: 11040:  {{.*}}     movt    r1, #0
+// 0x20008 - 0x11044 + 4 = :upper16:0xefc8 = 0
+// CHECK: 11044:  {{.*}}     movt    r2, #0
+// 0x2fffc - 0x11048 = :upper16:0x1efb4 = 1
+// CHECK: 11048:  {{.*}}     movt    r3, #1
+// 0x2fffc - 0x1104c + 0x1050 = :upper16:0x20000 = 2
+// CHECK: 1104c:  {{.*}}     movt    r4, #2
  .section .destination, "aw",%progbits
  .balign 65536
+// 0x20000
 label:
  .word 0
+// 0x20004
 label1:
  .word 1
+// 0x20008
 label2:
  .word 2
 // Test label3 is immediately below 2^16 alignment boundary
  .space 65536 - 16
+// 0x2fffc
 label3:
  .word 3
 // label3 + 4 is on a 2^16 alignment boundary
  .word 4

test/ELF/arm-thumb-interwork-thunk.s

+// RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
+// RUN: echo "SECTIONS { \
+// RUN:       .R_ARM_JUMP24_callee_1 : { *(.R_ARM_JUMP24_callee_low) } \
+// RUN:       .R_ARM_THM_JUMP_callee_1 : { *(.R_ARM_THM_JUMP_callee_low)} \
+// RUN:       .text : { *(.text) } \
+// RUN:       .arm_caller : { *(.arm_caller) } \
+// RUN:       .thumb_caller : { *(.thumb_caller) } \
+// RUN:       .R_ARM_JUMP24_callee_2 : { *(.R_ARM_JUMP24_callee_high) } \
+// RUN:       .R_ARM_THM_JUMP_callee_2 : { *(.R_ARM_THM_JUMP_callee_high) } } " > %t.script
+// RUN: ld.lld --script %t.script %t -o %t2 2>&1
+// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi %t2 | FileCheck -check-prefix=CHECK-THUMB -check-prefix=CHECK-ABS-THUMB %s
+// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi %t2 | FileCheck -check-prefix=CHECK-ARM -check-prefix=CHECK-ABS-ARM %s
+// RUN: ld.lld --script %t.script %t -pie -o %t3 2>&1
+// RUN: ld.lld --script %t.script %t --shared -o %t4 2>&1
+// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi %t3 | FileCheck -check-prefix=CHECK-THUMB -check-prefix=CHECK-PI-THUMB %s
+// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi %t3 | FileCheck -check-prefix=CHECK-ARM -check-prefix=CHECK-PI-ARM %s
+// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi %t4 | FileCheck -check-prefix=CHECK-THUMB -check-prefix=CHECK-PI-PLT-THUMB %s
+// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi %t4 | FileCheck -check-prefix=CHECK-ARM -check-prefix=CHECK-PI-PLT-ARM %s
+// RUN: llvm-readobj -s -r %t4 | FileCheck -check-prefix=CHECK-DSO-REL %s
+// REQUIRES: arm
+
+// Test ARM Thumb Interworking
+// The file is linked and checked 3 times to check the following contexts
+// - Absolute executables, absolute Thunks are used.
+// - Position independent executables, position independent Thunks are used.
+// - Shared object, position independent Thunks to PLT entries are used.
+
+ .syntax unified
+
+// Target Sections for thunks at a lower address than the callers.
+.section .R_ARM_JUMP24_callee_low, "ax", %progbits
+ .thumb
+ .balign 0x1000
+ .globl thumb_callee1
+ .type thumb_callee1, %function
+thumb_callee1:
+ bx lr
+
+// CHECK-THUMB: Disassembly of section .R_ARM_JUMP24_callee_1:
+// CHECK-THUMB: thumb_callee1:
+// CHECK-THUMB: 1000:       70 47   bx
+ .section .R_ARM_THM_JUMP_callee_low, "ax", %progbits
+ .arm
+ .balign 0x100
+ .globl arm_callee1
+ .type arm_callee1, %function
+arm_callee1:
+ bx lr
+// Disassembly of section .R_ARM_THM_JUMP_callee_1:
+// CHECK-ARM: arm_callee1:
+// CHECK-ARM-NEXT: 1100:         1e ff 2f e1     bx      lr
+
+ // Calling sections
+ // At present ARM and Thumb interworking thunks are always added to the calling
+ // section.
+ .section .arm_caller, "ax", %progbits
+ .arm
+ .balign 0x100
+ .globl arm_caller
+ .type arm_caller, %function
+arm_caller:
+ // If target supports BLX and target is in range we don't need an
+ // interworking thunk for a BL or BLX instruction.
+ bl thumb_callee1
+ blx thumb_callee1
+ // A B instruction can't be transformed into a BLX and needs an interworking
+ // thunk
+ b thumb_callee1
+ // As long as the thunk is in range it can be reused
+ b thumb_callee1
+ // There can be more than one thunk associated with a section
+ b thumb_callee2
+ b thumb_callee3
+ // In range ARM targets do not require interworking thunks
+ b arm_callee1
+ beq arm_callee2
+ bne arm_callee3
+ bx lr
+// CHECK-ABS-ARM: Disassembly of section .arm_caller:
+// CHECK-ABS-ARM-NEXT: arm_caller:
+// CHECK-ABS-ARM-NEXT: 1300:       3e ff ff fa     blx     #-776 <thumb_callee1>
+// CHECK-ABS-ARM-NEXT: 1304:       3d ff ff fa     blx     #-780 <thumb_callee1>
+// CHECK-ABS-ARM-NEXT: 1308:       06 00 00 ea     b       #24 <arm_caller+0x28>
+// CHECK-ABS-ARM-NEXT: 130c:       05 00 00 ea     b       #20 <arm_caller+0x28>
+// CHECK-ABS-ARM-NEXT: 1310:       07 00 00 ea     b       #28 <arm_caller+0x34>
+// CHECK-ABS-ARM-NEXT: 1314:       09 00 00 ea     b       #36 <arm_caller+0x40>
+// CHECK-ABS-ARM-NEXT: 1318:       78 ff ff ea     b       #-544 <arm_callee1>
+// CHECK-ABS-ARM-NEXT: 131c:       b7 00 00 0a     beq     #732 <arm_callee2>
+// CHECK-ABS-ARM-NEXT: 1320:       b7 00 00 1a     bne     #732 <arm_callee3>
+// CHECK-ABS-ARM-NEXT: 1324:       1e ff 2f e1     bx      lr
+// 0x1001 = thumb_callee1
+// CHECK-ABS-ARM-NEXT: 1328:       01 c0 01 e3     movw    r12, #4097
+// CHECK-ABS-ARM-NEXT: 132c:       00 c0 40 e3     movt    r12, #0
+// CHECK-ABS-ARM-NEXT: 1330:       1c ff 2f e1     bx      r12
+// 0x1501 = thumb_callee2
+// CHECK-ABS-ARM-NEXT: 1334:       01 c5 01 e3     movw    r12, #5377
+// CHECK-ABS-ARM-NEXT: 1338:       00 c0 40 e3     movt    r12, #0
+// CHECK-ABS-ARM-NEXT: 133c:       1c ff 2f e1     bx      r12
+// 0x1503 = thumb_callee3
+// CHECK-ABS-ARM-NEXT: 1340:       03 c5 01 e3     movw    r12, #5379
+// CHECK-ABS-ARM-NEXT: 1344:       00 c0 40 e3     movt    r12, #0
+// CHECK-ABS-ARM-NEXT: 1348:       1c ff 2f e1     bx      r12
+
+// CHECK-PI-ARM: Disassembly of section .arm_caller:
+// CHECK-PI-ARM-NEXT: arm_caller:
+// CHECK-PI-ARM-NEXT: 1300:       3e ff ff fa     blx     #-776 <thumb_callee1>
+// CHECK-PI-ARM-NEXT: 1304:       3d ff ff fa     blx     #-780 <thumb_callee1>
+// 0x1308 + 8 + 0x18 = 0x1328
+// CHECK-PI-ARM-NEXT: 1308:       06 00 00 ea     b       #24 <arm_caller+0x28>
+// 0x130c + 8 + 0x14 = 0x1328
+// CHECK-PI-ARM-NEXT: 130c:       05 00 00 ea     b       #20 <arm_caller+0x28>
+// 0x1310 + 8 + 0x20 = 0x1338
+// CHECK-PI-ARM-NEXT: 1310:       08 00 00 ea     b       #32 <arm_caller+0x38>
+// 0x1314 + 8 + 0x2c = 0x1348
+// CHECK-PI-ARM-NEXT: 1314:       0b 00 00 ea     b       #44 <arm_caller+0x48>
+// CHECK-PI-ARM-NEXT: 1318:       78 ff ff ea     b       #-544 <arm_callee1>
+// CHECK-PI-ARM-NEXT: 131c:       b7 00 00 0a     beq     #732 <arm_callee2>
+// CHECK-PI-ARM-NEXT: 1320:       b7 00 00 1a     bne     #732 <arm_callee3>
+// CHECK-PI-ARM-NEXT: 1324:       1e ff 2f e1     bx      lr
+// 0x1330 + 8 - 0x337 = 0x1001 = thumb_callee1
+// CHECK-PI-ARM-NEXT: 1328:       c9 cc 0f e3     movw    r12, #64713
+// CHECK-PI-ARM-NEXT: 132c:       ff cf 4f e3     movt    r12, #65535
+// CHECK-PI-ARM-NEXT: 1330:       0f c0 8c e0     add     r12, r12, pc
+// CHECK-PI-ARM-NEXT: 1334:       1c ff 2f e1     bx      r12
+// 0x1340 + 8 + 0x1b9 = 0x1501
+// CHECK-PI-ARM-NEXT: 1338:       b9 c1 00 e3     movw    r12, #441
+// CHECK-PI-ARM-NEXT: 133c:       00 c0 40 e3     movt    r12, #0
+// CHECK-PI-ARM-NEXT: 1340:       0f c0 8c e0     add     r12, r12, pc
+// CHECK-PI-ARM-NEXT: 1344:       1c ff 2f e1     bx      r12
+// 1350 + 8 + 0x1ab = 0x1503
+// CHECK-PI-ARM-NEXT: 1348:       ab c1 00 e3     movw    r12, #427
+// CHECK-PI-ARM-NEXT: 134c:       00 c0 40 e3     movt    r12, #0
+// CHECK-PI-ARM-NEXT: 1350:       0f c0 8c e0     add     r12, r12, pc
+// CHECK-PI-ARM-NEXT: 1354:       1c ff 2f e1     bx      r12
+
+// All PLT entries are ARM, no need for interworking thunks
+// CHECK-PI-ARM-PLT: Disassembly of section .arm_caller:
+// CHECK-PI-ARM-PLT-NEXT: arm_caller:
+// 0x17e4 PLT(thumb_callee1)
+// CHECK-PI-ARM-PLT-NEXT:    1300:       37 01 00 eb     bl      #1244
+// 0x17e4 PLT(thumb_callee1)
+// CHECK-PI-ARM-PLT-NEXT:    1304:       36 01 00 eb     bl      #1240
+// 0x17e4 PLT(thumb_callee1)
+// CHECK-PI-ARM-PLT-NEXT:    1308:       35 01 00 ea     b       #1236
+// 0x17e4 PLT(thumb_callee1)
+// CHECK-PI-ARM-PLT-NEXT:    130c:       34 01 00 ea     b       #1232
+// 0x17f4 PLT(thumb_callee2)
+// CHECK-PI-ARM-PLT-NEXT:    1310:       37 01 00 ea     b       #1244
+// 0x1804 PLT(thumb_callee3)
+// CHECK-PI-ARM-PLT-NEXT:    1314:       3a 01 00 ea     b       #1256
+// 0x1814 PLT(arm_callee1)
+// CHECK-PI-ARM-PLT-NEXT:    1318:       3d 01 00 ea     b       #1268
+// 0x1824 PLT(arm_callee2)
+// CHECK-PI-ARM-PLT-NEXT:    131c:       40 01 00 0a     beq     #1280
+// 0x1834 PLT(arm_callee3)
+// CHECK-PI-ARM-PLT-NEXT:    1320:       43 01 00 1a     bne     #1292
+// CHECK-PI-ARM-PLT-NEXT:    1324:       1e ff 2f e1     bx      lr
+
+ .section .thumb_caller, "ax", %progbits
+ .balign 0x100
+ .thumb
+ .globl thumb_caller
+ .type thumb_caller, %function
+thumb_caller:
+ // If target supports BLX and target is in range we don't need an
+ // interworking thunk for a BL or BLX instruction.
+ bl arm_callee1
+ blx arm_callee1
+ // A B instruction can't be transformed into a BLX and needs an interworking
+ // thunk
+ b.w arm_callee1
+ // As long as the thunk is in range it can be reused
+ b.w arm_callee2
+ // There can be more than one thunk associated with a section
+ b.w arm_callee3
+ // Conditional branches also require interworking thunks, they can use the
+ // same interworking thunks.
+ beq.w arm_callee1
+ beq.w arm_callee2
+ bne.w arm_callee3
+// CHECK-ABS-THUMB: Disassembly of section .thumb_caller:
+// CHECK-ABS-THUMB-NEXT: thumb_caller:
+// 0x1400 + 4 - 0x304 = 0x1100 = arm_callee1
+// CHECK-ABS-THUMB-NEXT: 1400:       ff f7 7e ee     blx     #-772
+// 0x1404 + 4 - 0x308 = 0x1100 = arm_callee1
+// CHECK-ABS-THUMB-NEXT: 1404:       ff f7 7c ee     blx     #-776
+// 0x1408 + 4 + 0x14 = 0x520
+// CHECK-ABS-THUMB-NEXT: 1408:       00 f0 0a b8     b.w     #20
+// 0x140c + 4 + 0x1a = 0x52a
+// CHECK-ABS-THUMB-NEXT: 140c:       00 f0 0d b8     b.w     #26
+// 0x1410 + 4 + 0x20 = 0x534
+// CHECK-ABS-THUMB-NEXT: 1410:       00 f0 10 b8     b.w     #32
+// 0x1414 + 4 + 8 = 0x520
+// CHECK-ABS-THUMB-NEXT: 1414:       00 f0 04 80     beq.w   #8
+// 0x1418 + 4 + 0xe = 0x52a
+// CHECK-ABS-THUMB-NEXT: 1418:       00 f0 07 80     beq.w   #14
+// 0x141c + 4 + 0x14 = 0x534
+// CHECK-ABS-THUMB-NEXT: 141c:       40 f0 0a 80     bne.w   #20
+// 0x1100 = arm_callee1
+// CHECK-ABS-THUMB-NEXT: 1420:       41 f2 00 1c     movw    r12, #4352
+// CHECK-ABS-THUMB-NEXT: 1424:       c0 f2 00 0c     movt    r12, #0
+// CHECK-ABS-THUMB-NEXT: 1428:       60 47   bx      r12
+// 0x1600 = arm_callee2
+// CHECK-ABS-THUMB-NEXT: 142a:       41 f2 00 6c     movw    r12, #5632
+// CHECK-ABS-THUMB-NEXT: 142e:       c0 f2 00 0c     movt    r12, #0
+// CHECK-ABS-THUMB-NEXT: 1432:       60 47   bx      r12
+// 0x1604 = arm_callee3
+// CHECK-ABS-THUMB-NEXT: 1434:       41 f2 04 6c     movw    r12, #5636
+// CHECK-ABS-THUMB-NEXT: 1438:       c0 f2 00 0c     movt    r12, #0
+// CHECK-ABS-THUMB-NEXT: 143c:       60 47   bx      r12
+
+// CHECK-PI-THUMB: Disassembly of section .thumb_caller:
+// CHECK-PI-THUMB-NEXT: thumb_caller:
+// CHECK-PI-THUMB-NEXT: 1400:       ff f7 7e ee     blx     #-772
+// CHECK-PI-THUMB-NEXT: 1404:       ff f7 7c ee     blx     #-776
+// CHECK-PI-THUMB-NEXT: 1408:       00 f0 0a b8     b.w     #20
+// CHECK-PI-THUMB-NEXT: 140c:       00 f0 0e b8     b.w     #28
+// CHECK-PI-THUMB-NEXT: 1410:       00 f0 12 b8     b.w     #36
+// CHECK-PI-THUMB-NEXT: 1414:       00 f0 04 80     beq.w   #8
+// CHECK-PI-THUMB-NEXT: 1418:       00 f0 08 80     beq.w   #16
+// CHECK-PI-THUMB-NEXT: 141c:       40 f0 0c 80     bne.w   #24
+// 0x1428 + 4 - 0x32c = 0x1100 = arm_callee1
+// CHECK-PI-THUMB-NEXT: 1420:       4f f6 d4 4c     movw    r12, #64724
+// CHECK-PI-THUMB-NEXT: 1424:       cf f6 ff 7c     movt    r12, #65535
+// CHECK-PI-THUMB-NEXT: 1428:       fc 44   add     r12, pc
+// CHECK-PI-THUMB-NEXT: 142a:       60 47   bx      r12
+// 0x1434 + 4 + 0x1c8 = 0x1600 = arm_callee2
+// CHECK-PI-THUMB-NEXT: 142c:       40 f2 c8 1c     movw    r12, #456
+// CHECK-PI-THUMB-NEXT: 1430:       c0 f2 00 0c     movt    r12, #0
+// CHECK-PI-THUMB-NEXT: 1434:       fc 44   add     r12, pc
+// CHECK-PI-THUMB-NEXT: 1436:       60 47   bx      r12
+// 0x1440 + 4 + 0x1c0 = 0x1604 = arm_callee3
+// CHECK-PI-THUMB-NEXT: 1438:       40 f2 c0 1c     movw    r12, #448
+// CHECK-PI-THUMB-NEXT: 143c:       c0 f2 00 0c     movt    r12, #0
+// CHECK-PI-THUMB-NEXT: 1440:       fc 44   add     r12, pc
+// CHECK-PI-THUMB-NEXT: 1442:       60 47   bx      r12
+
+// CHECK-PI-THUMB-PLT: Disassembly of section .arm_caller:
+// CHECK-PI-THUMB-PLT-NEXT: thumb_caller:
+// 0x1400 + 4 + 0x410 = 0x1814 = PLT(arm_callee1)
+// CHECK-PI-THUMB-PLT-NEXT:    1400:    00 f0 08 ea     blx     #1040
+// 0x1404 + 4 + 0x40c = 0x1814 = PLT(arm_callee1)
+// CHECK-PI-THUMB-PLT-NEXT:    1404:    00 f0 06 ea     blx     #1036
+// 0x1408 + 4 + 0x14 = 0x1420 = IWV(PLT(arm_callee1)
+// CHECK-PI-THUMB-PLT-NEXT:    1408:    00 f0 0a b8     b.w     #20
+// 0x140c + 4 + 0x1c = 0x142c = IWV(PLT(arm_callee2)
+// CHECK-PI-THUMB-PLT-NEXT:    140c:    00 f0 0e b8     b.w     #28
+// 0x1410 + 4 + 0x24 = 0x1438 = IWV(PLT(arm_callee3)
+// CHECK-PI-THUMB-PLT-NEXT:    1410:    00 f0 12 b8     b.w     #36
+// 0x1414 + 4 + 8 = 0x1420    = IWV(PLT(arm_callee1)
+// CHECK-PI-THUMB-PLT-NEXT:    1414:    00 f0 04 80     beq.w   #8
+// 0x1418 + 4 + 0x10 = 0x142c = IWV(PLT(arm_callee2)
+// CHECK-PI-THUMB-PLT-NEXT:    1418:    00 f0 08 80     beq.w   #16
+// 0x141c + 4 + 0x18 = 0x1438 = IWV(PLT(arm_callee3)
+// CHECK-PI-THUMB-PLT-NEXT:    141c:    40 f0 0c 80     bne.w   #24
+// 0x1428 + 4 + 0x3e8 = 0x1814 = PLT(arm_callee1)
+// CHECK-PI-THUMB-PLT-NEXT:    1420:    40 f2 e8 3c     movw    r12, #1000
+// CHECK-PI-THUMB-PLT-NEXT:    1424:    c0 f2 00 0c     movt    r12, #0
+// CHECK-PI-THUMB-PLT-NEXT:    1428:    fc 44   add     r12, pc
+// CHECK-PI-THUMB-PLT-NEXT:    142a:    60 47   bx      r12
+// 0x1434 + 4 + 0x3ec = 0x1824 = PLT(arm_callee2)
+// CHECK-PI-THUMB-PLT-NEXT:    142c:    40 f2 ec 3c     movw    r12, #1004
+// CHECK-PI-THUMB-PLT-NEXT:    1430:    c0 f2 00 0c     movt    r12, #0
+// CHECK-PI-THUMB-PLT-NEXT:    1434:    fc 44   add     r12, pc
+// CHECK-PI-THUMB-PLT-NEXT:    1436:    60 47   bx      r12
+// 0x1440 + 4 + 0x3f0 = 0x1834 = PLT(arm_callee3)
+// CHECK-PI-THUMB-PLT-NEXT:    1438:    40 f2 f0 3c     movw    r12, #1008
+// CHECK-PI-THUMB-PLT-NEXT:    143c:    c0 f2 00 0c     movt    r12, #0
+// CHECK-PI-THUMB-PLT-NEXT:    1440:    fc 44   add     r12, pc
+// CHECK-PI-THUMB-PLT-NEXT:    1442:    60 47   bx      r12
+
+// Target Sections for thunks at a higher address than the callers.
+.section .R_ARM_JUMP24_callee_high, "ax", %progbits
+ .thumb
+ .balign 0x100
+ .globl thumb_callee2
+ .type thumb_callee2, %function
+thumb_callee2:
+ bx lr
+
+ .globl thumb_callee3
+ .type thumb_callee3, %function
+thumb_callee3:
+ bx lr
+// CHECK-THUMB:  Disassembly of section .R_ARM_JUMP24_callee_2:
+// CHECK-THUMB-NEXT: thumb_callee2:
+// CHECK-THUMB-NEXT: 1500:       70 47   bx      lr
+// CHECK-THUMB: thumb_callee3:
+// CHECK-THUMB-NEXT: 1502:       70 47   bx      lr
+
+ .section .R_ARM_THM_JUMP_callee_high, "ax", %progbits
+ .arm
+ .balign 0x100
+ .globl arm_callee2
+ .type arm_callee2, %function
+arm_callee2:
+ bx lr
+ .globl arm_callee3
+ .type arm_callee3, %function
+arm_callee3:
+ bx lr
+// CHECK-ARM: Disassembly of section .R_ARM_THM_JUMP_callee_2:
+// CHECK-ARM-NEXT: arm_callee2:
+// CHECK-ARM-NEXT:     1600:     1e ff 2f e1     bx      lr
+// CHECK-ARM: arm_callee3:
+// CHECK-ARM-NEXT:     1604:     1e ff 2f e1     bx      lr
+
+// _start section just calls the arm and thumb calling sections
+ .text
+ .arm
+ .globl _start
+ .balign 0x100
+ .type _start, %function
+_start:
+ bl arm_caller
+ bl thumb_caller
+ bx lr
+
+
+// CHECK-PI-ARM-PLT: Disassembly of section .plt:
+// CHECK-PI-ARM-PLT-NEXT: .plt:
+// CHECK-PI-ARM-PLT-NEXT: 17b0:         04 e0 2d e5     str     lr, [sp, #-4]!
+// CHECK-PI-ARM-PLT-NEXT: 17b4:         04 e0 9f e5     ldr     lr, [pc, #4]
+// CHECK-PI-ARM-PLT-NEXT: 17b8:         0e e0 8f e0     add     lr, pc, lr
+// CHECK-PI-ARM-PLT-NEXT: 17bc:         08 f0 be e5     ldr     pc, [lr, #8]!
+// CHECK-PI-ARM-PLT-NEXT: 17c0:         d4 00 00 00
+// 0x17c8 + 8 + 0xd0 = 0x18a0 arm_caller
+// CHECK-PI-ARM-PLT-NEXT: 17c4:         04 c0 9f e5     ldr     r12, [pc, #4]
+// CHECK-PI-ARM-PLT-NEXT: 17c8:         0f c0 8c e0     add     r12, r12, pc
+// CHECK-PI-ARM-PLT-NEXT: 17cc:         00 f0 9c e5     ldr     pc, [r12]
+// CHECK-PI-ARM-PLT-NEXT: 17d0:         d0 00 00 00
+// 0x17d8 + 8 + 0xc4 = 0x18a4 thumb_caller
+// CHECK-PI-ARM-PLT-NEXT: 17d4:         04 c0 9f e5     ldr     r12, [pc, #4]
+// CHECK-PI-ARM-PLT-NEXT: 17d8:         0f c0 8c e0     add     r12, r12, pc
+// CHECK-PI-ARM-PLT-NEXT: 17dc:         00 f0 9c e5     ldr     pc, [r12]
+// CHECK-PI-ARM-PLT-NEXT: 17e0:         c4 00 00 00
+// 0x17e8 + 8 + 0xb8 = 0x18a8 thumb_callee1
+// CHECK-PI-ARM-PLT-NEXT: 17e4:         04 c0 9f e5     ldr     r12, [pc, #4]
+// CHECK-PI-ARM-PLT-NEXT: 17e8:         0f c0 8c e0     add     r12, r12, pc
+// CHECK-PI-ARM-PLT-NEXT: 17ec:         00 f0 9c e5     ldr     pc, [r12]
+// CHECK-PI-ARM-PLT-NEXT: 17f0:         b8 00 00 00
+// 0x17f8 + 8 + 0xac = 0x18ac thumb_callee2
+// CHECK-PI-ARM-PLT-NEXT: 17f4:         04 c0 9f e5     ldr     r12, [pc, #4]
+// CHECK-PI-ARM-PLT-NEXT: 17f8:         0f c0 8c e0     add     r12, r12, pc
+// CHECK-PI-ARM-PLT-NEXT: 17fc:         00 f0 9c e5     ldr     pc, [r12]
+// CHECK-PI-ARM-PLT-NEXT: 1800:         ac 00 00 00
+// 0x1808 + 8 + 0xa0 = 0x18b0 thumb_callee3
+// CHECK-PI-ARM-PLT-NEXT: 1804:         04 c0 9f e5     ldr     r12, [pc, #4]
+// CHECK-PI-ARM-PLT-NEXT: 1808:         0f c0 8c e0     add     r12, r12, pc
+// CHECK-PI-ARM-PLT-NEXT: 180c:         00 f0 9c e5     ldr     pc, [r12]
+// CHECK-PI-ARM-PLT-NEXT: 1810:         a0 00 00 00
+// 0x1818 + 8 + 0x94 = 0x18b4 arm_callee1
+// CHECK-PI-ARM-PLT-NEXT: 1814:         04 c0 9f e5     ldr     r12, [pc, #4]
+// CHECK-PI-ARM-PLT-NEXT: 1818:         0f c0 8c e0     add     r12, r12, pc
+// CHECK-PI-ARM-PLT-NEXT: 181c:         00 f0 9c e5     ldr     pc, [r12]
+// CHECK-PI-ARM-PLT-NEXT: 1820:         94 00 00 00
+// 0x1828 + 8 + 0x88 = 0x18b8 arm_callee2
+// CHECK-PI-ARM-PLT-NEXT: 1824:         04 c0 9f e5     ldr     r12, [pc, #4]
+// CHECK-PI-ARM-PLT-NEXT: 1828:         0f c0 8c e0     add     r12, r12, pc
+// CHECK-PI-ARM-PLT-NEXT: 182c:         00 f0 9c e5     ldr     pc, [r12]
+// CHECK-PI-ARM-PLT-NEXT: 1830:         88 00 00 00
+// 0x1838 + 8 + 0x7c = 0x18bc arm_callee3
+// CHECK-PI-ARM-PLT-NEXT: 1834:         04 c0 9f e5     ldr     r12, [pc, #4]
+// CHECK-PI-ARM-PLT-NEXT: 1838:         0f c0 8c e0     add     r12, r12, pc
+// CHECK-PI-ARM-PLT-NEXT: 183c:         00 f0 9c e5     ldr     pc, [r12]
+// CHECK-PI-ARM-PLT-NEXT: 1840:         7c 00 00 00
+
+// CHECK-DSO-REL:      0x18A0 R_ARM_JUMP_SLOT arm_caller
+// CHECK-DSO-REL-NEXT: 0x18A4 R_ARM_JUMP_SLOT thumb_caller
+// CHECK-DSO-REL-NEXT: 0x18A8 R_ARM_JUMP_SLOT thumb_callee1
+// CHECK-DSO-REL-NEXT: 0x18AC R_ARM_JUMP_SLOT thumb_callee2
+// CHECK-DSO-REL-NEXT: 0x18B0 R_ARM_JUMP_SLOT thumb_callee3
+// CHECK-DSO-REL-NEXT: 0x18B4 R_ARM_JUMP_SLOT arm_callee1
+// CHECK-DSO-REL-NEXT: 0x18B8 R_ARM_JUMP_SLOT arm_callee2
+// CHECK-DSO-REL-NEXT: 0x18BC R_ARM_JUMP_SLOT arm_callee3