[AArch64] Switch regression tests to test features not CPUs

[sbaranga]

Summary

We have switched to using features for all heuristics, but
the tests for these are still using -mcpu, which means we
are not directly testing the features.

This converts at least some of the existing regression tests
to use the new features.

This still leaves the following features untested:

merge-narrow-ld
predictable-select-expensive
alternate-sextload-cvt-f32-pattern
disable-latency-sched-heuristic

[rengolin]

Hi Silviu,

I'm all for using target features, and that's a good way to make sure we test *all* CPUs, not just the one where the feature was introduced.

Do we also need a small test to show that certain CPUs still have certain features? I'm not sure how to do that, though.

cheers,
--renato

[sbaranga]

In D21288#456148, @rengolin wrote:

Hi Silviu,

I'm all for using target features, and that's a good way to make sure we test *all* CPUs, not just the one where the feature was introduced.

Do we also need a small test to show that certain CPUs still have certain features? I'm not sure how to do that, though.

cheers,
--renato

Perhaps. That's something that we're already missing for most (all?) CPUs for these heuristics?
The best idea i can come up with is to make SubtargetEmitter.cpp generate some debug code that will print all features.

Cheers,
Silviu

[rengolin]

In D21288#456185, @sbaranga wrote:

Perhaps. That's something that we're already missing for most (all?) CPUs for these heuristics?
The best idea i can come up with is to make SubtargetEmitter.cpp generate some debug code that will print all features.

How about we *add* tests on sub-target features, instead of replace, and change the CPU's Check lines to the flag's own, so that we're testing both features and CPU's support?

[sbaranga]

Keep the old tests, but add new ones which should be CPU independent and test the features.

[rengolin]

Hi Silviu,

I was thinking more in the lines of using the same CHECK lines, to make sure they don't diverge?

So, if you have Cyclone specific as well as FeatureX in Cyclone:

; RUN: ... cyclone ... FileCheck --check=FEATUREX --check=CYCLONE
; RUN: ... +FeatureX . FileCheck --check=FEATUREX

; CHECK-CYCLONE: cyclone-specific things (Target->isCyclone())
; CHECK-FEATUREX: Feature X things, including Cyclone

Makes sense?

cheers,
--renato

[sbaranga]

Hi Renato,

In D21288#463159, @rengolin wrote:

So, if you have Cyclone specific as well as FeatureX in Cyclone:

; RUN: ... cyclone ... FileCheck --check=FEATUREX --check=CYCLONE
; RUN: ... +FeatureX . FileCheck --check=FEATUREX

; CHECK-CYCLONE: cyclone-specific things (Target->isCyclone())
; CHECK-FEATUREX: Feature X things, including Cyclone

Makes sense?

It does, and I was trying to follow this already (see test/CodeGen/AArch64/misched-fusion.ll for example). Is there any place where you think the CHECK lines could be improved?

Cheers,
Silviu

[rengolin]

Ok, some inline comment to make my point more explicit. :)

Otherwise, looks good. Thanks!

test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll

87

Here, A57 has BalanceFPOps and could check for CHECK-BALFP rather than spit in A57 up there and GENERIC down here.

test/CodeGen/AArch64/merge-store.ll

13

These two sets of lines are identical because Cyclone has FeatureSlowMisaligned128Store, so the first RUN line could also check for CHECK-MISALIGNED instead of duplicate the CHECK lines or call it FAST.

test/CodeGen/AArch64/misched-fusion.ll

15

Duplicated, Cyclone has FeatureMacroOpFusion, call it CHECK-FUSION or something.

[sbaranga]

Address review comments from Renato.
Additionally, misched-fusion.ll now uses regex so we don't need different check prefixes.

[rengolin]

LGTM, thanks!

[sbaranga]

Thanks, r273271!

test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll

-; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A57 --check-prefix CHECK-EVEN
-; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A57 --check-prefix CHECK-ODD
+; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-BALFP --check-prefix CHECK-EVEN
+; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-BALFP --check-prefix CHECK-ODD
 ; RUN: llc < %s -mcpu=cortex-a53 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A53 --check-prefix CHECK-EVEN
 ; RUN: llc < %s -mcpu=cortex-a53 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A53 --check-prefix CHECK-ODD
 
+; The following tests use the balance-fp-ops feature, and should be independent of
+; the target cpu.
+
+; RUN: llc < %s -mtriple=aarch64-linux-gnueabi -mattr=+balance-fp-ops -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-EVEN --check-prefix CHECK-BALFP
+; RUN: llc < %s -mtriple=aarch64-linux-gnueabi -mattr=+balance-fp-ops  -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-ODD --check-prefix CHECK-BALFP
+
 ; Test the AArch64A57FPLoadBalancing pass. This pass relies heavily on register allocation, so
 ; our test strategy is to:
 ;   * Force the pass to always perform register swapping even if the dest register is of the
 ;     correct color already (-force-all)
 ;   * Force the pass to ignore all hints it obtained from regalloc (-deterministic-balance),
 ;     and run it twice, once where it always hints odd, and once where it always hints even.
 ;
 ; We then use regex magic to check that in the two cases the register allocation is

 ; CHECK-EVEN: fmul [[y:d[0-9]*[13579]]]
 ; CHECK-ODD: fmadd [[x:d[0-9]*[13579]]]
 ; CHECK-ODD: fmul [[y:d[0-9]*[02468]]]
 ; CHECK: fmadd [[x]]
 ; CHECK: fmadd [[y]]
 ; CHECK: fmsub [[x]]
 ; CHECK: fmadd [[y]]
 ; CHECK: fmadd [[x]]
-; CHECK-A57: stp [[x]], [[y]]
+; CHECK-BALFP: stp [[x]], [[y]]
 ; CHECK-A53-DAG: str [[x]]
 ; CHECK-A53-DAG: str [[y]]
 
 define void @f2(double* nocapture readonly %p, double* nocapture %q) #0 {
 entry:
   %0 = load double, double* %p, align 8
   %arrayidx1 = getelementptr inbounds double, double* %p, i64 1
   %1 = load double, double* %arrayidx1, align 8
   %arrayidx2 = getelementptr inbounds double, double* %p, i64 2
   %2 = load double, double* %arrayidx2, align 8
   %arrayidx3 = getelementptr inbounds double, double* %p, i64 3

 ; CHECK-EVEN: fmul [[y:s[0-9]*[13579]]]
 ; CHECK-ODD: fmadd [[x:s[0-9]*[13579]]]
 ; CHECK-ODD: fmul [[y:s[0-9]*[02468]]]
 ; CHECK: fmadd [[x]]
 ; CHECK: fmadd [[y]]
 ; CHECK: fmsub [[x]]
 ; CHECK: fmadd [[y]]
 ; CHECK: fmadd [[x]]
-; CHECK-A57: stp [[x]], [[y]]
+; CHECK-BALFP: stp [[x]], [[y]]
 ; CHECK-A53-DAG: str [[x]]
 ; CHECK-A53-DAG: str [[y]]
 
 define void @f4(float* nocapture readonly %p, float* nocapture %q) #0 {
 entry:
   %0 = load float, float* %p, align 4
   %arrayidx1 = getelementptr inbounds float, float* %p, i64 1
   %1 = load float, float* %arrayidx1, align 4

test/CodeGen/AArch64/aarch64-gep-opt.ll

 ; RUN: llc -O3 -aarch64-gep-opt=true -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -O3 -aarch64-gep-opt=true -mattr=-use-aa -print-after=codegenprepare < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-NoAA <%t %s
+; RUN: llc -O3 -aarch64-gep-opt=true -mattr=+use-aa -print-after=codegenprepare < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-UseAA <%t %s
 ; RUN: llc -O3 -aarch64-gep-opt=true -print-after=codegenprepare -mcpu=cyclone < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-NoAA <%t %s
 ; RUN: llc -O3 -aarch64-gep-opt=true -print-after=codegenprepare -mcpu=cortex-a53 < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-UseAA <%t %s
+
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-linux-gnueabi"
 
 ; Following test cases test enabling SeparateConstOffsetFromGEP pass in AArch64
 ; backend. If useAA() returns true, it will lower a GEP with multiple indices
 ; into GEPs with a single index, otherwise it will lower it into a
 ; "ptrtoint+arithmetics+inttoptr" form.
 

test/CodeGen/AArch64/exynos-quad-ldp-stp.ll

-; RUN: llc < %s -march=aarch64 -mcpu=exynos-m1 -verify-machineinstrs -asm-verbose=false | FileCheck %s
-
-; CHECK-LABEL: test_exynos_nopair_st
-; CHECK: str
-; CHECK: stur
-; CHECK-NOT: stp
-define void @test_exynos_nopair_st(double* %ptr, <2 x double> %v1, <2 x double> %v2) {
-  %tmp1 = bitcast double* %ptr to <2 x double>*
-  store <2 x double> %v2, <2 x double>* %tmp1, align 16
-  %add.ptr = getelementptr inbounds double, double* %ptr, i64 -2
-  %tmp = bitcast double* %add.ptr to <2 x double>*
-  store <2 x double> %v1, <2 x double>* %tmp, align 16
-  ret void
-}
-
-; CHECK-LABEL: test_exynos_nopair_ld
-; CHECK: ldr
-; CHECK: ldr
-; CHECK-NOT: ldp
-define <2 x i64> @test_exynos_nopair_ld(i64* %p) {
-  %a1 = bitcast i64* %p to <2 x i64>*
-  %tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8
-  %add.ptr2 = getelementptr inbounds i64, i64* %p, i64 2
-  %a2 = bitcast i64* %add.ptr2 to <2 x i64>*
-  %tmp2 = load <2 x i64>, <2 x i64>* %a2, align 8
-  %add = add nsw <2 x i64> %tmp1, %tmp2
-  ret <2 x i64> %add
-}

test/CodeGen/AArch64/merge-store-dependency.ll

+; RUN: llc -mcpu cortex-a53 -march aarch64 %s -o - | FileCheck %s --check-prefix=A53
+
+; PR26827 - Merge stores causes wrong dependency.
+%struct1 = type { %struct1*, %struct1*, i32, i32, i16, i16, void (i32, i32, i8*)*, i8* }
+@gv0 = internal unnamed_addr global i32 0, align 4
+@gv1 = internal unnamed_addr global %struct1** null, align 8
+
+define void @test(%struct1* %fde, i32 %fd, void (i32, i32, i8*)* %func, i8* %arg)  {
+;CHECK-LABEL: test
+entry:
+; A53: mov [[DATA:w[0-9]+]], w1
+; A53: str q{{[0-9]+}}, {{.*}}
+; A53: str q{{[0-9]+}}, {{.*}}
+; A53: str [[DATA]], {{.*}}
+
+  %0 = bitcast %struct1* %fde to i8*
+  tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 40, i32 8, i1 false)
+  %state = getelementptr inbounds %struct1, %struct1* %fde, i64 0, i32 4
+  store i16 256, i16* %state, align 8
+  %fd1 = getelementptr inbounds %struct1, %struct1* %fde, i64 0, i32 2
+  store i32 %fd, i32* %fd1, align 8
+  %force_eof = getelementptr inbounds %struct1, %struct1* %fde, i64 0, i32 3
+  store i32 0, i32* %force_eof, align 4
+  %func2 = getelementptr inbounds %struct1, %struct1* %fde, i64 0, i32 6
+  store void (i32, i32, i8*)* %func, void (i32, i32, i8*)** %func2, align 8
+  %arg3 = getelementptr inbounds %struct1, %struct1* %fde, i64 0, i32 7
+  store i8* %arg, i8** %arg3, align 8
+  %call = tail call i32 (i32, i32, ...) @fcntl(i32 %fd, i32 4, i8* %0) #6
+  %1 = load i32, i32* %fd1, align 8
+  %cmp.i = icmp slt i32 %1, 0
+  br i1 %cmp.i, label %if.then.i, label %while.body.i.preheader
+if.then.i:
+  unreachable
+
+while.body.i.preheader:
+  %2 = load i32, i32* @gv0, align 4
+  %3 = icmp eq i32* %fd1, @gv0
+  br i1 %3, label %while.body.i.split, label %while.body.i.split.ver.us.preheader
+
+while.body.i.split.ver.us.preheader:
+  br label %while.body.i.split.ver.us
+
+while.body.i.split.ver.us:
+  %.reg2mem21.0 = phi i32 [ %mul.i.ver.us, %while.body.i.split.ver.us ], [ %2, %while.body.i.split.ver.us.preheader ]
+  %mul.i.ver.us = shl nsw i32 %.reg2mem21.0, 1
+  %4 = icmp sgt i32 %mul.i.ver.us, %1
+  br i1 %4, label %while.end.i, label %while.body.i.split.ver.us
+
+while.body.i.split:
+  br label %while.body.i.split
+
+while.end.i:
+  %call.i = tail call i8* @foo()
+  store i8* %call.i, i8** bitcast (%struct1*** @gv1 to i8**), align 8
+  br label %exit
+
+exit:
+  ret void
+}
+
+declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1)
+declare i32 @fcntl(i32, i32, ...)
+declare noalias i8* @foo()

test/CodeGen/AArch64/merge-store.ll

-; RUN: llc -march aarch64 %s -o - | FileCheck %s
-; RUN: llc < %s -mtriple=aarch64-unknown-unknown  -mcpu=cyclone  | FileCheck %s --check-prefix=CYCLONE
-; RUN: llc -mcpu cortex-a53 -march aarch64 %s -o - | FileCheck %s --check-prefix=A53
+; RUN: llc -march aarch64 %s -mcpu=cyclone -o - | FileCheck %s --check-prefix=CYCLONE --check-prefix=CHECK
+; RUN: llc -march aarch64 %s -mattr=-slow-misaligned-128store -o - | FileCheck %s --check-prefix=MISALIGNED --check-prefix=CHECK
 
 @g0 = external global <3 x float>, align 16
 @g1 = external global <3 x float>, align 4
 
 ; CHECK: ldr s[[R0:[0-9]+]], {{\[}}[[R1:x[0-9]+]]{{\]}}, #4
 ; CHECK: ld1{{\.?s?}} { v[[R0]]{{\.?s?}} }[1], {{\[}}[[R1]]{{\]}}
 ; CHECK: str d[[R0]]
 
 define void @blam() {
   %tmp4 = getelementptr inbounds <3 x float>, <3 x float>* @g1, i64 0, i64 0
   %tmp5 = load <3 x float>, <3 x float>* @g0, align 16
   %tmp6 = extractelement <3 x float> %tmp5, i64 0
   store float %tmp6, float* %tmp4
   %tmp7 = getelementptr inbounds float, float* %tmp4, i64 1
   %tmp8 = load <3 x float>, <3 x float>* @g0, align 16
   %tmp9 = extractelement <3 x float> %tmp8, i64 1
   store float %tmp9, float* %tmp7
   ret void;
 }
define void @merge_vec_extract_stores(<4 x float> %v1, <2 x float>* %ptr) {
 
   %shuffle0 = shufflevector <4 x float> %v1, <4 x float> undef, <2 x i32> <i32 0, i32 1>
   %shuffle1 = shufflevector <4 x float> %v1, <4 x float> undef, <2 x i32> <i32 2, i32 3>
 
   store <2 x float> %shuffle0, <2 x float>* %idx0, align 8
   store <2 x float> %shuffle1, <2 x float>* %idx1, align 8
   ret void
 
-; CHECK-LABEL:    merge_vec_extract_stores
-; CHECK:          stur   q0, [x0, #24]
-; CHECK-NEXT:     ret
+; MISALIGNED-LABEL:    merge_vec_extract_stores
+; MISALIGNED:          stur   q0, [x0, #24]
+; MISALIGNED-NEXT:     ret
+
+; FIXME: Ideally we would like to use a generic target for this test, but this relies
+; on suppressing store pairs.
 
 ; CYCLONE-LABEL:    merge_vec_extract_stores
 ; CYCLONE:          ext   v1.16b, v0.16b, v0.16b, #8
 ; CYCLONE-NEXT:     str   d0, [x0, #24]
 ; CYCLONE-NEXT:     str   d1, [x0, #32]
 ; CYCLONE-NEXT:     ret
 }
-
-
-; PR26827 - Merge stores causes wrong dependency.
-%struct1 = type { %struct1*, %struct1*, i32, i32, i16, i16, void (i32, i32, i8*)*, i8* }
-@gv0 = internal unnamed_addr global i32 0, align 4
-@gv1 = internal unnamed_addr global %struct1** null, align 8
-
-define void @test(%struct1* %fde, i32 %fd, void (i32, i32, i8*)* %func, i8* %arg)  {
-;CHECK-LABEL: test
-entry:
-;A53: mov [[DATA:w[0-9]+]], w1
-;A53: str q{{[0-9]+}}, {{.*}}
-;A53: str q{{[0-9]+}}, {{.*}}
-;A53: str [[DATA]], {{.*}}
-
-  %0 = bitcast %struct1* %fde to i8*
-  tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 40, i32 8, i1 false)
-  %state = getelementptr inbounds %struct1, %struct1* %fde, i64 0, i32 4
-  store i16 256, i16* %state, align 8
-  %fd1 = getelementptr inbounds %struct1, %struct1* %fde, i64 0, i32 2
-  store i32 %fd, i32* %fd1, align 8
-  %force_eof = getelementptr inbounds %struct1, %struct1* %fde, i64 0, i32 3
-  store i32 0, i32* %force_eof, align 4
-  %func2 = getelementptr inbounds %struct1, %struct1* %fde, i64 0, i32 6
-  store void (i32, i32, i8*)* %func, void (i32, i32, i8*)** %func2, align 8
-  %arg3 = getelementptr inbounds %struct1, %struct1* %fde, i64 0, i32 7
-  store i8* %arg, i8** %arg3, align 8
-  %call = tail call i32 (i32, i32, ...) @fcntl(i32 %fd, i32 4, i8* %0) #6
-  %1 = load i32, i32* %fd1, align 8
-  %cmp.i = icmp slt i32 %1, 0
-  br i1 %cmp.i, label %if.then.i, label %while.body.i.preheader
-if.then.i:
-  unreachable
-
-while.body.i.preheader:
-  %2 = load i32, i32* @gv0, align 4
-  %3 = icmp eq i32* %fd1, @gv0
-  br i1 %3, label %while.body.i.split, label %while.body.i.split.ver.us.preheader
-
-while.body.i.split.ver.us.preheader:
-  br label %while.body.i.split.ver.us
-
-while.body.i.split.ver.us:
-  %.reg2mem21.0 = phi i32 [ %mul.i.ver.us, %while.body.i.split.ver.us ], [ %2, %while.body.i.split.ver.us.preheader ]
-  %mul.i.ver.us = shl nsw i32 %.reg2mem21.0, 1
-  %4 = icmp sgt i32 %mul.i.ver.us, %1
-  br i1 %4, label %while.end.i, label %while.body.i.split.ver.us
-
-while.body.i.split:
-  br label %while.body.i.split
-
-while.end.i:
-  %call.i = tail call i8* @foo()
-  store i8* %call.i, i8** bitcast (%struct1*** @gv1 to i8**), align 8
-  br label %exit
-
-exit:
-  ret void
-}
-
-declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1)
-declare i32 @fcntl(i32, i32, ...)
-declare noalias i8* @foo()

test/CodeGen/AArch64/misched-fusion.ll

+; RUN: llc -o - %s -mattr=+macroop-fusion,+use-postra-scheduler | FileCheck %s
 ; RUN: llc -o - %s -mcpu=cyclone | FileCheck %s
+
 target triple = "arm64-apple-ios"
 
 declare void @foobar(i32 %v0, i32 %v1)
 
 ; Make sure sub is scheduled in front of cbnz
 ; CHECK-LABEL: test_sub_cbz:
 ; CHECK: add w[[ADDRES:[0-9]+]], w1, #7
 ; CHECK: sub w[[SUBRES:[0-9]+]], w0, #13
 ; CHECK-NEXT: cbnz w[[SUBRES]], [[SKIPBLOCK:LBB[0-9_]+]]
-; CHECK: mov x0, x[[ADDRES]]
-; CHECK: mov x1, x[[SUBRES]]
+; CHECK: mov [[REGTY:[x,w]]]0, [[REGTY]][[ADDRES]]
+; CHECK: mov [[REGTY]]1, [[REGTY]][[SUBRES]]
 ; CHECK: bl _foobar
 ; CHECK: [[SKIPBLOCK]]:
-; CHECK: mov x0, x[[SUBRES]]
-; CHECK: mov x1, x[[ADDRES]]
+; CHECK: mov [[REGTY]]0, [[REGTY]][[SUBRES]]
+; CHECK: mov [[REGTY]]1, [[REGTY]][[ADDRES]]
 ; CHECK: bl _foobar
 define void @test_sub_cbz(i32 %a0, i32 %a1) {
 entry:
   ; except for the fusion opportunity the sub/add should be equal so the
   ; scheduler would leave them in source order if it weren't for the scheduling
   %v0 = sub i32 %a0, 13
   %cond = icmp eq i32 %v0, 0
   %v1 = add i32 %a1, 7

test/CodeGen/AArch64/no-quad-ldp-stp.ll

+; RUN: llc < %s -march=aarch64 -mattr=+no-quad-ldst-pairs -verify-machineinstrs -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -march=aarch64 -mcpu=exynos-m1 -verify-machineinstrs -asm-verbose=false | FileCheck %s
+
+; CHECK-LABEL: test_nopair_st
+; CHECK: str
+; CHECK: stur
+; CHECK-NOT: stp
+define void @test_nopair_st(double* %ptr, <2 x double> %v1, <2 x double> %v2) {
+  %tmp1 = bitcast double* %ptr to <2 x double>*
+  store <2 x double> %v2, <2 x double>* %tmp1, align 16
+  %add.ptr = getelementptr inbounds double, double* %ptr, i64 -2
+  %tmp = bitcast double* %add.ptr to <2 x double>*
+  store <2 x double> %v1, <2 x double>* %tmp, align 16
+  ret void
+}
+
+; CHECK-LABEL: test_nopair_ld
+; CHECK: ldr
+; CHECK: ldr
+; CHECK-NOT: ldp
+define <2 x i64> @test_nopair_ld(i64* %p) {
+  %a1 = bitcast i64* %p to <2 x i64>*
+  %tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8
+  %add.ptr2 = getelementptr inbounds i64, i64* %p, i64 2
+  %a2 = bitcast i64* %add.ptr2 to <2 x i64>*
+  %tmp2 = load <2 x i64>, <2 x i64>* %a2, align 8
+  %add = add nsw <2 x i64> %tmp1, %tmp2
+  ret <2 x i64> %add
+}

test/CodeGen/AArch64/remat.ll

 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a35 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a73 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m1 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=kryo -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=vulcan -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
 
 %X = type { i64, i64, i64 }
 declare void @f(%X*)
 define void @t() {
 entry:
   %tmp = alloca %X
   call void @f(%X* %tmp)
 ; CHECK: add x0, sp, #8
 ; CHECK-NOT: mov
 ; CHECK-NEXT: bl f
   call void @f(%X* %tmp)               
 ; CHECK: add x0, sp, #8
 ; CHECK-NOT: mov
 ; CHECK-NEXT: bl f
   ret void 
 }

test/CodeGen/AArch64/sqrt-fastmath.ll

 ; RUN: llc < %s -mtriple=aarch64 -mattr=neon -recip=!sqrt,!vec-sqrt | FileCheck %s --check-prefix=FAULT
 ; RUN: llc < %s -mtriple=aarch64 -mattr=neon -recip=sqrt,vec-sqrt   | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -mattr=neon,-use-reverse-square-root  | FileCheck %s --check-prefix=FAULT
+; RUN: llc < %s -mtriple=aarch64 -mattr=neon,+use-reverse-square-root | FileCheck %s
 
 declare float @llvm.sqrt.f32(float) #1
 declare double @llvm.sqrt.f64(double) #1
 declare <2 x float> @llvm.sqrt.v2f32(<2 x float>) #1
 declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1
 declare <2 x double> @llvm.sqrt.v2f64(<2 x double>) #1
 
 define float @fsqrt(float %a) #0 {