[X86]: Quit promoting 8 and 16 bit compares to 32 bit.

[kbsmith1]

Summary

This change effectively just reverts r195496, and updates the tests as needed.
8 and 16 bit compares no longer promoted up into 32 bit compares. This has some
nice performance improvements, especially in eembc/rgbcmykv2. In order for this
not to cause performance regressions in 401.bzip2, changes http://reviews.llvm.org/D21085
are also necessary to get all the necessary movb and movw instructions promoted to
movzbl/movzwl.

[echristo]

We talked about this on the list, but getting an explicit ack from Jim.

-eric

[eli.friedman]

test/CodeGen/X86/memcmp.ll

44 ↗

(On Diff #60068)

16-bit immediate operands are bad for performance on modern x86.

[kbsmith1]

test/CodeGen/X86/memcmp.ll

44 ↗

(On Diff #60068)

I'm looking into changing the code so that 16 bit compares which have a constant operand will continue to get promoted, and how that affects the performance numbers.

[kbsmith1]

Updated changes so this will continue to promote 16 bit compares to 32 bits if one of the compare
operands is a constant. This addresses Eli Friedman's comment.

[danielcdh]

In D21144#453975, @kbsmith1 wrote:

Updated changes so this will continue to promote 16 bit compares to 32 bits if one of the compare
operands is a constant. This addresses Eli Friedman's comment.

Yes, 16bit immediate constant may introduce LCP that may end up hurting performance. But on newer architectures (sandybridge and later), this problem is much less severe, especially when the loop body fits in LSD. I don't think it's a good idea to blindly convert all 16bit immediate constant comparison to 32bit.

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

bool X86::isCalleePop(CallingConv::ID CallingConv,
   case CallingConv::X86_StdCall:
   case CallingConv::X86_FastCall:
   case CallingConv::X86_ThisCall:
   case CallingConv::X86_VectorCall:
     return !is64Bit;
   }
 }
 
-/// \brief Return true if the condition is an unsigned comparison operation.
-static bool isX86CCUnsigned(unsigned X86CC) {
-  switch (X86CC) {
-  default:
-    llvm_unreachable("Invalid integer condition!");
-  case X86::COND_E:
-  case X86::COND_NE:
-  case X86::COND_B:
-  case X86::COND_A:
-  case X86::COND_BE:
-  case X86::COND_AE:
-    return true;
-  case X86::COND_G:
-  case X86::COND_GE:
-  case X86::COND_L:
-  case X86::COND_LE:
-    return false;
-  }
-}
-
 static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
   switch (SetCCOpcode) {
   default: llvm_unreachable("Invalid integer condition!");
   case ISD::SETEQ:  return X86::COND_E;
   case ISD::SETGT:  return X86::COND_G;
   case ISD::SETGE:  return X86::COND_GE;
   case ISD::SETLT:  return X86::COND_L;
   case ISD::SETLE:  return X86::COND_LE;
SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
   if (isNullConstant(Op1))
     return EmitTest(Op0, X86CC, dl, DAG);
 
   assert(!(isa<ConstantSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
          "Unexpected comparison operation for MVT::i1 operands");
 
   if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
        Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
-    // Do the comparison at i32 if it's smaller, besides the Atom case.
-    // This avoids subregister aliasing issues. Keep the smaller reference
-    // if we're optimizing for size, however, as that'll allow better folding
-    // of memory operations.
-    if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
-        !DAG.getMachineFunction().getFunction()->optForMinSize() &&
-        !Subtarget.isAtom()) {
-      unsigned ExtendOp =
-          isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
-      Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
-      Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
-    }
     // Use SUB instead of CMP to enable CSE between SUB and CMP.
     SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
     SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
                               Op0, Op1);
     return SDValue(Sub.getNode(), 1);
   }
   return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
 }

llvm/trunk/test/CodeGen/X86/3addr-16bit.ll

 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -asm-verbose=false | FileCheck %s -check-prefix=64BIT
 ; rdar://7329206
 
 ; In 32-bit the partial register stall would degrade performance.
 
 define zeroext i16 @t1(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
 entry:
 ; 32BIT-LABEL:     t1:
 ; 32BIT:     movw 20(%esp), %ax
 ; 32BIT-NOT: movw %ax, %cx
 ; 32BIT:     leal 1(%eax), %ecx
 
 ; 64BIT-LABEL:     t1:
 ; 64BIT-NOT: movw %si, %ax
-; 64BIT:     leal 1(%rsi), %eax
+; 64BIT:     movl %esi, %eax
   %0 = icmp eq i16 %k, %c                         ; <i1> [#uses=1]
   %1 = add i16 %k, 1                              ; <i16> [#uses=3]
   br i1 %0, label %bb, label %bb1
 
 bb:                                               ; preds = %entry
   tail call void @foo(i16 zeroext %1) nounwind
   ret i16 %1
 
 bb1:                                              ; preds = %entry
   ret i16 %1
 }
 
 define zeroext i16 @t2(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
 entry:
 ; 32BIT-LABEL:     t2:
 ; 32BIT:     movw 20(%esp), %ax
 ; 32BIT-NOT: movw %ax, %cx
 ; 32BIT:     leal -1(%eax), %ecx
 
 ; 64BIT-LABEL:     t2:
 ; 64BIT-NOT: movw %si, %ax
-; 64BIT:     leal -1(%rsi), %eax
+; 64BIT:     movl %esi, %eax
 ; 64BIT:     movzwl %ax
   %0 = icmp eq i16 %k, %c                         ; <i1> [#uses=1]
   %1 = add i16 %k, -1                             ; <i16> [#uses=3]
   br i1 %0, label %bb, label %bb1
 
 bb:                                               ; preds = %entry
   tail call void @foo(i16 zeroext %1) nounwind
   ret i16 %1
 
 bb1:                                              ; preds = %entry
   ret i16 %1
 }
 
 declare void @foo(i16 zeroext)
 
 define zeroext i16 @t3(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
 entry:
 ; 32BIT-LABEL:     t3:
 ; 32BIT:     movw 20(%esp), %ax
 ; 32BIT-NOT: movw %ax, %cx
 ; 32BIT:     leal 2(%eax), %ecx
 
 ; 64BIT-LABEL:     t3:
 ; 64BIT-NOT: movw %si, %ax
-; 64BIT:     leal 2(%rsi), %eax
+; 64BIT:     movl %esi, %eax
   %0 = add i16 %k, 2                              ; <i16> [#uses=3]
   %1 = icmp eq i16 %k, %c                         ; <i1> [#uses=1]
   br i1 %1, label %bb, label %bb1
 
 bb:                                               ; preds = %entry
   tail call void @foo(i16 zeroext %0) nounwind
   ret i16 %0
 
 bb1:                                              ; preds = %entry
   ret i16 %0
 }
 
 define zeroext i16 @t4(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
 entry:
 ; 32BIT-LABEL:     t4:
 ; 32BIT:     movw 16(%esp), %ax
 ; 32BIT:     movw 20(%esp), %cx
 ; 32BIT-NOT: movw %cx, %dx
 ; 32BIT:     leal (%ecx,%eax), %edx
 
 ; 64BIT-LABEL:     t4:
 ; 64BIT-NOT: movw %si, %ax
-; 64BIT:     leal (%rsi,%rdi), %eax
+; 64BIT:     movl %esi, %eax
   %0 = add i16 %k, %c                             ; <i16> [#uses=3]
   %1 = icmp eq i16 %k, %c                         ; <i1> [#uses=1]
   br i1 %1, label %bb, label %bb1
 
 bb:                                               ; preds = %entry
   tail call void @foo(i16 zeroext %0) nounwind
   ret i16 %0
 
 bb1:                                              ; preds = %entry
   ret i16 %0
 }

llvm/trunk/test/CodeGen/X86/atomic16.ll

 ; X32:       lock
 ; X32:       cmpxchgw
   ret void
 ; X64:       ret
 ; X32:       ret
 }
 
 define void @atomic_fetch_max16(i16 %x) nounwind {
+; X64-LABEL:   atomic_fetch_max16
+; X32-LABEL:   atomic_fetch_max16
   %t1 = atomicrmw max  i16* @sc16, i16 %x acquire
-; X64:       movswl
-; X64:       movswl
-; X64:       subl
+; X64:       movw
+; X64:       movw
+; X64:       subw
 ; X64:       cmov
 ; X64:       lock
 ; X64:       cmpxchgw
 
-; X32:       movswl
-; X32:       movswl
-; X32:       subl
+; X32:       movw
+; X32:       movw
+; X32:       subw
 ; X32:       cmov
 ; X32:       lock
 ; X32:       cmpxchgw
   ret void
 ; X64:       ret
 ; X32:       ret
 }
 
 define void @atomic_fetch_min16(i16 %x) nounwind {
+; X64-LABEL:   atomic_fetch_min16
+; X32-LABEL:   atomic_fetch_min16
   %t1 = atomicrmw min  i16* @sc16, i16 %x acquire
-; X64:       movswl
-; X64:       movswl
-; X64:       subl
+; X64:       movw
+; X64:       movw
+; X64:       subw
 ; X64:       cmov
 ; X64:       lock
 ; X64:       cmpxchgw
 
-; X32:       movswl
-; X32:       movswl
-; X32:       subl
+; X32:       movw
+; X32:       movw
+; X32:       subw
 ; X32:       cmov
 ; X32:       lock
 ; X32:       cmpxchgw
   ret void
 ; X64:       ret
 ; X32:       ret
 }
 
 define void @atomic_fetch_umax16(i16 %x) nounwind {
+; X64-LABEL:   atomic_fetch_umax16
+; X32-LABEL:   atomic_fetch_umax16
   %t1 = atomicrmw umax i16* @sc16, i16 %x acquire
-; X64:       movzwl
-; X64:       movzwl
-; X64:       subl
+; X64:       movw
+; X64:       movw
+; X64:       subw
 ; X64:       cmov
 ; X64:       lock
 ; X64:       cmpxchgw
 
-; X32:       movzwl
-; X32:       movzwl
-; X32:       subl
+; X32:       movw
+; X32:       movw
+; X32:       subw
 ; X32:       cmov
 ; X32:       lock
 ; X32:       cmpxchgw
   ret void
 ; X64:       ret
 ; X32:       ret
 }
 
 define void @atomic_fetch_umin16(i16 %x) nounwind {
+; X64-LABEL:   atomic_fetch_umin16
+; X32-LABEL:   atomic_fetch_umin16
   %t1 = atomicrmw umin i16* @sc16, i16 %x acquire
-; X64:       movzwl
-; X64:       movzwl
-; X64:       subl
+; X64:       movw
+; X64:       movw
+; X64:       subw
 ; X64:       cmov
 ; X64:       lock
 ; X64:       cmpxchgw
 
-; X32:       movzwl
-; X32:       movzwl
-; X32:       subl
+; X32:       movw
+; X32:       movw
+; X32:       subw
 ; X32:       cmov
 ; X32:       lock
 ; X32:       cmpxchgw
   ret void
 ; X64:       ret
 ; X32:       ret
 }
 

llvm/trunk/test/CodeGen/X86/atomic8.ll

 ; X64:       ret
 ; X32:       ret
 }
 
 define void @atomic_fetch_max8(i8 %x) nounwind {
 ; X64-LABEL:   atomic_fetch_max8:
 ; X32-LABEL:   atomic_fetch_max8:
   %t1 = atomicrmw max  i8* @sc8, i8 %x acquire
-; X64:       movsbl
-; X64:       movsbl
-; X64:       subl
+; X64:       movb
+; X64:       movb
+; X64:       subb
 ; X64:       lock
 ; X64:       cmpxchgb
 
-; X32:       movsbl
-; X32:       movsbl
-; X32:       subl
+; X32:       movb
+; X32:       movb
+; X32:       subb
 ; X32:       lock
 ; X32:       cmpxchgb
   ret void
 ; X64:       ret
 ; X32:       ret
 }
 
 define void @atomic_fetch_min8(i8 %x) nounwind {
 ; X64-LABEL:   atomic_fetch_min8:
 ; X32-LABEL:   atomic_fetch_min8:
   %t1 = atomicrmw min  i8* @sc8, i8 %x acquire
-; X64:       movsbl
-; X64:       movsbl
-; X64:       subl
+; X64:       movb
+; X64:       movb
+; X64:       subb
 ; X64:       lock
 ; X64:       cmpxchgb
 
-; X32:       movsbl
-; X32:       movsbl
-; X32:       subl
+; X32:       movb
+; X32:       movb
+; X32:       subb
 ; X32:       lock
 ; X32:       cmpxchgb
   ret void
 ; X64:       ret
 ; X32:       ret
 }
 
 define void @atomic_fetch_umax8(i8 %x) nounwind {
 ; X64-LABEL:   atomic_fetch_umax8:
 ; X32-LABEL:   atomic_fetch_umax8:
   %t1 = atomicrmw umax i8* @sc8, i8 %x acquire
-; X64:       movzbl
-; X64:       movzbl
-; X64:       subl
+; X64:       movb
+; X64:       movb
+; X64:       subb
 ; X64:       lock
 ; X64:       cmpxchgb
 
-; X32:       movzbl
-; X32:       movzbl
-; X32:       subl
+; X32:       movb
+; X32:       movb
+; X32:       subb
 ; X32:       lock
 ; X32:       cmpxchgb
   ret void
 ; X64:       ret
 ; X32:       ret
 }
 
 define void @atomic_fetch_umin8(i8 %x) nounwind {
 ; X64-LABEL:   atomic_fetch_umin8:
 ; X32-LABEL:   atomic_fetch_umin8:
   %t1 = atomicrmw umin i8* @sc8, i8 %x acquire
-; X64:       movzbl
-; X64:       movzbl
-; X64:       subl
+; X64:       movb
+; X64:       movb
+; X64:       subb
 ; X64:       lock
 ; X64:       cmpxchgb
 
-; X32:       movzbl
-; X32:       movzbl
-; X32:       subl
+; X32:       movb
+; X32:       movb
+; X32:       subb
 ; X32:       lock
 ; X32:       cmpxchgb
   ret void
 ; X64:       ret
 ; X32:       ret
 }
 
 define void @atomic_fetch_cmpxchg8() nounwind {

llvm/trunk/test/CodeGen/X86/ctpop-combine.ll

 
 define i32 @test3(i64 %x) nounwind readnone {
   %count = tail call i64 @llvm.ctpop.i64(i64 %x)
   %cast = trunc i64 %count to i6 ; Too small for 0-64
   %cmp = icmp ult i6 %cast, 2
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 ; CHECK-LABEL: test3:
-; CHECK: cmpl $2
+; CHECK: cmpb $2
 ; CHECK: ret
 }

llvm/trunk/test/CodeGen/X86/machine-sink-and-implicit-null-checks.ll

 }
 
 ; Check that we have two implicit null checks in @f
 
 ; CHECK: __LLVM_FaultMaps:
 ; CHECK-NEXT:        .byte   1
 ; CHECK-NEXT:        .byte   0
 ; CHECK-NEXT:        .short  0
-; CHECK-NEXT:        .long   2
+; CHECK-NEXT:        .long   1
 
 ; FunctionInfo[0] =
 
 ; FunctionAddress =
 ; CHECK-NEXT:        .quad   _f
 
 ; NumFaultingPCs =
 ; CHECK-NEXT:        .long   2
 
 ; Reserved =
 ; CHECK-NEXT:        .long   0
 
 !0 = !{}

llvm/trunk/test/CodeGen/X86/memcmp.ll

 bb:                                               ; preds = %entry
   store i32 4, i32* %P, align 4
   ret void
 
 return:                                           ; preds = %entry
   ret void
 ; CHECK-LABEL: memcmp2:
 ; CHECK: movzwl
-; CHECK-NEXT: movzwl
-; CHECK-NEXT: cmpl
+; CHECK-NEXT: cmpw
 ; NOBUILTIN-LABEL: memcmp2:
 ; NOBUILTIN: callq
 }
 
 define void @memcmp2a(i8* %X, i32* nocapture %P) nounwind {
 entry:
   %0 = tail call i32 (...) @memcmp(i8* %X, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @.str, i32 0, i32 1), i32 2) nounwind ; <i32> [#uses=1]
   %1 = icmp eq i32 %0, 0                          ; <i1> [#uses=1]
   br i1 %1, label %return, label %bb
 
 bb:                                               ; preds = %entry
   store i32 4, i32* %P, align 4
   ret void
 
 return:                                           ; preds = %entry
   ret void
 ; CHECK-LABEL: memcmp2a:
-; CHECK: movzwl
-; CHECK-NEXT: cmpl    $28527,
+; CHECK: cmpw $28527, (%
 }
 
 
 define void @memcmp4(i8* %X, i8* %Y, i32* nocapture %P) nounwind {
 entry:
   %0 = tail call i32 (...) @memcmp(i8* %X, i8* %Y, i32 4) nounwind ; <i32> [#uses=1]
   %1 = icmp eq i32 %0, 0                          ; <i1> [#uses=1]
   br i1 %1, label %return, label %bb

llvm/trunk/test/CodeGen/X86/pr5145.ll

 ; RUN: llc -march=x86-64 < %s | FileCheck %s
 @sc8 = external global i8
 
 define void @atomic_maxmin_i8() {
 ; CHECK: atomic_maxmin_i8
   %1 = atomicrmw max  i8* @sc8, i8 5 acquire
 ; CHECK: [[LABEL1:\.?LBB[0-9]+_[0-9]+]]:
-; CHECK: movsbl
-; CHECK: cmpl
+; CHECK: cmpb
+; CHECK: jg
 ; CHECK: lock cmpxchgb
 ; CHECK: jne [[LABEL1]]
   %2 = atomicrmw min  i8* @sc8, i8 6 acquire
 ; CHECK: [[LABEL3:\.?LBB[0-9]+_[0-9]+]]:
-; CHECK: movsbl
-; CHECK: cmpl
+; CHECK: cmpb
+; CHECK: jl
 ; CHECK: lock cmpxchgb
 ; CHECK: jne [[LABEL3]]
   %3 = atomicrmw umax i8* @sc8, i8 7 acquire
 ; CHECK: [[LABEL5:\.?LBB[0-9]+_[0-9]+]]:
-; CHECK: movzbl
-; CHECK: cmpl
+; CHECK: cmpb
+; CHECK: ja
 ; CHECK: lock cmpxchgb
 ; CHECK: jne [[LABEL5]]
   %4 = atomicrmw umin i8* @sc8, i8 8 acquire
 ; CHECK: [[LABEL7:\.?LBB[0-9]+_[0-9]+]]:
-; CHECK: movzbl
-; CHECK: cmpl
+; CHECK: cmpb
+; CHECK: jb
 ; CHECK: lock cmpxchgb
 ; CHECK: jne [[LABEL7]]
   ret void
 }

llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll

 declare hidden fastcc %struct.temp_slot* @find_temp_slot_from_address(%struct.rtx_def* readonly)
 
 ; CHECK-LABEL: useLEA:
 ; DISABLE: pushq 
 ;
 ; CHECK: testq   %rdi, %rdi
 ; CHECK-NEXT: je      [[CLEANUP:LBB[0-9_]+]]
 ;
-; CHECK: movzwl  (%rdi), [[BF_LOAD:%e[a-z]+]]
-; CHECK-NEXT: cmpl $66, [[BF_LOAD]]
+; CHECK: cmpw $66, (%rdi)
 ; CHECK-NEXT: jne [[CLEANUP]]
 ;
 ; CHECK: movq 8(%rdi), %rdi
 ; CHECK-NEXT: movzwl (%rdi), %e[[BF_LOAD2:[a-z]+]]
 ; CHECK-NEXT: leal -54(%r[[BF_LOAD2]]), [[TMP:%e[a-z]+]]
 ; CHECK-NEXT: cmpl $14, [[TMP]]
 ; CHECK-NEXT: ja [[LOR_LHS_FALSE:LBB[0-9_]+]]
 ;