This is an archive of the discontinued LLVM Phabricator instance.

Differential D21077

[ARM] Accept conditional versions of BXNS and BLXNS
ClosedPublic

Authored by olista01 on Jun 7 2016, 7:45 AM.

Details

Reviewers
bsmith
rengolin
t.p.northover
jmolloy
Commits
rG8de5f24d1085: [ARM] Accept conditional versions of BXNS and BLXNS
rL272015: [ARM] Accept conditional versions of BXNS and BLXNS
Summary

These instructions end in "S" but are not flag-setting, so they need including in the list of special cases in the assembly parser.

Diff Detail

Repository
rL LLVM

Event Timeline

olista01 updated this revision to Diff 59889.Jun 7 2016, 7:45 AM
olista01 retitled this revision from to [ARM] Accept conditional versions of BXNS and BLXNS.
olista01 updated this object.
olista01 added reviewers: rengolin, t.p.northover, bsmith.
olista01 set the repository for this revision to rL LLVM.
olista01 added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson. · View Herald TranscriptJun 7 2016, 7:45 AM
jmolloy accepted this revision.Jun 7 2016, 7:50 AM
jmolloy added a reviewer: jmolloy.
jmolloy added a subscriber: jmolloy.

LGTM!

This revision is now accepted and ready to land.Jun 7 2016, 7:50 AM
Closed by commit rL272015: [ARM] Accept conditional versions of BXNS and BLXNS (authored by olista01). · Explain WhyJun 7 2016, 8:05 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
ARM/
AsmParser/
1 line
test/
MC/
ARM/
14 lines

Diff 59892

llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,414 Lines • ▼ Show 20 Lines if (Mnemonic.endswith("s") &&
Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" || Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
Mnemonic == "bxns" || Mnemonic == "blxns" ||
(Mnemonic == "movs" && isThumb()))) { (Mnemonic == "movs" && isThumb()))) {
Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
CarrySetting = true; CarrySetting = true;
} }
// The "cps" instruction can have a interrupt mode operand which is glued into // The "cps" instruction can have a interrupt mode operand which is glued into
// the mnemonic. Check if this is the case, split it and parse the imod op // the mnemonic. Check if this is the case, split it and parse the imod op
if (Mnemonic.startswith("cps")) { if (Mnemonic.startswith("cps")) {
▲ Show 20 Lines • Show All 4,844 Lines • Show Last 20 Lines

llvm/trunk/test/MC/ARM/thumbv8m.s

Show First 20 Lines • Show All 140 Lines • ▼ Show 20 Lines
// ARMv8-M Security Extensions // ARMv8-M Security Extensions
// CHECK: sg @ encoding: [0x7f,0xe9,0x7f,0xe9] // CHECK: sg @ encoding: [0x7f,0xe9,0x7f,0xe9]
sg sg
// CHECK: bxns r0 @ encoding: [0x04,0x47] // CHECK: bxns r0 @ encoding: [0x04,0x47]
bxns r0 bxns r0
// UNDEF-BASELINE: error: invalid operand for instruction
// UNDEF-BASELINE: error: conditional execution not supported in Thumb1
// CHECK-MAINLINE: it eq @ encoding: [0x08,0xbf]
// CHECK-MAINLINE: bxnseq r1 @ encoding: [0x0c,0x47]
it eq
bxnseq r1
// CHECK: bxns lr @ encoding: [0x74,0x47] // CHECK: bxns lr @ encoding: [0x74,0x47]
bxns lr bxns lr
// CHECK: blxns r0 @ encoding: [0x84,0x47] // CHECK: blxns r0 @ encoding: [0x84,0x47]
blxns r0 blxns r0
// UNDEF-BASELINE: error: invalid operand for instruction
// UNDEF-BASELINE: error: conditional execution not supported in Thumb1
// CHECK-MAINLINE: it eq @ encoding: [0x08,0xbf]
// CHECK-MAINLINE: blxnseq r1 @ encoding: [0x8c,0x47]
it eq
blxnseq r1
// CHECK: tt r0, r1 @ encoding: [0x41,0xe8,0x00,0xf0] // CHECK: tt r0, r1 @ encoding: [0x41,0xe8,0x00,0xf0]
tt r0, r1 tt r0, r1
// CHECK: tt r0, sp @ encoding: [0x4d,0xe8,0x00,0xf0] // CHECK: tt r0, sp @ encoding: [0x4d,0xe8,0x00,0xf0]
tt r0, sp tt r0, sp
// CHECK: tta r0, r1 @ encoding: [0x41,0xe8,0x80,0xf0] // CHECK: tta r0, r1 @ encoding: [0x41,0xe8,0x80,0xf0]
tta r0, r1 tta r0, r1
▲ Show 20 Lines • Show All 106 Lines • Show Last 20 Lines