ARM: Add additional matching for UBFX instructions.

[dmgreen]

Summary

This adds an additional matcher to select UBFX(..) from SRL(AND(..)) in ARMISelDAGToDAG to help with code size.

[jmolloy]

Hi David,

This looks good generally to me. But is there an obvious way to extend this to handle SBFX as well?

James

[dmgreen]

Hey James, cheers for taking a look at this.

For adding SBFX support; there might some cases to do with sign extending i16/i8's, but are probably quite limited in scope. The top bit of the AND would need to be set. Most such sequences of an AND+ASR are already either optimised to an AND+LSR, so will get caught by this change, or end up as just an ASR as the AND becomes superfluous.

This change was motivated by code like this:

int example(unsigned int x, unsigned int *y) {
    if (x == 1) {
        return (*y & (1 << 5U)) != 0;
    } else if (x == 2) {
        return (*y & (1 << 6U)) != 0;
    }
    return 0;
}

which was coming through as an AND+LSR. I made it a little more general to handle shifted mask AND operands, not just powers of 2, but in this case SBFX isn't as useful.

[jmolloy]

Thanks for the clarification David.

This LGTM.

llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp

if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
                         CurDAG->getTargetConstant(LSB, dl, MVT::i32),
                         CurDAG->getTargetConstant(Width, dl, MVT::i32),
                         getAL(CurDAG, dl), Reg0 };
       CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
       return true;
     }
   }
 
+  // Or we are looking for a shift of an and, with a mask operand
+  if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, And_imm) &&
+      isShiftedMask_32(And_imm)) {
+    unsigned Srl_imm = 0;
+    unsigned LSB = countTrailingZeros(And_imm);
+    // Shift must be the same as the ands lsb
+    if (isInt32Immediate(N->getOperand(1), Srl_imm) && Srl_imm == LSB) {
+      assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
+      unsigned MSB = 31 - countLeadingZeros(And_imm);
+      // Note: The width operand is encoded as width-1.
+      unsigned Width = MSB - LSB;
+      SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
+      SDValue Ops[] = { N->getOperand(0).getOperand(0),
+                        CurDAG->getTargetConstant(Srl_imm, dl, MVT::i32),
+                        CurDAG->getTargetConstant(Width, dl, MVT::i32),
+                        getAL(CurDAG, dl), Reg0 };
+      CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
+      return true;
+    }
+  }
+
   if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {
     unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
     unsigned LSB = 0;
     if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL, LSB) &&
         !isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRA, LSB))
       return false;
 
     if (LSB + Width > 32)

llvm/trunk/test/CodeGen/ARM/bfx.ll

; CHECK: ldr {{lr|r[0-9]+}}, [r0, [[REG3]], lsl #2]
   %arrayidx5 = getelementptr inbounds i32, i32* %ctx, i32 %shr2
   %1 = load i32, i32* %arrayidx5, align 4
   %add = add i32 %1, %0
   %arrayidx6 = getelementptr inbounds i32, i32* %ctx, i32 %shr
   %2 = load i32, i32* %arrayidx6, align 4
   %add7 = add i32 %add, %2
   ret i32 %add7
 }
+
+define i32 @ubfx3(i32 %a) {
+; CHECK: ubfx3
+; CHECK: ubfx r0, r0, #11, #1
+  %t1 = and i32 %a, 2048
+  %t2 = lshr i32 %t1, 11
+  ret i32 %t2
+}
+
+define i32 @ubfx4(i32 %a) {
+; CHECK: ubfx4
+; CHECK: ubfx r0, r0, #7, #3
+  %t1 = and i32 %a, 896
+  %t2 = lshr i32 %t1, 7
+  ret i32 %t2
+}